1148 lines
39 KiB
C++
1148 lines
39 KiB
C++
/* Definitions of target machine for GNU compiler. LoongArch version.
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Copyright (C) 2021-2022 Free Software Foundation, Inc.
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Contributed by Loongson Ltd.
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Based on MIPS and RISC-V target for GNU compiler.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* LoongArch external variables defined in loongarch.cc. */
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#include "config/loongarch/loongarch-opts.h"
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/* Macros to silence warnings about numbers being signed in traditional
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C and unsigned in ISO C when compiled on 32-bit hosts. */
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#define BITMASK_HIGH (((unsigned long) 1) << 31) /* 0x80000000 */
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/* Run-time compilation parameters selecting different hardware subsets. */
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/* Target CPU builtins. */
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#define TARGET_CPU_CPP_BUILTINS() loongarch_cpu_cpp_builtins (pfile)
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/* Default target_flags if no switches are specified. */
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#ifdef IN_LIBGCC2
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#undef TARGET_64BIT
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/* Make this compile time constant for libgcc2. */
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#ifdef __loongarch64
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#define TARGET_64BIT 1
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#else
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#define TARGET_64BIT 0
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#endif
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#endif /* IN_LIBGCC2 */
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#define TARGET_LIBGCC_SDATA_SECTION ".sdata"
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/* Driver native functions for SPEC processing in the GCC driver. */
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#include "loongarch-driver.h"
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/* This definition replaces the formerly used 'm' constraint with a
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different constraint letter in order to avoid changing semantics of
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the 'm' constraint when accepting new address formats in
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TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here
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must not be used in insn definitions or inline assemblies. */
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#define TARGET_MEM_CONSTRAINT 'w'
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/* Tell collect what flags to pass to nm. */
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#ifndef NM_FLAGS
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#define NM_FLAGS "-Bn"
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#endif
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/* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
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overridden by subtargets. */
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#ifndef SUBTARGET_ASM_SPEC
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#define SUBTARGET_ASM_SPEC ""
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#endif
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#undef ASM_SPEC
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#define ASM_SPEC "%{mabi=*} %{subtarget_asm_spec}"
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/* Extra switches sometimes passed to the linker. */
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#ifndef LINK_SPEC
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#define LINK_SPEC ""
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#endif /* LINK_SPEC defined */
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/* Specs for the compiler proper. */
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/* CC1_SPEC is the set of arguments to pass to the compiler proper. */
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#undef CC1_SPEC
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#define CC1_SPEC "\
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%{G*} \
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%(subtarget_cc1_spec)"
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/* Preprocessor specs. */
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/* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
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overridden by subtargets. */
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#ifndef SUBTARGET_CPP_SPEC
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#define SUBTARGET_CPP_SPEC ""
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#endif
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#define CPP_SPEC "%(subtarget_cpp_spec)"
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/* This macro defines names of additional specifications to put in the specs
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that can be used in various specifications like CC1_SPEC. Its definition
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is an initializer with a subgrouping for each command option.
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Each subgrouping contains a string constant, that defines the
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specification name, and a string constant that used by the GCC driver
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program.
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Do not define this macro if it does not need to do anything. */
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#define EXTRA_SPECS \
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{"subtarget_cc1_spec", SUBTARGET_CC1_SPEC}, \
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{"subtarget_cpp_spec", SUBTARGET_CPP_SPEC}, \
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{"subtarget_asm_spec", SUBTARGET_ASM_SPEC},
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/* Registers may have a prefix which can be ignored when matching
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user asm and register definitions. */
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#ifndef REGISTER_PREFIX
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#define REGISTER_PREFIX "$"
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#endif
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/* Local compiler-generated symbols must have a prefix that the assembler
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understands. */
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#define LOCAL_LABEL_PREFIX "."
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/* By default on the loongarch, external symbols do not have an underscore
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prepended. */
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#define USER_LABEL_PREFIX ""
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#ifndef PREFERRED_DEBUGGING_TYPE
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#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
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#endif
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/* The size of DWARF addresses should be the same as the size of symbols
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in the target file format. */
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#define DWARF2_ADDR_SIZE (TARGET_64BIT ? 8 : 4)
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/* By default, turn on GDB extensions. */
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#define DEFAULT_GDB_EXTENSIONS 1
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/* By default, produce dwarf version 2 format debugging output in response
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to the ‘-g’ option. */
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#define DWARF2_DEBUGGING_INFO 1
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/* The mapping from gcc register number to DWARF 2 CFA column number. */
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#define DWARF_FRAME_REGNUM(REGNO) loongarch_dwarf_regno[REGNO]
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/* The DWARF 2 CFA column which tracks the return address. */
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#define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
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/* Before the prologue, RA lives in r1. */
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#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
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/* Describe how we implement __builtin_eh_return. */
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#define EH_RETURN_DATA_REGNO(N) \
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((N) < (4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
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#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
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#define EH_USES(N) loongarch_eh_uses (N)
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/* Offsets recorded in opcodes are a multiple of this alignment factor.
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The default for this in 64-bit mode is 8, which causes problems with
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SFmode register saves. */
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#define DWARF_CIE_DATA_ALIGNMENT -4
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/* Target machine storage layout. */
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#define BITS_BIG_ENDIAN 0
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#define BYTES_BIG_ENDIAN 0
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#define WORDS_BIG_ENDIAN 0
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#define MAX_BITS_PER_WORD 64
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/* Width of a word, in units (bytes). */
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#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
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#ifndef IN_LIBGCC2
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#define MIN_UNITS_PER_WORD 4
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#endif
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/* For LARCH, width of a floating point register. */
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#define UNITS_PER_FPREG (TARGET_DOUBLE_FLOAT ? 8 : 4)
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/* The largest size of value that can be held in floating-point
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registers and moved with a single instruction. */
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#define UNITS_PER_HWFPVALUE \
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(TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FPREG)
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/* The largest size of value that can be held in floating-point
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registers. */
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#define UNITS_PER_FPVALUE \
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(TARGET_SOFT_FLOAT ? 0 \
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: TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
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: LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
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/* The number of bytes in a double. */
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#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
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/* Set the sizes of the core types. */
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#define SHORT_TYPE_SIZE 16
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#define INT_TYPE_SIZE 32
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#define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
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#define LONG_LONG_TYPE_SIZE 64
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#define FLOAT_TYPE_SIZE 32
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#define DOUBLE_TYPE_SIZE 64
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#define LONG_DOUBLE_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
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/* Define the sizes of fixed-point types. */
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#define SHORT_FRACT_TYPE_SIZE 8
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#define FRACT_TYPE_SIZE 16
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#define LONG_FRACT_TYPE_SIZE 32
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#define LONG_LONG_FRACT_TYPE_SIZE 64
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#define SHORT_ACCUM_TYPE_SIZE 16
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#define ACCUM_TYPE_SIZE 32
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#define LONG_ACCUM_TYPE_SIZE 64
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#define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
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/* long double is not a fixed mode, but the idea is that, if we
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support long double, we also want a 128-bit integer type. */
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#define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
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/* Width in bits of a pointer. */
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#ifndef POINTER_SIZE
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#define POINTER_SIZE (TARGET_64BIT ? 64 : 32)
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#endif
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/* Allocation boundary (in *bits*) for storing arguments in argument list. */
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#define PARM_BOUNDARY BITS_PER_WORD
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/* Allocation boundary (in *bits*) for the code of a function. */
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#define FUNCTION_BOUNDARY 32
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/* Alignment of field after `int : 0' in a structure. */
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#define EMPTY_FIELD_BOUNDARY 32
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/* Number of bits which any structure or union's size must be a multiple of.
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Each structure or union's size is rounded up to a multiple of this. */
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#define STRUCTURE_SIZE_BOUNDARY 8
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/* There is no point aligning anything to a rounder boundary than
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LONG_DOUBLE_TYPE_SIZE. */
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#define BIGGEST_ALIGNMENT (LONG_DOUBLE_TYPE_SIZE)
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/* All accesses must be aligned. */
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#define STRICT_ALIGNMENT (TARGET_STRICT_ALIGN)
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/* Define this if you wish to imitate the way many other C compilers
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handle alignment of bitfields and the structures that contain
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them.
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The behavior is that the type written for a bit-field (`int',
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`short', or other integer type) imposes an alignment for the
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entire structure, as if the structure really did contain an
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ordinary field of that type. In addition, the bit-field is placed
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within the structure so that it would fit within such a field,
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not crossing a boundary for it.
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Thus, on most machines, a bit-field whose type is written as `int'
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would not cross a four-byte boundary, and would force four-byte
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alignment for the whole structure. (The alignment used may not
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be four bytes; it is controlled by the other alignment
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parameters.)
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If the macro is defined, its definition should be a C expression;
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a nonzero value for the expression enables this behavior. */
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#define PCC_BITFIELD_TYPE_MATTERS 1
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/* If defined, a C expression to compute the alignment for a static
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variable. TYPE is the data type, and ALIGN is the alignment that
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the object would ordinarily have. The value of this macro is used
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instead of that alignment to align the object.
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If this macro is not defined, then ALIGN is used.
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One use of this macro is to increase alignment of medium-size
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data to make it all fit in fewer cache lines. Another is to
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cause character arrays to be word-aligned so that `strcpy' calls
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that copy constants to character arrays can be done inline. */
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#undef DATA_ALIGNMENT
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#define DATA_ALIGNMENT(TYPE, ALIGN) \
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((((ALIGN) < BITS_PER_WORD) \
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&& (TREE_CODE (TYPE) == ARRAY_TYPE \
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|| TREE_CODE (TYPE) == UNION_TYPE \
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|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
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/* We need this for the same reason as DATA_ALIGNMENT, namely to cause
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character arrays to be word-aligned so that `strcpy' calls that copy
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constants to character arrays can be done inline, and 'strcmp' can be
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optimised to use word loads. */
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#define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN)
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/* Define if operations between registers always perform the operation
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on the full register even if a narrower mode is specified. */
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#define WORD_REGISTER_OPERATIONS 1
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/* When in 64-bit mode, move insns will sign extend SImode and FCCmode
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moves. All other references are zero extended. */
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#define LOAD_EXTEND_OP(MODE) \
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(TARGET_64BIT && ((MODE) == SImode || (MODE) == FCCmode) ? SIGN_EXTEND \
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: ZERO_EXTEND)
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/* Define this macro if it is advisable to hold scalars in registers
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in a wider mode than that declared by the program. In such cases,
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the value is constrained to be within the bounds of the declared
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type, but kept valid in the wider mode. The signedness of the
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extension may differ from that of the type. */
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#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
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if (GET_MODE_CLASS (MODE) == MODE_INT \
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&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
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{ \
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if ((MODE) == SImode) \
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(UNSIGNEDP) = 0; \
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(MODE) = Pmode; \
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}
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/* Pmode is always the same as ptr_mode, but not always the same as word_mode.
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Extensions of pointers to word_mode must be signed. */
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#define POINTERS_EXTEND_UNSIGNED false
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/* Define if loading short immediate values into registers sign extends. */
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#define SHORT_IMMEDIATES_SIGN_EXTEND 1
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/* The clz.{w/d} instructions have the natural values at 0. */
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#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
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((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
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/* Standard register usage. */
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/* Number of hardware registers. We have:
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- 32 integer registers
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- 32 floating point registers
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- 8 condition code registers
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- 2 fake registers:
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- ARG_POINTER_REGNUM
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- FRAME_POINTER_REGNUM
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*/
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#define FIRST_PSEUDO_REGISTER 74
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/* zero, tp, sp and x are fixed. */
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#define FIXED_REGISTERS \
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{ /* General registers. */ \
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1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Floating-point registers. */ \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Others. */ \
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0, 0, 0, 0, 0, 0, 0, 0, 1, 1}
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/* The call RTLs themselves clobber ra. */
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#define CALL_USED_REGISTERS \
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{ /* General registers. */ \
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1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Floating-point registers. */ \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Others. */ \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
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/* Internal macros to classify a register number as to whether it's a
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general purpose register, a floating point register, or a status
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register. */
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#define GP_REG_FIRST 0
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#define GP_REG_LAST 31
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#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
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#define FP_REG_FIRST 32
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#define FP_REG_LAST 63
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#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
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/* The DWARF 2 CFA column which tracks the return address from a
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signal handler context. This means that to maintain backwards
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compatibility, no hard register can be assigned this column if it
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would need to be handled by the DWARF unwinder. */
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#define DWARF_ALT_FRAME_RETURN_COLUMN 72
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#define FCC_REG_FIRST 64
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#define FCC_REG_LAST 71
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#define FCC_REG_NUM (FCC_REG_LAST - FCC_REG_FIRST + 1)
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#define GP_REG_P(REGNO) \
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((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
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#define FP_REG_P(REGNO) \
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((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
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#define FCC_REG_P(REGNO) \
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((unsigned int) ((int) (REGNO) - FCC_REG_FIRST) < FCC_REG_NUM)
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#define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
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/* Select a register mode required for caller save of hard regno REGNO. */
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#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
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loongarch_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
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||
|
||
/* Register to use for pushing function arguments. */
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#define STACK_POINTER_REGNUM (GP_REG_FIRST + 3)
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/* These two registers don't really exist: they get eliminated to either
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the stack or hard frame pointer. */
|
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#define ARG_POINTER_REGNUM 72
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#define FRAME_POINTER_REGNUM 73
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#define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 22)
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||
|
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#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
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#define HARD_FRAME_POINTER_IS_ARG_POINTER 0
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|
||
/* Register in which static-chain is passed to a function. */
|
||
#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 20) /* $t8 */
|
||
|
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#define GP_TEMP_FIRST (GP_REG_FIRST + 12)
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#define LARCH_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1)
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#define LARCH_PROLOGUE_TEMP2_REGNUM (GP_TEMP_FIRST)
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||
#define LARCH_PROLOGUE_TEMP3_REGNUM (GP_TEMP_FIRST + 2)
|
||
#define LARCH_EPILOGUE_TEMP_REGNUM (GP_TEMP_FIRST)
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||
|
||
#define CALLEE_SAVED_REG_NUMBER(REGNO) \
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((REGNO) >= 22 && (REGNO) <= 31 ? (REGNO) - 22 : -1)
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|
||
#define LARCH_PROLOGUE_TEMP(MODE) \
|
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gen_rtx_REG (MODE, LARCH_PROLOGUE_TEMP_REGNUM)
|
||
#define LARCH_PROLOGUE_TEMP2(MODE) \
|
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gen_rtx_REG (MODE, LARCH_PROLOGUE_TEMP2_REGNUM)
|
||
#define LARCH_PROLOGUE_TEMP3(MODE) \
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gen_rtx_REG (MODE, LARCH_PROLOGUE_TEMP3_REGNUM)
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#define LARCH_EPILOGUE_TEMP(MODE) \
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gen_rtx_REG (MODE, LARCH_EPILOGUE_TEMP_REGNUM)
|
||
|
||
/* Define this macro if it is as good or better to call a constant
|
||
function address than to call an address kept in a register. */
|
||
#define NO_FUNCTION_CSE 1
|
||
|
||
#define THREAD_POINTER_REGNUM (GP_REG_FIRST + 2)
|
||
|
||
/* Define the classes of registers for register constraints in the
|
||
machine description. Also define ranges of constants.
|
||
|
||
One of the classes must always be named ALL_REGS and include all hard regs.
|
||
If there is more than one class, another class must be named NO_REGS
|
||
and contain no registers.
|
||
|
||
The name GENERAL_REGS must be the name of a class (or an alias for
|
||
another name such as ALL_REGS). This is the class of registers
|
||
that is allowed by "r" in a register constraint.
|
||
Also, registers outside this class are allocated only when
|
||
instructions express preferences for them.
|
||
|
||
The classes must be numbered in nondecreasing order; that is,
|
||
a larger-numbered class must never be contained completely
|
||
in a smaller-numbered class.
|
||
|
||
For any two classes, it is very desirable that there be another
|
||
class that represents their union. */
|
||
|
||
enum reg_class
|
||
{
|
||
NO_REGS, /* no registers in set */
|
||
SIBCALL_REGS, /* registers used by indirect sibcalls */
|
||
JIRL_REGS, /* registers used by indirect calls */
|
||
CSR_REGS, /* integer registers except for $r0 and $r1 for lcsr. */
|
||
GR_REGS, /* integer registers */
|
||
FP_REGS, /* floating point registers */
|
||
FCC_REGS, /* status registers (fp status) */
|
||
FRAME_REGS, /* arg pointer and frame pointer */
|
||
ALL_REGS, /* all registers */
|
||
LIM_REG_CLASSES /* max value + 1 */
|
||
};
|
||
|
||
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
||
|
||
#define GENERAL_REGS GR_REGS
|
||
|
||
/* An initializer containing the names of the register classes as C
|
||
string constants. These names are used in writing some of the
|
||
debugging dumps. */
|
||
|
||
#define REG_CLASS_NAMES \
|
||
{ \
|
||
"NO_REGS", \
|
||
"SIBCALL_REGS", \
|
||
"JIRL_REGS", \
|
||
"CSR_REGS", \
|
||
"GR_REGS", \
|
||
"FP_REGS", \
|
||
"FCC_REGS", \
|
||
"FRAME_REGS", \
|
||
"ALL_REGS" \
|
||
}
|
||
|
||
/* An initializer containing the contents of the register classes,
|
||
as integers which are bit masks. The Nth integer specifies the
|
||
contents of class N. The way the integer MASK is interpreted is
|
||
that register R is in the class if `MASK & (1 << R)' is 1.
|
||
|
||
When the machine has more than 32 registers, an integer does not
|
||
suffice. Then the integers are replaced by sub-initializers,
|
||
braced groupings containing several integers. Each
|
||
sub-initializer must be suitable as an initializer for the type
|
||
`HARD_REG_SET' which is defined in `hard-reg-set.h'. */
|
||
|
||
#define REG_CLASS_CONTENTS \
|
||
{ \
|
||
{ 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
|
||
{ 0x001ff000, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \
|
||
{ 0xff9ffff0, 0x00000000, 0x00000000 }, /* JIRL_REGS */ \
|
||
{ 0xfffffffc, 0x00000000, 0x00000000 }, /* CSR_REGS */ \
|
||
{ 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \
|
||
{ 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \
|
||
{ 0x00000000, 0x00000000, 0x000000ff }, /* FCC_REGS */ \
|
||
{ 0x00000000, 0x00000000, 0x00000300 }, /* FRAME_REGS */ \
|
||
{ 0xffffffff, 0xffffffff, 0x000003ff } /* ALL_REGS */ \
|
||
}
|
||
|
||
/* A C expression whose value is a register class containing hard
|
||
register REGNO. In general there is more that one such class;
|
||
choose a class which is "minimal", meaning that no smaller class
|
||
also contains the register. */
|
||
|
||
#define REGNO_REG_CLASS(REGNO) loongarch_regno_to_class[(REGNO)]
|
||
|
||
/* A macro whose definition is the name of the class to which a
|
||
valid base register must belong. A base register is one used in
|
||
an address which is the register value plus a displacement. */
|
||
|
||
#define BASE_REG_CLASS (GR_REGS)
|
||
|
||
/* A macro whose definition is the name of the class to which a
|
||
valid index register must belong. An index register is one used
|
||
in an address where its value is either multiplied by a scale
|
||
factor or added to another register (as well as added to a
|
||
displacement). */
|
||
|
||
#define INDEX_REG_CLASS GR_REGS
|
||
|
||
/* We generally want to put call-clobbered registers ahead of
|
||
call-saved ones. (IRA expects this.) */
|
||
|
||
#define REG_ALLOC_ORDER \
|
||
{ /* Call-clobbered GPRs. */ \
|
||
12, 13, 14, 15, 16, 17, 18, 19, 20, 4, 5, 6, 7, 8, 9, 10, 11, 1, \
|
||
/* Call-saved GPRs. */ \
|
||
23, 24, 25, 26, 27, 28, 29, 30, 31, \
|
||
/* GPRs that can never be exposed to the register allocator. */ \
|
||
0, 2, 3, 21, 22, \
|
||
/* Call-clobbered FPRs. */ \
|
||
32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
|
||
48, 49, 50, 51,52, 53, 54, 55, \
|
||
56, 57, 58, 59, 60, 61, 62, 63, \
|
||
/* None of the remaining classes have defined call-saved \
|
||
registers. */ \
|
||
64, 65, 66, 67, 68, 69, 70, 71, 72, 73}
|
||
|
||
#define IMM_BITS 12
|
||
#define IMM_REACH (1LL << IMM_BITS)
|
||
|
||
/* True if VALUE is an unsigned 6-bit number. */
|
||
|
||
#define UIMM6_OPERAND(VALUE) (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
|
||
|
||
/* True if VALUE is a signed 10-bit number. */
|
||
|
||
#define IMM10_OPERAND(VALUE) ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
|
||
|
||
/* True if VALUE is a signed 12-bit number. */
|
||
|
||
#define IMM12_OPERAND(VALUE) \
|
||
((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH / 2 < IMM_REACH)
|
||
|
||
/* True if VALUE is a signed 16-bit number. */
|
||
|
||
#define IMM16_OPERAND(VALUE) \
|
||
((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
|
||
|
||
/* True if VALUE is an unsigned 12-bit number. */
|
||
|
||
#define IMM12_OPERAND_UNSIGNED(VALUE) \
|
||
(((VALUE) & ~(unsigned HOST_WIDE_INT) (IMM_REACH - 1)) == 0)
|
||
|
||
/* True if VALUE can be loaded into a register using LU12I. */
|
||
|
||
#define LU12I_OPERAND(VALUE) \
|
||
(((VALUE) | ((1UL << 31) - IMM_REACH)) == ((1UL << 31) - IMM_REACH) \
|
||
|| ((VALUE) | ((1UL << 31) - IMM_REACH)) + IMM_REACH == 0)
|
||
|
||
/* True if VALUE can be loaded into a register using LU32I. */
|
||
|
||
#define LU32I_OPERAND(VALUE) \
|
||
(((VALUE) | (((1ULL << 19) - 1) << 32)) == (((1ULL << 19) - 1) << 32) \
|
||
|| ((VALUE) | (((1ULL << 19) - 1) << 32)) + (1ULL << 32) == 0)
|
||
|
||
/* True if VALUE can be loaded into a register using LU52I. */
|
||
|
||
#define LU52I_OPERAND(VALUE) (((VALUE) | (0xfffULL << 52)) == (0xfffULL << 52))
|
||
|
||
/* Return a value X with the low 12 bits clear, and such that
|
||
VALUE - X is a signed 12-bit value. */
|
||
|
||
#define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH / 2)) & ~(IMM_REACH - 1))
|
||
|
||
#define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
|
||
|
||
#define IMM12_INT(X) IMM12_OPERAND (INTVAL (X))
|
||
#define IMM12_INT_UNSIGNED(X) IMM12_OPERAND_UNSIGNED (INTVAL (X))
|
||
#define LU12I_INT(X) LU12I_OPERAND (INTVAL (X))
|
||
#define LU32I_INT(X) LU32I_OPERAND (INTVAL (X))
|
||
#define LU52I_INT(X) LU52I_OPERAND (INTVAL (X))
|
||
#define LARCH_U12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
|
||
#define LARCH_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
|
||
#define LARCH_16BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -32768, 32767))
|
||
#define LARCH_SHIFT_2_OFFSET_P(OFFSET) (((OFFSET) & 0x3) == 0)
|
||
|
||
/* Return the maximum number of consecutive registers
|
||
needed to represent mode MODE in a register of class CLASS. */
|
||
|
||
#define CLASS_MAX_NREGS(CLASS, MODE) loongarch_class_max_nregs (CLASS, MODE)
|
||
|
||
/* Stack layout; function entry, exit and calling. */
|
||
|
||
#define STACK_GROWS_DOWNWARD 1
|
||
|
||
#define FRAME_GROWS_DOWNWARD 1
|
||
|
||
#define RETURN_ADDR_RTX loongarch_return_addr
|
||
|
||
/* Similarly, don't use the least-significant bit to tell pointers to
|
||
code from vtable index. */
|
||
|
||
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
|
||
|
||
#define ELIMINABLE_REGS \
|
||
{ \
|
||
{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
||
{ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
|
||
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
||
{FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
|
||
}
|
||
|
||
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
||
(OFFSET) = loongarch_initial_elimination_offset ((FROM), (TO))
|
||
|
||
/* Allocate stack space for arguments at the beginning of each function. */
|
||
#define ACCUMULATE_OUTGOING_ARGS 1
|
||
|
||
/* The argument pointer always points to the first argument. */
|
||
#define FIRST_PARM_OFFSET(FNDECL) 0
|
||
|
||
#define REG_PARM_STACK_SPACE(FNDECL) 0
|
||
|
||
/* Define this if it is the responsibility of the caller to
|
||
allocate the area reserved for arguments passed in registers.
|
||
If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
|
||
of this macro is to determine whether the space is included in
|
||
`crtl->outgoing_args_size'. */
|
||
#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
|
||
|
||
#define STACK_BOUNDARY (TARGET_ABI_LP64 ? 128 : 64)
|
||
|
||
/* Symbolic macros for the registers used to return integer and floating
|
||
point values. */
|
||
|
||
#define GP_RETURN (GP_REG_FIRST + 4)
|
||
#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
|
||
|
||
#define MAX_ARGS_IN_REGISTERS 8
|
||
|
||
/* Symbolic macros for the first/last argument registers. */
|
||
|
||
#define GP_ARG_FIRST (GP_REG_FIRST + 4)
|
||
#define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
|
||
#define FP_ARG_FIRST (FP_REG_FIRST + 0)
|
||
#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
|
||
|
||
/* 1 if N is a possible register number for function argument passing.
|
||
We have no FP argument registers when soft-float. */
|
||
|
||
/* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */
|
||
#define FUNCTION_ARG_REGNO_P(N) \
|
||
(IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \
|
||
|| (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
|
||
|
||
typedef struct {
|
||
/* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
|
||
unsigned int num_gprs;
|
||
|
||
/* Number of floating-point registers used so far, likewise. */
|
||
unsigned int num_fprs;
|
||
|
||
} CUMULATIVE_ARGS;
|
||
|
||
/* Initialize a variable CUM of type CUMULATIVE_ARGS
|
||
for a call to a function whose data type is FNTYPE.
|
||
For a library call, FNTYPE is 0. */
|
||
|
||
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
||
memset (&(CUM), 0, sizeof (CUM))
|
||
|
||
#define EPILOGUE_USES(REGNO) loongarch_epilogue_uses (REGNO)
|
||
|
||
/* Treat LOC as a byte offset from the stack pointer and round it up
|
||
to the next fully-aligned offset. */
|
||
#define LARCH_STACK_ALIGN(LOC) \
|
||
(TARGET_ABI_LP64 ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
|
||
|
||
#define MCOUNT_NAME "_mcount"
|
||
|
||
/* Emit rtl for profiling. Output assembler code to FILE
|
||
to call "_mcount" for profiling a function entry. */
|
||
#define PROFILE_HOOK(LABEL) \
|
||
{ \
|
||
rtx fun, ra; \
|
||
ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \
|
||
fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \
|
||
emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \
|
||
}
|
||
|
||
/* All the work done in PROFILE_HOOK, but still required. */
|
||
#define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
|
||
|
||
#define NO_PROFILE_COUNTERS 1
|
||
|
||
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
|
||
the stack pointer does not matter. The value is tested only in
|
||
functions that have frame pointers.
|
||
No definition is equivalent to always zero. */
|
||
|
||
#define EXIT_IGNORE_STACK 1
|
||
|
||
/* Trampolines are a block of code followed by two pointers. */
|
||
|
||
#define TRAMPOLINE_CODE_SIZE 16
|
||
#define TRAMPOLINE_SIZE \
|
||
((Pmode == SImode) ? TRAMPOLINE_CODE_SIZE \
|
||
: (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
|
||
#define TRAMPOLINE_ALIGNMENT POINTER_SIZE
|
||
|
||
/* loongarch_trampoline_init calls this library function to flush
|
||
program and data caches. */
|
||
|
||
#ifndef CACHE_FLUSH_FUNC
|
||
#define CACHE_FLUSH_FUNC "_flush_cache"
|
||
#endif
|
||
|
||
/* Addressing modes, and classification of registers for them. */
|
||
|
||
#define REGNO_OK_FOR_INDEX_P(REGNO) \
|
||
loongarch_regno_mode_ok_for_base_p (REGNO, VOIDmode, 1)
|
||
|
||
#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
|
||
loongarch_regno_mode_ok_for_base_p (REGNO, MODE, 1)
|
||
|
||
/* Maximum number of registers that can appear in a valid memory address. */
|
||
|
||
#define MAX_REGS_PER_ADDRESS 2
|
||
|
||
/* Check for constness inline but use loongarch_legitimate_address_p
|
||
to check whether a constant really is an address. */
|
||
|
||
#define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X) && memory_address_p (SImode, X))
|
||
|
||
/* This handles the magic '..CURRENT_FUNCTION' symbol, which means
|
||
'the start of the function that this code is output in'. */
|
||
|
||
#define ASM_OUTPUT_LABELREF(FILE, NAME) \
|
||
do \
|
||
{ \
|
||
if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
|
||
asm_fprintf ((FILE), "%U%s", \
|
||
XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
|
||
else \
|
||
asm_fprintf ((FILE), "%U%s", (NAME)); \
|
||
} \
|
||
while (0)
|
||
|
||
#define CASE_VECTOR_MODE Pmode
|
||
|
||
#define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) Pmode
|
||
|
||
/* Define this as 1 if `char' should by default be signed; else as 0. */
|
||
#ifndef DEFAULT_SIGNED_CHAR
|
||
#define DEFAULT_SIGNED_CHAR 1
|
||
#endif
|
||
|
||
/* The SPARC port says:
|
||
The maximum number of bytes that a single instruction
|
||
can move quickly between memory and registers or between
|
||
two memory locations. */
|
||
#define MOVE_MAX UNITS_PER_WORD
|
||
#define MAX_MOVE_MAX 8
|
||
|
||
/* The SPARC port says:
|
||
Nonzero if access to memory by bytes is slow and undesirable.
|
||
For RISC chips, it means that access to memory by bytes is no
|
||
better than access by words when possible, so grab a whole word
|
||
and maybe make use of that. */
|
||
#define SLOW_BYTE_ACCESS 1
|
||
|
||
/* Standard LoongArch integer shifts truncate the shift amount to the
|
||
width of the shifted operand. */
|
||
#define SHIFT_COUNT_TRUNCATED 1
|
||
|
||
/* Specify the machine mode that pointers have.
|
||
After generation of rtl, the compiler makes no further distinction
|
||
between pointers and any other objects of this machine mode. */
|
||
|
||
#ifndef Pmode
|
||
#define Pmode (TARGET_64BIT ? DImode : SImode)
|
||
#endif
|
||
|
||
/* Give call MEMs SImode since it is the "most permissive" mode
|
||
for both 32-bit and 64-bit targets. */
|
||
|
||
#define FUNCTION_MODE SImode
|
||
|
||
/* We allocate $fcc registers by hand and can't cope with moves of
|
||
CCmode registers to and from pseudos (or memory). */
|
||
#define AVOID_CCMODE_COPIES
|
||
|
||
/* A C expression for the cost of a branch instruction. A value of
|
||
1 is the default; other values are interpreted relative to that. */
|
||
|
||
#define BRANCH_COST(speed_p, predictable_p) loongarch_branch_cost
|
||
#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
|
||
|
||
/* Return the asm template for a conditional branch instruction.
|
||
OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
|
||
its operands. */
|
||
#define LARCH_BRANCH(OPCODE, OPERANDS) OPCODE "\t" OPERANDS
|
||
|
||
/* Control the assembler format that we output. */
|
||
|
||
/* Output to assembler file text saying following lines
|
||
may contain character constants, extra white space, comments, etc. */
|
||
|
||
#ifndef ASM_APP_ON
|
||
#define ASM_APP_ON " #APP\n"
|
||
#endif
|
||
|
||
/* Output to assembler file text saying following lines
|
||
no longer contain unusual constructs. */
|
||
|
||
#ifndef ASM_APP_OFF
|
||
#define ASM_APP_OFF " #NO_APP\n"
|
||
#endif
|
||
|
||
#define REGISTER_NAMES \
|
||
{ "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
|
||
"$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$r15", \
|
||
"$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
|
||
"$r24", "$r25", "$r26", "$r27", "$r28", "$r29", "$r30", "$r31", \
|
||
"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
|
||
"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
|
||
"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
|
||
"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
|
||
"$fcc0","$fcc1","$fcc2","$fcc3","$fcc4","$fcc5","$fcc6","$fcc7", \
|
||
"$arg", "$frame"}
|
||
|
||
/* This macro defines additional names for hard registers. */
|
||
|
||
#define ADDITIONAL_REGISTER_NAMES \
|
||
{ \
|
||
{ "zero", 0 + GP_REG_FIRST }, \
|
||
{ "ra", 1 + GP_REG_FIRST }, \
|
||
{ "tp", 2 + GP_REG_FIRST }, \
|
||
{ "sp", 3 + GP_REG_FIRST }, \
|
||
{ "a0", 4 + GP_REG_FIRST }, \
|
||
{ "a1", 5 + GP_REG_FIRST }, \
|
||
{ "a2", 6 + GP_REG_FIRST }, \
|
||
{ "a3", 7 + GP_REG_FIRST }, \
|
||
{ "a4", 8 + GP_REG_FIRST }, \
|
||
{ "a5", 9 + GP_REG_FIRST }, \
|
||
{ "a6", 10 + GP_REG_FIRST }, \
|
||
{ "a7", 11 + GP_REG_FIRST }, \
|
||
{ "t0", 12 + GP_REG_FIRST }, \
|
||
{ "t1", 13 + GP_REG_FIRST }, \
|
||
{ "t2", 14 + GP_REG_FIRST }, \
|
||
{ "t3", 15 + GP_REG_FIRST }, \
|
||
{ "t4", 16 + GP_REG_FIRST }, \
|
||
{ "t5", 17 + GP_REG_FIRST }, \
|
||
{ "t6", 18 + GP_REG_FIRST }, \
|
||
{ "t7", 19 + GP_REG_FIRST }, \
|
||
{ "t8", 20 + GP_REG_FIRST }, \
|
||
{ "x", 21 + GP_REG_FIRST }, \
|
||
{ "fp", 22 + GP_REG_FIRST }, \
|
||
{ "s0", 23 + GP_REG_FIRST }, \
|
||
{ "s1", 24 + GP_REG_FIRST }, \
|
||
{ "s2", 25 + GP_REG_FIRST }, \
|
||
{ "s3", 26 + GP_REG_FIRST }, \
|
||
{ "s4", 27 + GP_REG_FIRST }, \
|
||
{ "s5", 28 + GP_REG_FIRST }, \
|
||
{ "s6", 29 + GP_REG_FIRST }, \
|
||
{ "s7", 30 + GP_REG_FIRST }, \
|
||
{ "s8", 31 + GP_REG_FIRST }, \
|
||
{ "v0", 4 + GP_REG_FIRST }, \
|
||
{ "v1", 5 + GP_REG_FIRST } \
|
||
}
|
||
|
||
/* Globalizing directive for a label. */
|
||
#define GLOBAL_ASM_OP "\t.globl\t"
|
||
|
||
/* This says how to output an external. It would be possible not to
|
||
output anything and let undefined symbol become external. However
|
||
the assembler uses length information on externals to allocate in
|
||
data/sdata bss/sbss, thereby saving exec time. */
|
||
|
||
#undef ASM_OUTPUT_EXTERNAL
|
||
#define ASM_OUTPUT_EXTERNAL(STREAM, DECL, NAME) \
|
||
loongarch_output_external (STREAM, DECL, NAME)
|
||
|
||
/* This is how to store into the string LABEL
|
||
the symbol_ref name of an internal numbered label where
|
||
PREFIX is the class of label and NUM is the number within the class.
|
||
This is suitable for output with `assemble_name'. */
|
||
|
||
#undef ASM_GENERATE_INTERNAL_LABEL
|
||
#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
|
||
sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
|
||
|
||
/* Print debug labels as "foo = ." rather than "foo:" because they should
|
||
represent a byte pointer rather than an ISA-encoded address. This is
|
||
particularly important for code like:
|
||
|
||
$LFBxxx = .
|
||
.cfi_startproc
|
||
...
|
||
.section .gcc_except_table,...
|
||
...
|
||
.uleb128 foo-$LFBxxx
|
||
|
||
The .uleb128 requies $LFBxxx to match the FDE start address, which is
|
||
likewise a byte pointer rather than an ISA-encoded address.
|
||
|
||
At the time of writing, this hook is not used for the function end
|
||
label:
|
||
|
||
$LFExxx:
|
||
.end foo
|
||
|
||
*/
|
||
|
||
#define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
|
||
fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
|
||
|
||
/* This is how to output an element of a case-vector that is absolute. */
|
||
|
||
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
|
||
fprintf (STREAM, "\t%s\t%sL%d\n", ptr_mode == DImode ? ".dword" : ".word", \
|
||
LOCAL_LABEL_PREFIX, VALUE)
|
||
|
||
/* This is how to output an element of a case-vector. */
|
||
|
||
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
|
||
do \
|
||
{ \
|
||
fprintf (STREAM, "\t%s\t%sL%d-%sL%d\n", \
|
||
ptr_mode == DImode ? ".dword" : ".word", LOCAL_LABEL_PREFIX, \
|
||
VALUE, LOCAL_LABEL_PREFIX, REL); \
|
||
} \
|
||
while (0)
|
||
|
||
#define JUMP_TABLES_IN_TEXT_SECTION 0
|
||
|
||
/* This is how to output an assembler line
|
||
that says to advance the location counter
|
||
to a multiple of 2**LOG bytes. */
|
||
|
||
#define ASM_OUTPUT_ALIGN(STREAM, LOG) fprintf (STREAM, "\t.align\t%d\n", (LOG))
|
||
|
||
/* "nop" instruction 54525952 (andi $r0,$r0,0) is
|
||
used for padding. */
|
||
#define ASM_OUTPUT_ALIGN_WITH_NOP(STREAM, LOG) \
|
||
fprintf (STREAM, "\t.align\t%d,54525952,4\n", (LOG))
|
||
|
||
/* This is how to output an assembler line to advance the location
|
||
counter by SIZE bytes. */
|
||
|
||
#undef ASM_OUTPUT_SKIP
|
||
#define ASM_OUTPUT_SKIP(STREAM, SIZE) \
|
||
fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", (SIZE))
|
||
|
||
/* This is how to output a string. */
|
||
#undef ASM_OUTPUT_ASCII
|
||
#define ASM_OUTPUT_ASCII loongarch_output_ascii
|
||
|
||
/* Define the strings to put out for each section in the object file. */
|
||
#define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
|
||
#define DATA_SECTION_ASM_OP "\t.data" /* large data */
|
||
|
||
#undef READONLY_DATA_SECTION_ASM_OP
|
||
#define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata" /* read-only data */
|
||
|
||
#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
|
||
do \
|
||
{ \
|
||
fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,%s,0\n", \
|
||
TARGET_64BIT ? "addi.d" : "addi.w", \
|
||
reg_names[STACK_POINTER_REGNUM], \
|
||
reg_names[STACK_POINTER_REGNUM], \
|
||
TARGET_64BIT ? "st.d" : "st.w", reg_names[REGNO], \
|
||
reg_names[STACK_POINTER_REGNUM]); \
|
||
} \
|
||
while (0)
|
||
|
||
#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
|
||
do \
|
||
{ \
|
||
fprintf (STREAM, "\t%s\t%s,%s,0\n\t%s\t%s,%s,8\n", \
|
||
TARGET_64BIT ? "ld.d" : "ld.w", reg_names[REGNO], \
|
||
reg_names[STACK_POINTER_REGNUM], \
|
||
TARGET_64BIT ? "addi.d" : "addi.w", \
|
||
reg_names[STACK_POINTER_REGNUM], \
|
||
reg_names[STACK_POINTER_REGNUM]); \
|
||
} \
|
||
while (0)
|
||
|
||
/* How to start an assembler comment.
|
||
The leading space is important (the loongarch native assembler requires it).
|
||
*/
|
||
#ifndef ASM_COMMENT_START
|
||
#define ASM_COMMENT_START " #"
|
||
#endif
|
||
|
||
#undef SIZE_TYPE
|
||
#define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
|
||
|
||
#undef PTRDIFF_TYPE
|
||
#define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
|
||
|
||
/* The maximum number of bytes that can be copied by one iteration of
|
||
a cpymemsi loop; see loongarch_block_move_loop. */
|
||
#define LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
|
||
|
||
/* The maximum number of bytes that can be copied by a straight-line
|
||
implementation of cpymemsi; see loongarch_block_move_straight. We want
|
||
to make sure that any loop-based implementation will iterate at
|
||
least twice. */
|
||
#define LARCH_MAX_MOVE_BYTES_STRAIGHT (LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
|
||
|
||
/* The base cost of a memcpy call, for MOVE_RATIO and friends. These
|
||
values were determined experimentally by benchmarking with CSiBE.
|
||
*/
|
||
#define LARCH_CALL_RATIO 8
|
||
|
||
/* Any loop-based implementation of cpymemsi will have at least
|
||
LARCH_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
|
||
moves, so allow individual copies of fewer elements.
|
||
|
||
When cpymemsi is not available, use a value approximating
|
||
the length of a memcpy call sequence, so that move_by_pieces
|
||
will generate inline code if it is shorter than a function call.
|
||
Since move_by_pieces_ninsns counts memory-to-memory moves, but
|
||
we'll have to generate a load/store pair for each, halve the
|
||
value of LARCH_CALL_RATIO to take that into account. */
|
||
|
||
#define MOVE_RATIO(speed) \
|
||
(HAVE_cpymemsi \
|
||
? LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD \
|
||
: CLEAR_RATIO (speed) / 2)
|
||
|
||
/* For CLEAR_RATIO, when optimizing for size, give a better estimate
|
||
of the length of a memset call, but use the default otherwise. */
|
||
|
||
#define CLEAR_RATIO(speed) ((speed) ? 15 : LARCH_CALL_RATIO)
|
||
|
||
/* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
|
||
optimizing for size adjust the ratio to account for the overhead of
|
||
loading the constant and replicating it across the word. */
|
||
|
||
#define SET_RATIO(speed) ((speed) ? 15 : LARCH_CALL_RATIO - 2)
|
||
|
||
#ifndef USED_FOR_TARGET
|
||
extern const enum reg_class loongarch_regno_to_class[];
|
||
extern int loongarch_dwarf_regno[];
|
||
|
||
/* Information about a function's frame layout. */
|
||
struct GTY (()) loongarch_frame_info
|
||
{
|
||
/* The size of the frame in bytes. */
|
||
HOST_WIDE_INT total_size;
|
||
|
||
/* Bit X is set if the function saves or restores GPR X. */
|
||
unsigned int mask;
|
||
|
||
/* Likewise FPR X. */
|
||
unsigned int fmask;
|
||
|
||
/* How much the GPR save/restore routines adjust sp (or 0 if unused). */
|
||
unsigned save_libcall_adjustment;
|
||
|
||
/* Offsets of fixed-point and floating-point save areas from frame
|
||
bottom. */
|
||
HOST_WIDE_INT gp_sp_offset;
|
||
HOST_WIDE_INT fp_sp_offset;
|
||
|
||
/* Offset of virtual frame pointer from stack pointer/frame bottom. */
|
||
HOST_WIDE_INT frame_pointer_offset;
|
||
|
||
/* Offset of hard frame pointer from stack pointer/frame bottom. */
|
||
HOST_WIDE_INT hard_frame_pointer_offset;
|
||
|
||
/* The offset of arg_pointer_rtx from the bottom of the frame. */
|
||
HOST_WIDE_INT arg_pointer_offset;
|
||
};
|
||
|
||
struct GTY (()) machine_function
|
||
{
|
||
/* The next floating-point condition-code register to allocate
|
||
for 8CC targets, relative to FCC_REG_FIRST. */
|
||
unsigned int next_fcc;
|
||
|
||
/* The number of extra stack bytes taken up by register varargs.
|
||
This area is allocated by the callee at the very top of the frame. */
|
||
int varargs_size;
|
||
|
||
/* The current frame information, calculated by loongarch_compute_frame_info.
|
||
*/
|
||
struct loongarch_frame_info frame;
|
||
};
|
||
#endif
|
||
|
||
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
|
||
(((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
|
||
|
||
/* Do emit .note.GNU-stack by default. */
|
||
#ifndef NEED_INDICATE_EXEC_STACK
|
||
#define NEED_INDICATE_EXEC_STACK 1
|
||
#endif
|
||
|
||
/* The `Q' extension is not yet supported. */
|
||
/* TODO: according to march. */
|
||
#define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
|
||
|
||
/* The largest type that can be passed in floating-point registers. */
|
||
/* TODO: according to mabi. */
|
||
#define UNITS_PER_FP_ARG \
|
||
(TARGET_HARD_FLOAT ? (TARGET_DOUBLE_FLOAT ? 8 : 4) : 0)
|
||
|
||
#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
|