566 lines
20 KiB
Modula-2
566 lines
20 KiB
Modula-2
/* Machine description for AArch64 architecture.
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Copyright (C) 2012-2017 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* In the list below, the BUILTIN_<ITERATOR> macros expand to create
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builtins for each of the modes described by <ITERATOR>. When adding
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new builtins to this list, a helpful idiom to follow is to add
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a line for each pattern in the md file. Thus, ADDP, which has one
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pattern defined for the VD_BHSI iterator, and one for DImode, has two
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entries below.
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Parameter 1 is the 'type' of the intrinsic. This is used to
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describe the type modifiers (for example; unsigned) applied to
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each of the parameters to the intrinsic function.
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Parameter 2 is the name of the intrinsic. This is appended
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to `__builtin_aarch64_<name><mode>` to give the intrinsic name
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as exported to the front-ends.
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Parameter 3 describes how to map from the name to the CODE_FOR_
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macro holding the RTL pattern for the intrinsic. This mapping is:
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0 - CODE_FOR_aarch64_<name><mode>
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1-9 - CODE_FOR_<name><mode><1-9>
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10 - CODE_FOR_<name><mode>. */
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BUILTIN_VDC (COMBINE, combine, 0)
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VAR1 (COMBINEP, combine, 0, di)
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BUILTIN_VB (BINOP, pmul, 0)
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BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0)
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BUILTIN_VHSDF_DF (UNOP, sqrt, 2)
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BUILTIN_VD_BHSI (BINOP, addp, 0)
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VAR1 (UNOP, addp, 0, di)
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BUILTIN_VDQ_BHSI (UNOP, clrsb, 2)
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BUILTIN_VDQ_BHSI (UNOP, clz, 2)
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BUILTIN_VS (UNOP, ctz, 2)
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BUILTIN_VB (UNOP, popcount, 2)
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/* Implemented by aarch64_<sur>q<r>shl<mode>. */
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BUILTIN_VSDQ_I (BINOP, sqshl, 0)
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BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0)
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BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
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BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0)
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/* Implemented by aarch64_<su_optab><optab><mode>. */
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BUILTIN_VSDQ_I (BINOP, sqadd, 0)
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BUILTIN_VSDQ_I (BINOPU, uqadd, 0)
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BUILTIN_VSDQ_I (BINOP, sqsub, 0)
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BUILTIN_VSDQ_I (BINOPU, uqsub, 0)
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/* Implemented by aarch64_<sur>qadd<mode>. */
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BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0)
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BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0)
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/* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */
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BUILTIN_VDC (GETREG, get_dregoi, 0)
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BUILTIN_VDC (GETREG, get_dregci, 0)
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BUILTIN_VDC (GETREG, get_dregxi, 0)
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VAR1 (GETREGP, get_dregoi, 0, di)
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VAR1 (GETREGP, get_dregci, 0, di)
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VAR1 (GETREGP, get_dregxi, 0, di)
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/* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */
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BUILTIN_VQ (GETREG, get_qregoi, 0)
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BUILTIN_VQ (GETREG, get_qregci, 0)
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BUILTIN_VQ (GETREG, get_qregxi, 0)
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VAR1 (GETREGP, get_qregoi, 0, v2di)
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VAR1 (GETREGP, get_qregci, 0, v2di)
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VAR1 (GETREGP, get_qregxi, 0, v2di)
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/* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */
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BUILTIN_VQ (SETREG, set_qregoi, 0)
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BUILTIN_VQ (SETREG, set_qregci, 0)
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BUILTIN_VQ (SETREG, set_qregxi, 0)
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VAR1 (SETREGP, set_qregoi, 0, v2di)
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VAR1 (SETREGP, set_qregci, 0, v2di)
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VAR1 (SETREGP, set_qregxi, 0, v2di)
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/* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */
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BUILTIN_VDC (LOADSTRUCT, ld2, 0)
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BUILTIN_VDC (LOADSTRUCT, ld3, 0)
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BUILTIN_VDC (LOADSTRUCT, ld4, 0)
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/* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>. */
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BUILTIN_VQ (LOADSTRUCT, ld2, 0)
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BUILTIN_VQ (LOADSTRUCT, ld3, 0)
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BUILTIN_VQ (LOADSTRUCT, ld4, 0)
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/* Implemented by aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>. */
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BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0)
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BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0)
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BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0)
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/* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>. */
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BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0)
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BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0)
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BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0)
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/* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */
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BUILTIN_VDC (STORESTRUCT, st2, 0)
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BUILTIN_VDC (STORESTRUCT, st3, 0)
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BUILTIN_VDC (STORESTRUCT, st4, 0)
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/* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>. */
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BUILTIN_VQ (STORESTRUCT, st2, 0)
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BUILTIN_VQ (STORESTRUCT, st3, 0)
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BUILTIN_VQ (STORESTRUCT, st4, 0)
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BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0)
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BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0)
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BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0)
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BUILTIN_VQW (BINOP, saddl2, 0)
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BUILTIN_VQW (BINOP, uaddl2, 0)
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BUILTIN_VQW (BINOP, ssubl2, 0)
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BUILTIN_VQW (BINOP, usubl2, 0)
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BUILTIN_VQW (BINOP, saddw2, 0)
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BUILTIN_VQW (BINOP, uaddw2, 0)
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BUILTIN_VQW (BINOP, ssubw2, 0)
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BUILTIN_VQW (BINOP, usubw2, 0)
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/* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */
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BUILTIN_VD_BHSI (BINOP, saddl, 0)
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BUILTIN_VD_BHSI (BINOP, uaddl, 0)
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BUILTIN_VD_BHSI (BINOP, ssubl, 0)
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BUILTIN_VD_BHSI (BINOP, usubl, 0)
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/* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */
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BUILTIN_VD_BHSI (BINOP, saddw, 0)
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BUILTIN_VD_BHSI (BINOP, uaddw, 0)
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BUILTIN_VD_BHSI (BINOP, ssubw, 0)
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BUILTIN_VD_BHSI (BINOP, usubw, 0)
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/* Implemented by aarch64_<sur>h<addsub><mode>. */
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BUILTIN_VDQ_BHSI (BINOP, shadd, 0)
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BUILTIN_VDQ_BHSI (BINOP, shsub, 0)
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BUILTIN_VDQ_BHSI (BINOP, uhadd, 0)
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BUILTIN_VDQ_BHSI (BINOP, uhsub, 0)
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BUILTIN_VDQ_BHSI (BINOP, srhadd, 0)
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BUILTIN_VDQ_BHSI (BINOP, urhadd, 0)
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/* Implemented by aarch64_<sur><addsub>hn<mode>. */
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BUILTIN_VQN (BINOP, addhn, 0)
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BUILTIN_VQN (BINOP, subhn, 0)
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BUILTIN_VQN (BINOP, raddhn, 0)
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BUILTIN_VQN (BINOP, rsubhn, 0)
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/* Implemented by aarch64_<sur><addsub>hn2<mode>. */
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BUILTIN_VQN (TERNOP, addhn2, 0)
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BUILTIN_VQN (TERNOP, subhn2, 0)
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BUILTIN_VQN (TERNOP, raddhn2, 0)
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BUILTIN_VQN (TERNOP, rsubhn2, 0)
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BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
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/* Implemented by aarch64_<sur>qmovn<mode>. */
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BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
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BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
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/* Implemented by aarch64_s<optab><mode>. */
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BUILTIN_VSDQ_I (UNOP, sqabs, 0)
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BUILTIN_VSDQ_I (UNOP, sqneg, 0)
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/* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>. */
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BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
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BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
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/* Implemented by aarch64_sqdml<SBINQOPS:as>l_lane<mode>. */
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BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0)
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BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0)
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/* Implemented by aarch64_sqdml<SBINQOPS:as>l_laneq<mode>. */
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BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0)
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BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0)
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/* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>. */
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BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
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BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
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BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
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BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
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BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0)
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BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0)
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BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0)
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BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0)
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BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
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BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
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BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
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BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0)
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BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0)
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BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
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BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
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BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0)
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BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0)
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BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
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/* Implemented by aarch64_sq<r>dmulh<mode>. */
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BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
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BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
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/* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */
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BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0)
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BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0)
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BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0)
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BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0)
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BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
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/* Implemented by aarch64_<sur>shl<mode>. */
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BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
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BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0)
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BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
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BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0)
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BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
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VAR1 (SHIFTIMM, ashr_simd, 0, di)
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BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
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VAR1 (USHIFTIMM, lshr_simd, 0, di)
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/* Implemented by aarch64_<sur>shr_n<mode>. */
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BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
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BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0)
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/* Implemented by aarch64_<sur>sra_n<mode>. */
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BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
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BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0)
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BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
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BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0)
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/* Implemented by aarch64_<sur>shll_n<mode>. */
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BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0)
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BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0)
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/* Implemented by aarch64_<sur>shll2_n<mode>. */
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BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
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BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
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/* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>. */
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BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
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BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
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BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
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BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0)
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BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
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BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0)
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/* Implemented by aarch64_<sur>s<lr>i_n<mode>. */
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BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
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BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
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BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
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VAR2 (SHIFTINSERTP, ssli_n, 0, di, v2di)
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BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
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/* Implemented by aarch64_<sur>qshl<u>_n<mode>. */
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BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
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BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
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BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0)
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/* Implemented by aarch64_reduc_plus_<mode>. */
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BUILTIN_VALL (UNOP, reduc_plus_scal_, 10)
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/* Implemented by reduc_<maxmin_uns>_scal_<mode> (producing scalar). */
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BUILTIN_VDQIF_F16 (UNOP, reduc_smax_scal_, 10)
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BUILTIN_VDQIF_F16 (UNOP, reduc_smin_scal_, 10)
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BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10)
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BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10)
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BUILTIN_VHSDF (UNOP, reduc_smax_nan_scal_, 10)
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BUILTIN_VHSDF (UNOP, reduc_smin_nan_scal_, 10)
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/* Implemented by <maxmin_uns><mode>3.
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smax variants map to fmaxnm,
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smax_nan variants map to fmax. */
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BUILTIN_VDQ_BHSI (BINOP, smax, 3)
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BUILTIN_VDQ_BHSI (BINOP, smin, 3)
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BUILTIN_VDQ_BHSI (BINOP, umax, 3)
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BUILTIN_VDQ_BHSI (BINOP, umin, 3)
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BUILTIN_VHSDF_DF (BINOP, smax_nan, 3)
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BUILTIN_VHSDF_DF (BINOP, smin_nan, 3)
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/* Implemented by <maxmin_uns><mode>3. */
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BUILTIN_VHSDF_HSDF (BINOP, fmax, 3)
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BUILTIN_VHSDF_HSDF (BINOP, fmin, 3)
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/* Implemented by aarch64_<maxmin_uns>p<mode>. */
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BUILTIN_VDQ_BHSI (BINOP, smaxp, 0)
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BUILTIN_VDQ_BHSI (BINOP, sminp, 0)
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BUILTIN_VDQ_BHSI (BINOP, umaxp, 0)
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BUILTIN_VDQ_BHSI (BINOP, uminp, 0)
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BUILTIN_VHSDF (BINOP, smaxp, 0)
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BUILTIN_VHSDF (BINOP, sminp, 0)
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BUILTIN_VHSDF (BINOP, smax_nanp, 0)
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BUILTIN_VHSDF (BINOP, smin_nanp, 0)
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/* Implemented by <frint_pattern><mode>2. */
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BUILTIN_VHSDF (UNOP, btrunc, 2)
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BUILTIN_VHSDF (UNOP, ceil, 2)
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BUILTIN_VHSDF (UNOP, floor, 2)
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BUILTIN_VHSDF (UNOP, nearbyint, 2)
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BUILTIN_VHSDF (UNOP, rint, 2)
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BUILTIN_VHSDF (UNOP, round, 2)
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BUILTIN_VHSDF_DF (UNOP, frintn, 2)
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VAR1 (UNOP, btrunc, 2, hf)
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VAR1 (UNOP, ceil, 2, hf)
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VAR1 (UNOP, floor, 2, hf)
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VAR1 (UNOP, frintn, 2, hf)
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VAR1 (UNOP, nearbyint, 2, hf)
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VAR1 (UNOP, rint, 2, hf)
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VAR1 (UNOP, round, 2, hf)
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/* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */
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VAR1 (UNOP, lbtruncv4hf, 2, v4hi)
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VAR1 (UNOP, lbtruncv8hf, 2, v8hi)
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VAR1 (UNOP, lbtruncv2sf, 2, v2si)
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VAR1 (UNOP, lbtruncv4sf, 2, v4si)
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VAR1 (UNOP, lbtruncv2df, 2, v2di)
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VAR1 (UNOPUS, lbtruncuv4hf, 2, v4hi)
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VAR1 (UNOPUS, lbtruncuv8hf, 2, v8hi)
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VAR1 (UNOPUS, lbtruncuv2sf, 2, v2si)
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VAR1 (UNOPUS, lbtruncuv4sf, 2, v4si)
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VAR1 (UNOPUS, lbtruncuv2df, 2, v2di)
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VAR1 (UNOP, lroundv4hf, 2, v4hi)
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VAR1 (UNOP, lroundv8hf, 2, v8hi)
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VAR1 (UNOP, lroundv2sf, 2, v2si)
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VAR1 (UNOP, lroundv4sf, 2, v4si)
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VAR1 (UNOP, lroundv2df, 2, v2di)
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/* Implemented by l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2. */
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BUILTIN_GPI_I16 (UNOP, lroundhf, 2)
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VAR1 (UNOP, lroundsf, 2, si)
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VAR1 (UNOP, lrounddf, 2, di)
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|
VAR1 (UNOPUS, lrounduv4hf, 2, v4hi)
|
|
VAR1 (UNOPUS, lrounduv8hf, 2, v8hi)
|
|
VAR1 (UNOPUS, lrounduv2sf, 2, v2si)
|
|
VAR1 (UNOPUS, lrounduv4sf, 2, v4si)
|
|
VAR1 (UNOPUS, lrounduv2df, 2, v2di)
|
|
BUILTIN_GPI_I16 (UNOPUS, lrounduhf, 2)
|
|
VAR1 (UNOPUS, lroundusf, 2, si)
|
|
VAR1 (UNOPUS, lroundudf, 2, di)
|
|
|
|
VAR1 (UNOP, lceilv4hf, 2, v4hi)
|
|
VAR1 (UNOP, lceilv8hf, 2, v8hi)
|
|
VAR1 (UNOP, lceilv2sf, 2, v2si)
|
|
VAR1 (UNOP, lceilv4sf, 2, v4si)
|
|
VAR1 (UNOP, lceilv2df, 2, v2di)
|
|
BUILTIN_GPI_I16 (UNOP, lceilhf, 2)
|
|
|
|
VAR1 (UNOPUS, lceiluv4hf, 2, v4hi)
|
|
VAR1 (UNOPUS, lceiluv8hf, 2, v8hi)
|
|
VAR1 (UNOPUS, lceiluv2sf, 2, v2si)
|
|
VAR1 (UNOPUS, lceiluv4sf, 2, v4si)
|
|
VAR1 (UNOPUS, lceiluv2df, 2, v2di)
|
|
BUILTIN_GPI_I16 (UNOPUS, lceiluhf, 2)
|
|
VAR1 (UNOPUS, lceilusf, 2, si)
|
|
VAR1 (UNOPUS, lceiludf, 2, di)
|
|
|
|
VAR1 (UNOP, lfloorv4hf, 2, v4hi)
|
|
VAR1 (UNOP, lfloorv8hf, 2, v8hi)
|
|
VAR1 (UNOP, lfloorv2sf, 2, v2si)
|
|
VAR1 (UNOP, lfloorv4sf, 2, v4si)
|
|
VAR1 (UNOP, lfloorv2df, 2, v2di)
|
|
BUILTIN_GPI_I16 (UNOP, lfloorhf, 2)
|
|
|
|
VAR1 (UNOPUS, lflooruv4hf, 2, v4hi)
|
|
VAR1 (UNOPUS, lflooruv8hf, 2, v8hi)
|
|
VAR1 (UNOPUS, lflooruv2sf, 2, v2si)
|
|
VAR1 (UNOPUS, lflooruv4sf, 2, v4si)
|
|
VAR1 (UNOPUS, lflooruv2df, 2, v2di)
|
|
BUILTIN_GPI_I16 (UNOPUS, lflooruhf, 2)
|
|
VAR1 (UNOPUS, lfloorusf, 2, si)
|
|
VAR1 (UNOPUS, lfloorudf, 2, di)
|
|
|
|
VAR1 (UNOP, lfrintnv4hf, 2, v4hi)
|
|
VAR1 (UNOP, lfrintnv8hf, 2, v8hi)
|
|
VAR1 (UNOP, lfrintnv2sf, 2, v2si)
|
|
VAR1 (UNOP, lfrintnv4sf, 2, v4si)
|
|
VAR1 (UNOP, lfrintnv2df, 2, v2di)
|
|
BUILTIN_GPI_I16 (UNOP, lfrintnhf, 2)
|
|
VAR1 (UNOP, lfrintnsf, 2, si)
|
|
VAR1 (UNOP, lfrintndf, 2, di)
|
|
|
|
VAR1 (UNOPUS, lfrintnuv4hf, 2, v4hi)
|
|
VAR1 (UNOPUS, lfrintnuv8hf, 2, v8hi)
|
|
VAR1 (UNOPUS, lfrintnuv2sf, 2, v2si)
|
|
VAR1 (UNOPUS, lfrintnuv4sf, 2, v4si)
|
|
VAR1 (UNOPUS, lfrintnuv2df, 2, v2di)
|
|
BUILTIN_GPI_I16 (UNOPUS, lfrintnuhf, 2)
|
|
VAR1 (UNOPUS, lfrintnusf, 2, si)
|
|
VAR1 (UNOPUS, lfrintnudf, 2, di)
|
|
|
|
/* Implemented by <optab><fcvt_target><VDQF:mode>2. */
|
|
VAR1 (UNOP, floatv4hi, 2, v4hf)
|
|
VAR1 (UNOP, floatv8hi, 2, v8hf)
|
|
VAR1 (UNOP, floatv2si, 2, v2sf)
|
|
VAR1 (UNOP, floatv4si, 2, v4sf)
|
|
VAR1 (UNOP, floatv2di, 2, v2df)
|
|
|
|
VAR1 (UNOP, floatunsv4hi, 2, v4hf)
|
|
VAR1 (UNOP, floatunsv8hi, 2, v8hf)
|
|
VAR1 (UNOP, floatunsv2si, 2, v2sf)
|
|
VAR1 (UNOP, floatunsv4si, 2, v4sf)
|
|
VAR1 (UNOP, floatunsv2di, 2, v2df)
|
|
|
|
VAR5 (UNOPU, bswap, 2, v4hi, v8hi, v2si, v4si, v2di)
|
|
|
|
BUILTIN_VB (UNOP, rbit, 0)
|
|
|
|
/* Implemented by
|
|
aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */
|
|
BUILTIN_VALL (BINOP, zip1, 0)
|
|
BUILTIN_VALL (BINOP, zip2, 0)
|
|
BUILTIN_VALL (BINOP, uzp1, 0)
|
|
BUILTIN_VALL (BINOP, uzp2, 0)
|
|
BUILTIN_VALL (BINOP, trn1, 0)
|
|
BUILTIN_VALL (BINOP, trn2, 0)
|
|
|
|
/* Implemented by
|
|
aarch64_frecp<FRECP:frecp_suffix><mode>. */
|
|
BUILTIN_GPF_F16 (UNOP, frecpe, 0)
|
|
BUILTIN_GPF_F16 (UNOP, frecpx, 0)
|
|
|
|
BUILTIN_VDQ_SI (UNOP, urecpe, 0)
|
|
|
|
BUILTIN_VHSDF (UNOP, frecpe, 0)
|
|
BUILTIN_VHSDF_HSDF (BINOP, frecps, 0)
|
|
|
|
/* Implemented by a mixture of abs2 patterns. Note the DImode builtin is
|
|
only ever used for the int64x1_t intrinsic, there is no scalar version. */
|
|
BUILTIN_VSDQ_I_DI (UNOP, abs, 0)
|
|
BUILTIN_VHSDF (UNOP, abs, 2)
|
|
VAR1 (UNOP, abs, 2, hf)
|
|
|
|
BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10)
|
|
VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
|
|
VAR1 (BINOP, float_truncate_hi_, 0, v8hf)
|
|
|
|
VAR1 (UNOP, float_extend_lo_, 0, v2df)
|
|
VAR1 (UNOP, float_extend_lo_, 0, v4sf)
|
|
BUILTIN_VDF (UNOP, float_truncate_lo_, 0)
|
|
|
|
/* Implemented by aarch64_ld1<VALL_F16:mode>. */
|
|
BUILTIN_VALL_F16 (LOAD1, ld1, 0)
|
|
VAR1(STORE1P, ld1, 0, v2di)
|
|
|
|
/* Implemented by aarch64_st1<VALL_F16:mode>. */
|
|
BUILTIN_VALL_F16 (STORE1, st1, 0)
|
|
VAR1(STORE1P, st1, 0, v2di)
|
|
|
|
/* Implemented by fma<mode>4. */
|
|
BUILTIN_VHSDF (TERNOP, fma, 4)
|
|
VAR1 (TERNOP, fma, 4, hf)
|
|
/* Implemented by fnma<mode>4. */
|
|
BUILTIN_VHSDF (TERNOP, fnma, 4)
|
|
VAR1 (TERNOP, fnma, 4, hf)
|
|
|
|
/* Implemented by aarch64_simd_bsl<mode>. */
|
|
BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
|
|
VAR2 (BSL_P, simd_bsl,0, di, v2di)
|
|
BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
|
|
BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
|
|
|
|
/* Implemented by aarch64_crypto_aes<op><mode>. */
|
|
VAR1 (BINOPU, crypto_aese, 0, v16qi)
|
|
VAR1 (BINOPU, crypto_aesd, 0, v16qi)
|
|
VAR1 (UNOPU, crypto_aesmc, 0, v16qi)
|
|
VAR1 (UNOPU, crypto_aesimc, 0, v16qi)
|
|
|
|
/* Implemented by aarch64_crypto_sha1<op><mode>. */
|
|
VAR1 (UNOPU, crypto_sha1h, 0, si)
|
|
VAR1 (BINOPU, crypto_sha1su1, 0, v4si)
|
|
VAR1 (TERNOPU, crypto_sha1c, 0, v4si)
|
|
VAR1 (TERNOPU, crypto_sha1m, 0, v4si)
|
|
VAR1 (TERNOPU, crypto_sha1p, 0, v4si)
|
|
VAR1 (TERNOPU, crypto_sha1su0, 0, v4si)
|
|
|
|
/* Implemented by aarch64_crypto_sha256<op><mode>. */
|
|
VAR1 (TERNOPU, crypto_sha256h, 0, v4si)
|
|
VAR1 (TERNOPU, crypto_sha256h2, 0, v4si)
|
|
VAR1 (BINOPU, crypto_sha256su0, 0, v4si)
|
|
VAR1 (TERNOPU, crypto_sha256su1, 0, v4si)
|
|
|
|
/* Implemented by aarch64_crypto_pmull<mode>. */
|
|
VAR1 (BINOPP, crypto_pmull, 0, di)
|
|
VAR1 (BINOPP, crypto_pmull, 0, v2di)
|
|
|
|
/* Implemented by aarch64_tbl3<mode>. */
|
|
VAR1 (BINOP, tbl3, 0, v8qi)
|
|
VAR1 (BINOP, tbl3, 0, v16qi)
|
|
|
|
/* Implemented by aarch64_qtbl3<mode>. */
|
|
VAR1 (BINOP, qtbl3, 0, v8qi)
|
|
VAR1 (BINOP, qtbl3, 0, v16qi)
|
|
|
|
/* Implemented by aarch64_qtbl4<mode>. */
|
|
VAR1 (BINOP, qtbl4, 0, v8qi)
|
|
VAR1 (BINOP, qtbl4, 0, v16qi)
|
|
|
|
/* Implemented by aarch64_tbx4<mode>. */
|
|
VAR1 (TERNOP, tbx4, 0, v8qi)
|
|
VAR1 (TERNOP, tbx4, 0, v16qi)
|
|
|
|
/* Implemented by aarch64_qtbx3<mode>. */
|
|
VAR1 (TERNOP, qtbx3, 0, v8qi)
|
|
VAR1 (TERNOP, qtbx3, 0, v16qi)
|
|
|
|
/* Implemented by aarch64_qtbx4<mode>. */
|
|
VAR1 (TERNOP, qtbx4, 0, v8qi)
|
|
VAR1 (TERNOP, qtbx4, 0, v16qi)
|
|
|
|
/* Builtins for ARMv8.1-A Adv.SIMD instructions. */
|
|
|
|
/* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>. */
|
|
BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0)
|
|
BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0)
|
|
|
|
/* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>. */
|
|
BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0)
|
|
BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0)
|
|
|
|
/* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>. */
|
|
BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0)
|
|
BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)
|
|
|
|
/* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3. */
|
|
BUILTIN_VSDQ_HSDI (SHIFTIMM, scvtf, 3)
|
|
BUILTIN_VSDQ_HSDI (FCVTIMM_SUS, ucvtf, 3)
|
|
BUILTIN_VHSDF_HSDF (SHIFTIMM, fcvtzs, 3)
|
|
BUILTIN_VHSDF_HSDF (SHIFTIMM_USS, fcvtzu, 3)
|
|
VAR1 (SHIFTIMM, scvtfsi, 3, hf)
|
|
VAR1 (SHIFTIMM, scvtfdi, 3, hf)
|
|
VAR1 (FCVTIMM_SUS, ucvtfsi, 3, hf)
|
|
VAR1 (FCVTIMM_SUS, ucvtfdi, 3, hf)
|
|
BUILTIN_GPI (SHIFTIMM, fcvtzshf, 3)
|
|
BUILTIN_GPI (SHIFTIMM_USS, fcvtzuhf, 3)
|
|
|
|
/* Implemented by aarch64_rsqrte<mode>. */
|
|
BUILTIN_VHSDF_HSDF (UNOP, rsqrte, 0)
|
|
|
|
/* Implemented by aarch64_rsqrts<mode>. */
|
|
BUILTIN_VHSDF_HSDF (BINOP, rsqrts, 0)
|
|
|
|
/* Implemented by fabd<mode>3. */
|
|
BUILTIN_VHSDF_HSDF (BINOP, fabd, 3)
|
|
|
|
/* Implemented by aarch64_faddp<mode>. */
|
|
BUILTIN_VHSDF (BINOP, faddp, 0)
|
|
|
|
/* Implemented by aarch64_cm<optab><mode>. */
|
|
BUILTIN_VHSDF_HSDF (BINOP_USS, cmeq, 0)
|
|
BUILTIN_VHSDF_HSDF (BINOP_USS, cmge, 0)
|
|
BUILTIN_VHSDF_HSDF (BINOP_USS, cmgt, 0)
|
|
BUILTIN_VHSDF_HSDF (BINOP_USS, cmle, 0)
|
|
BUILTIN_VHSDF_HSDF (BINOP_USS, cmlt, 0)
|
|
|
|
/* Implemented by neg<mode>2. */
|
|
BUILTIN_VHSDF_HSDF (UNOP, neg, 2)
|
|
|
|
/* Implemented by aarch64_fac<optab><mode>. */
|
|
BUILTIN_VHSDF_HSDF (BINOP_USS, faclt, 0)
|
|
BUILTIN_VHSDF_HSDF (BINOP_USS, facle, 0)
|
|
BUILTIN_VHSDF_HSDF (BINOP_USS, facgt, 0)
|
|
BUILTIN_VHSDF_HSDF (BINOP_USS, facge, 0)
|
|
|
|
/* Implemented by sqrt<mode>2. */
|
|
VAR1 (UNOP, sqrt, 2, hf)
|
|
|
|
/* Implemented by <optab><mode>hf2. */
|
|
VAR1 (UNOP, floatdi, 2, hf)
|
|
VAR1 (UNOP, floatsi, 2, hf)
|
|
VAR1 (UNOP, floathi, 2, hf)
|
|
VAR1 (UNOPUS, floatunsdi, 2, hf)
|
|
VAR1 (UNOPUS, floatunssi, 2, hf)
|
|
VAR1 (UNOPUS, floatunshi, 2, hf)
|
|
BUILTIN_GPI_I16 (UNOP, fix_trunchf, 2)
|
|
BUILTIN_GPI (UNOP, fix_truncsf, 2)
|
|
BUILTIN_GPI (UNOP, fix_truncdf, 2)
|
|
BUILTIN_GPI_I16 (UNOPUS, fixuns_trunchf, 2)
|
|
BUILTIN_GPI (UNOPUS, fixuns_truncsf, 2)
|
|
BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2) |