164 lines
4.1 KiB
C++
164 lines
4.1 KiB
C++
/* Copyright (C) 2008-2019 Free Software Foundation, Inc.
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Contributed by Richard Henderson <rth@redhat.com>.
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This file is part of the GNU Transactional Memory Library (libitm).
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Libitm is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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// We'll be using some of the cpu builtins, and their associated types.
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#include <x86intrin.h>
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#include <cpuid.h>
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namespace GTM HIDDEN {
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/* ??? This doesn't work for Win64. */
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typedef struct gtm_jmpbuf
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{
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void *cfa;
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#ifdef __x86_64__
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unsigned long long rbx;
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unsigned long long rbp;
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unsigned long long r12;
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unsigned long long r13;
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unsigned long long r14;
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unsigned long long r15;
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unsigned long long ssp;
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unsigned long long rip;
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#else
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unsigned long ebx;
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unsigned long esi;
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unsigned long edi;
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unsigned long ebp;
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unsigned long ssp;
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unsigned long eip;
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#endif
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} gtm_jmpbuf;
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/* x86 doesn't require strict alignment for the basic types. */
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#define STRICT_ALIGNMENT 0
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/* The size of one line in hardware caches (in bytes). */
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#define HW_CACHELINE_SIZE 64
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static inline void
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cpu_relax (void)
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{
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__builtin_ia32_pause ();
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}
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// Use Intel RTM if supported by the assembler.
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// See gtm_thread::begin_transaction for how these functions are used.
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#ifdef HAVE_AS_RTM
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#define USE_HTM_FASTPATH
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#ifdef __x86_64__
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// Use the custom fastpath in ITM_beginTransaction.
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#define HTM_CUSTOM_FASTPATH
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#endif
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static inline bool
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htm_available ()
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{
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const unsigned cpuid_rtm = bit_RTM;
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unsigned vendor;
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if (__get_cpuid_max (0, &vendor) >= 7)
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{
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unsigned a, b, c, d;
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unsigned family;
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__cpuid (1, a, b, c, d);
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family = (a >> 8) & 0x0f;
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/* TSX is broken on some processors. TSX can be disabled by microcode,
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but we cannot reliably detect whether the microcode has been
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updated. Therefore, do not report availability of TSX on these
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processors. We use the same approach here as in glibc (see
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https://sourceware.org/ml/libc-alpha/2016-12/msg00470.html). */
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if (vendor == signature_INTEL_ebx && family == 0x06)
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{
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unsigned model = ((a >> 4) & 0x0f) + ((a >> 12) & 0xf0);
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unsigned stepping = a & 0x0f;
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if (model == 0x3c
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/* Xeon E7 v3 has correct TSX if stepping >= 4. */
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|| (model == 0x3f && stepping < 4)
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|| model == 0x45
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|| model == 0x46)
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return false;
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}
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__cpuid_count (7, 0, a, b, c, d);
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if (b & cpuid_rtm)
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return true;
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}
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return false;
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}
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static inline uint32_t
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htm_init ()
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{
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// Maximum number of times we try to execute a transaction as a HW
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// transaction.
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// ??? Why 2? Any offline or runtime tuning necessary?
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return htm_available () ? 2 : 0;
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}
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static inline uint32_t
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htm_begin ()
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{
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return _xbegin();
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}
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static inline bool
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htm_begin_success (uint32_t begin_ret)
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{
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return begin_ret == _XBEGIN_STARTED;
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}
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static inline void
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htm_commit ()
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{
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_xend();
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}
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static inline void
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htm_abort ()
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{
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// ??? According to a yet unpublished ABI rule, 0xff is reserved and
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// supposed to signal a busy lock. Source: andi.kleen@intel.com
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_xabort(0xff);
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}
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static inline bool
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htm_abort_should_retry (uint32_t begin_ret)
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{
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return begin_ret & _XABORT_RETRY;
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}
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/* Returns true iff a hardware transaction is currently being executed. */
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static inline bool
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htm_transaction_active ()
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{
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return _xtest() != 0;
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}
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#endif
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} // namespace GTM
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