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glibc/sysdeps/microblaze/atomic-machine.h

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Update copyright dates with scripts/update-copyrights. * All files with FSF copyright notices: Update copyright dates using scripts/update-copyrights. * locale/programs/charmap-kw.h: Regenerated. * locale/programs/locfile-kw.h: Likewise.
2018-01-01 01:32:25 +01:00
/* Copyright (C) 2003-2018 Free Software Foundation, Inc.
MicroBlaze Port Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2012-01-10 06:38:42 +01:00
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library. If not, see
<http://www.gnu.org/licenses/>. */
#include <stdint.h>
#include <sysdep.h>
typedef int8_t atomic8_t;
typedef uint8_t uatomic8_t;
typedef int_fast8_t atomic_fast8_t;
typedef uint_fast8_t uatomic_fast8_t;
typedef int32_t atomic32_t;
typedef uint32_t uatomic32_t;
typedef int_fast32_t atomic_fast32_t;
typedef uint_fast32_t uatomic_fast32_t;
typedef intptr_t atomicptr_t;
typedef uintptr_t uatomicptr_t;
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
microblaze: 64b atomic operations are not supported.
2014-11-21 14:09:21 +01:00
#define __HAVE_64B_ATOMICS 0
Add arch-specific configuration for C11 atomics support. This sets __HAVE_64B_ATOMICS if provided. It also sets USE_ATOMIC_COMPILER_BUILTINS to true if the existing atomic ops use the __atomic* builtins (aarch64, mips partially) or if this has been tested (x86_64); otherwise, this is set to false so that C11 atomics will be based on the existing atomic operations.
2014-10-18 01:02:59 +02:00
#define USE_ATOMIC_COMPILER_BUILTINS 0
Optimize generic spinlock code and use C11 like atomic macros. This patch optimizes the generic spinlock code. The type pthread_spinlock_t is a typedef to volatile int on all archs. Passing a volatile pointer to the atomic macros which are not mapped to the C11 atomic builtins can lead to extra stores and loads to stack if such a macro creates a temporary variable by using "__typeof (*(mem)) tmp;". Thus, those macros which are used by spinlock code - atomic_exchange_acquire, atomic_load_relaxed, atomic_compare_exchange_weak - have to be adjusted. According to the comment from Szabolcs Nagy, the type of a cast expression is unqualified (see http://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_423.htm): __typeof ((__typeof (*(mem)) *(mem)) tmp; Thus from spinlock perspective the variable tmp is of type int instead of type volatile int. This patch adjusts those macros in include/atomic.h. With this construct GCC >= 5 omits the extra stores and loads. The atomic macros are replaced by the C11 like atomic macros and thus the code is aligned to it. The pthread_spin_unlock implementation is now using release memory order instead of sequentially consistent memory order. The issue with passed volatile int pointers applies to the C11 like atomic macros as well as the ones used before. I've added a glibc_likely hint to the first atomic exchange in pthread_spin_lock in order to return immediately to the caller if the lock is free. Without the hint, there is an additional jump if the lock is free. I've added the atomic_spin_nop macro within the loop of plain reads. The plain reads are also realized by C11 like atomic_load_relaxed macro. The new define ATOMIC_EXCHANGE_USES_CAS determines if the first try to acquire the spinlock in pthread_spin_lock or pthread_spin_trylock is an exchange or a CAS. This is defined in atomic-machine.h for all architectures. The define SPIN_LOCK_READS_BETWEEN_CMPXCHG is now removed. There is no technical reason for throwing in a CAS every now and then, and so far we have no evidence that it can improve performance. If that would be the case, we have to adjust other spin-waiting loops elsewhere, too! Using a CAS loop without plain reads is not a good idea on many targets and wasn't used by one. Thus there is now no option to do so. Architectures are now using the generic spinlock automatically if they do not provide an own implementation. Thus the pthread_spin_lock.c files in sysdeps folder are deleted. ChangeLog: * NEWS: Mention new spinlock implementation. * include/atomic.h: (__atomic_val_bysize): Cast type to omit volatile qualifier. (atomic_exchange_acq): Likewise. (atomic_load_relaxed): Likewise. (ATOMIC_EXCHANGE_USES_CAS): Check definition. * nptl/pthread_spin_init.c (pthread_spin_init): Use atomic_store_relaxed. * nptl/pthread_spin_lock.c (pthread_spin_lock): Use C11-like atomic macros. * nptl/pthread_spin_trylock.c (pthread_spin_trylock): Likewise. * nptl/pthread_spin_unlock.c (pthread_spin_unlock): Use atomic_store_release. * sysdeps/aarch64/nptl/pthread_spin_lock.c: Delete File. * sysdeps/arm/nptl/pthread_spin_lock.c: Likewise. * sysdeps/hppa/nptl/pthread_spin_lock.c: Likewise. * sysdeps/m68k/nptl/pthread_spin_lock.c: Likewise. * sysdeps/microblaze/nptl/pthread_spin_lock.c: Likewise. * sysdeps/mips/nptl/pthread_spin_lock.c: Likewise. * sysdeps/nios2/nptl/pthread_spin_lock.c: Likewise. * sysdeps/aarch64/atomic-machine.h (ATOMIC_EXCHANGE_USES_CAS): Define. * sysdeps/alpha/atomic-machine.h: Likewise. * sysdeps/arm/atomic-machine.h: Likewise. * sysdeps/i386/atomic-machine.h: Likewise. * sysdeps/ia64/atomic-machine.h: Likewise. * sysdeps/m68k/coldfire/atomic-machine.h: Likewise. * sysdeps/m68k/m680x0/m68020/atomic-machine.h: Likewise. * sysdeps/microblaze/atomic-machine.h: Likewise. * sysdeps/mips/atomic-machine.h: Likewise. * sysdeps/powerpc/powerpc32/atomic-machine.h: Likewise. * sysdeps/powerpc/powerpc64/atomic-machine.h: Likewise. * sysdeps/s390/atomic-machine.h: Likewise. * sysdeps/sparc/sparc32/atomic-machine.h: Likewise. * sysdeps/sparc/sparc32/sparcv9/atomic-machine.h: Likewise. * sysdeps/sparc/sparc64/atomic-machine.h: Likewise. * sysdeps/tile/tilegx/atomic-machine.h: Likewise. * sysdeps/tile/tilepro/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/hppa/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/nios2/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/sh/atomic-machine.h: Likewise. * sysdeps/x86_64/atomic-machine.h: Likewise.
2017-06-06 09:41:56 +02:00
/* XXX Is this actually correct? */
#define ATOMIC_EXCHANGE_USES_CAS 1
MicroBlaze Port Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2012-01-10 06:38:42 +01:00
/* Microblaze does not have byte and halfword forms of load and reserve and
store conditional. So for microblaze we stub out the 8- and 16-bit forms. */
#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
(abort (), 0)
#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
(abort (), 0)
#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
({ \
__typeof (*(mem)) __tmp; \
__typeof (mem) __memp = (mem); \
int test; \
__asm __volatile ( \
" addc r0, r0, r0;" \
"1: lwx %0, %3, r0;" \
" addic %1, r0, 0;" \
" bnei %1, 1b;" \
" cmp %1, %0, %4;" \
" bnei %1, 2f;" \
" swx %5, %3, r0;" \
" addic %1, r0, 0;" \
" bnei %1, 1b;" \
"2:" \
: "=&r" (__tmp), \
"=&r" (test), \
"=m" (*__memp) \
: "r" (__memp), \
"r" (oldval), \
"r" (newval) \
: "cc", "memory"); \
__tmp; \
})
#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
({ \
__typeof (*(mem)) __result; \
if (sizeof (*mem) == 4) \
__result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \
else if (sizeof (*mem) == 8) \
__result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \
else \
abort (); \
__result; \
})
#define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \
({ \
__typeof (*(mem)) __result; \
if (sizeof (*mem) == 4) \
__result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \
else if (sizeof (*mem) == 8) \
__result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \
else \
abort (); \
__result; \
})
#define __arch_atomic_exchange_32_acq(mem, value) \
({ \
__typeof (*(mem)) __tmp; \
__typeof (mem) __memp = (mem); \
int test; \
__asm __volatile ( \
" addc r0, r0, r0;" \
"1: lwx %0, %4, r0;" \
" addic %1, r0, 0;" \
" bnei %1, 1b;" \
" swx %3, %4, r0;" \
" addic %1, r0, 0;" \
" bnei %1, 1b;" \
: "=&r" (__tmp), \
"=&r" (test), \
"=m" (*__memp) \
: "r" (value), \
"r" (__memp) \
: "cc", "memory"); \
__tmp; \
})
#define __arch_atomic_exchange_64_acq(mem, newval) \
(abort (), (__typeof (*mem)) 0)
#define atomic_exchange_acq(mem, value) \
({ \
__typeof (*(mem)) __result; \
if (sizeof (*mem) == 4) \
__result = __arch_atomic_exchange_32_acq (mem, value); \
else if (sizeof (*mem) == 8) \
__result = __arch_atomic_exchange_64_acq (mem, value); \
else \
abort (); \
__result; \
})
#define atomic_exchange_rel(mem, value) \
({ \
__typeof (*(mem)) __result; \
if (sizeof (*mem) == 4) \
__result = __arch_atomic_exchange_32_acq (mem, value); \
else if (sizeof (*mem) == 8) \
__result = __arch_atomic_exchange_64_acq (mem, value); \
else \
abort (); \
__result; \
})
#define __arch_atomic_exchange_and_add_32(mem, value) \
({ \
__typeof (*(mem)) __tmp; \
__typeof (mem) __memp = (mem); \
int test; \
__asm __volatile ( \
" addc r0, r0, r0;" \
"1: lwx %0, %4, r0;" \
" addic %1, r0, 0;" \
" bnei %1, 1b;" \
" add %1, %3, %0;" \
" swx %1, %4, r0;" \
" addic %1, r0, 0;" \
" bnei %1, 1b;" \
: "=&r" (__tmp), \
"=&r" (test), \
"=m" (*__memp) \
: "r" (value), \
"r" (__memp) \
: "cc", "memory"); \
__tmp; \
})
#define __arch_atomic_exchange_and_add_64(mem, value) \
(abort (), (__typeof (*mem)) 0)
#define atomic_exchange_and_add(mem, value) \
({ \
__typeof (*(mem)) __result; \
if (sizeof (*mem) == 4) \
__result = __arch_atomic_exchange_and_add_32 (mem, value); \
else if (sizeof (*mem) == 8) \
__result = __arch_atomic_exchange_and_add_64 (mem, value); \
else \
abort (); \
__result; \
})
#define __arch_atomic_increment_val_32(mem) \
({ \
__typeof (*(mem)) __val; \
int test; \
__asm __volatile ( \
" addc r0, r0, r0;" \
"1: lwx %0, %3, r0;" \
" addic %1, r0, 0;" \
" bnei %1, 1b;" \
" addi %0, %0, 1;" \
" swx %0, %3, r0;" \
" addic %1, r0, 0;" \
" bnei %1, 1b;" \
: "=&r" (__val), \
"=&r" (test), \
"=m" (*mem) \
: "r" (mem), \
"m" (*mem) \
: "cc", "memory"); \
__val; \
})
#define __arch_atomic_increment_val_64(mem) \
(abort (), (__typeof (*mem)) 0)
#define atomic_increment_val(mem) \
({ \
__typeof (*(mem)) __result; \
if (sizeof (*(mem)) == 4) \
__result = __arch_atomic_increment_val_32 (mem); \
else if (sizeof (*(mem)) == 8) \
__result = __arch_atomic_increment_val_64 (mem); \
else \
abort (); \
__result; \
})
#define atomic_increment(mem) ({ atomic_increment_val (mem); (void) 0; })
#define __arch_atomic_decrement_val_32(mem) \
({ \
__typeof (*(mem)) __val; \
int test; \
__asm __volatile ( \
" addc r0, r0, r0;" \
"1: lwx %0, %3, r0;" \
" addic %1, r0, 0;" \
" bnei %1, 1b;" \
" rsubi %0, %0, 1;" \
" swx %0, %3, r0;" \
" addic %1, r0, 0;" \
" bnei %1, 1b;" \
: "=&r" (__val), \
"=&r" (test), \
"=m" (*mem) \
: "r" (mem), \
"m" (*mem) \
: "cc", "memory"); \
__val; \
})
#define __arch_atomic_decrement_val_64(mem) \
(abort (), (__typeof (*mem)) 0)
#define atomic_decrement_val(mem) \
({ \
__typeof (*(mem)) __result; \
if (sizeof (*(mem)) == 4) \
__result = __arch_atomic_decrement_val_32 (mem); \
else if (sizeof (*(mem)) == 8) \
__result = __arch_atomic_decrement_val_64 (mem); \
else \
abort (); \
__result; \
})
#define atomic_decrement(mem) ({ atomic_decrement_val (mem); (void) 0; })