2003-04-17 21:19:29 +02:00
|
|
|
/* Atomic operations. PowerPC64 version.
|
2016-01-04 17:05:18 +01:00
|
|
|
Copyright (C) 2003-2016 Free Software Foundation, Inc.
|
2003-04-17 21:19:29 +02:00
|
|
|
This file is part of the GNU C Library.
|
|
|
|
Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
|
|
|
|
|
|
|
|
The GNU C Library is free software; you can redistribute it and/or
|
|
|
|
modify it under the terms of the GNU Lesser General Public
|
|
|
|
License as published by the Free Software Foundation; either
|
|
|
|
version 2.1 of the License, or (at your option) any later version.
|
|
|
|
|
|
|
|
The GNU C Library is distributed in the hope that it will be useful,
|
|
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
Lesser General Public License for more details.
|
|
|
|
|
|
|
|
You should have received a copy of the GNU Lesser General Public
|
2012-02-10 00:18:22 +01:00
|
|
|
License along with the GNU C Library; if not, see
|
|
|
|
<http://www.gnu.org/licenses/>. */
|
2003-04-17 21:19:29 +02:00
|
|
|
|
2007-03-26 22:16:39 +02:00
|
|
|
/* POWER6 adds a "Mutex Hint" to the Load and Reserve instruction.
|
|
|
|
This is a hint to the hardware to expect additional updates adjacent
|
|
|
|
to the lock word or not. If we are acquiring a Mutex, the hint
|
|
|
|
should be true. Otherwise we releasing a Mutex or doing a simple
|
2013-01-07 18:20:53 +01:00
|
|
|
atomic operation. In that case we don't expect additional updates
|
2007-03-26 22:16:39 +02:00
|
|
|
adjacent to the lock word after the Store Conditional and the hint
|
|
|
|
should be false. */
|
|
|
|
|
|
|
|
#if defined _ARCH_PWR6 || defined _ARCH_PWR6X
|
|
|
|
# define MUTEX_HINT_ACQ ",1"
|
|
|
|
# define MUTEX_HINT_REL ",0"
|
|
|
|
#else
|
|
|
|
# define MUTEX_HINT_ACQ
|
|
|
|
# define MUTEX_HINT_REL
|
|
|
|
#endif
|
|
|
|
|
2014-10-18 01:02:59 +02:00
|
|
|
#define __HAVE_64B_ATOMICS 1
|
|
|
|
#define USE_ATOMIC_COMPILER_BUILTINS 0
|
|
|
|
|
2004-08-26 01:24:20 +02:00
|
|
|
/* The 32-bit exchange_bool is different on powerpc64 because the subf
|
2013-01-07 18:20:53 +01:00
|
|
|
does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
|
2004-08-26 01:24:20 +02:00
|
|
|
(a load word and zero (high 32) form) load.
|
|
|
|
In powerpc64 register values are 64-bit by default, including oldval.
|
|
|
|
The value in old val unknown sign extension, lwarx loads the 32-bit
|
|
|
|
value as unsigned. So we explicitly clear the high 32 bits in oldval. */
|
2007-03-26 22:16:39 +02:00
|
|
|
#define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
|
2003-04-17 21:19:29 +02:00
|
|
|
({ \
|
2004-08-26 01:24:20 +02:00
|
|
|
unsigned int __tmp, __tmp2; \
|
|
|
|
__asm __volatile (" clrldi %1,%1,32\n" \
|
2007-03-26 22:16:39 +02:00
|
|
|
"1: lwarx %0,0,%2" MUTEX_HINT_ACQ "\n" \
|
2004-08-26 01:24:20 +02:00
|
|
|
" subf. %0,%1,%0\n" \
|
2003-04-17 21:19:29 +02:00
|
|
|
" bne 2f\n" \
|
2004-08-26 01:24:20 +02:00
|
|
|
" stwcx. %4,0,%2\n" \
|
2003-04-17 21:19:29 +02:00
|
|
|
" bne- 1b\n" \
|
|
|
|
"2: " __ARCH_ACQ_INSTR \
|
2004-08-26 01:24:20 +02:00
|
|
|
: "=&r" (__tmp), "=r" (__tmp2) \
|
|
|
|
: "b" (mem), "1" (oldval), "r" (newval) \
|
2003-04-17 21:19:29 +02:00
|
|
|
: "cr0", "memory"); \
|
|
|
|
__tmp != 0; \
|
|
|
|
})
|
|
|
|
|
2007-03-26 22:16:39 +02:00
|
|
|
#define __arch_compare_and_exchange_bool_32_rel(mem, newval, oldval) \
|
2003-05-13 23:14:28 +02:00
|
|
|
({ \
|
2004-08-26 01:24:20 +02:00
|
|
|
unsigned int __tmp, __tmp2; \
|
2003-05-13 23:14:28 +02:00
|
|
|
__asm __volatile (__ARCH_REL_INSTR "\n" \
|
2004-08-26 01:24:20 +02:00
|
|
|
" clrldi %1,%1,32\n" \
|
2007-03-26 22:16:39 +02:00
|
|
|
"1: lwarx %0,0,%2" MUTEX_HINT_REL "\n" \
|
2004-08-26 01:24:20 +02:00
|
|
|
" subf. %0,%1,%0\n" \
|
2003-05-13 23:14:28 +02:00
|
|
|
" bne 2f\n" \
|
2004-08-26 01:24:20 +02:00
|
|
|
" stwcx. %4,0,%2\n" \
|
2003-05-13 23:14:28 +02:00
|
|
|
" bne- 1b\n" \
|
|
|
|
"2: " \
|
2004-08-26 01:24:20 +02:00
|
|
|
: "=&r" (__tmp), "=r" (__tmp2) \
|
2004-08-26 01:27:17 +02:00
|
|
|
: "b" (mem), "1" (oldval), "r" (newval) \
|
2003-05-13 23:14:28 +02:00
|
|
|
: "cr0", "memory"); \
|
|
|
|
__tmp != 0; \
|
|
|
|
})
|
|
|
|
|
2004-04-04 05:32:19 +02:00
|
|
|
/*
|
|
|
|
* Only powerpc64 processors support Load doubleword and reserve index (ldarx)
|
2003-04-17 21:19:29 +02:00
|
|
|
* and Store doubleword conditional indexed (stdcx) instructions. So here
|
|
|
|
* we define the 64-bit forms.
|
|
|
|
*/
|
2007-03-26 22:16:39 +02:00
|
|
|
#define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
|
2003-04-17 21:19:29 +02:00
|
|
|
({ \
|
|
|
|
unsigned long __tmp; \
|
2003-05-13 23:14:28 +02:00
|
|
|
__asm __volatile ( \
|
2007-03-26 22:16:39 +02:00
|
|
|
"1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
|
2003-04-17 21:19:29 +02:00
|
|
|
" subf. %0,%2,%0\n" \
|
|
|
|
" bne 2f\n" \
|
|
|
|
" stdcx. %3,0,%1\n" \
|
|
|
|
" bne- 1b\n" \
|
|
|
|
"2: " __ARCH_ACQ_INSTR \
|
|
|
|
: "=&r" (__tmp) \
|
|
|
|
: "b" (mem), "r" (oldval), "r" (newval) \
|
|
|
|
: "cr0", "memory"); \
|
|
|
|
__tmp != 0; \
|
|
|
|
})
|
|
|
|
|
2007-03-26 22:16:39 +02:00
|
|
|
#define __arch_compare_and_exchange_bool_64_rel(mem, newval, oldval) \
|
2003-05-13 23:14:28 +02:00
|
|
|
({ \
|
|
|
|
unsigned long __tmp; \
|
|
|
|
__asm __volatile (__ARCH_REL_INSTR "\n" \
|
2014-11-25 13:26:12 +01:00
|
|
|
"1: ldarx %0,0,%1" MUTEX_HINT_REL "\n" \
|
2003-05-13 23:14:28 +02:00
|
|
|
" subf. %0,%2,%0\n" \
|
|
|
|
" bne 2f\n" \
|
|
|
|
" stdcx. %3,0,%1\n" \
|
|
|
|
" bne- 1b\n" \
|
|
|
|
"2: " \
|
|
|
|
: "=&r" (__tmp) \
|
|
|
|
: "b" (mem), "r" (oldval), "r" (newval) \
|
|
|
|
: "cr0", "memory"); \
|
|
|
|
__tmp != 0; \
|
|
|
|
})
|
|
|
|
|
2003-04-17 21:19:29 +02:00
|
|
|
#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
|
|
|
|
({ \
|
|
|
|
__typeof (*(mem)) __tmp; \
|
|
|
|
__typeof (mem) __memp = (mem); \
|
2003-05-13 23:14:28 +02:00
|
|
|
__asm __volatile ( \
|
2007-03-26 22:16:39 +02:00
|
|
|
"1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
|
2003-04-17 21:19:29 +02:00
|
|
|
" cmpd %0,%2\n" \
|
|
|
|
" bne 2f\n" \
|
|
|
|
" stdcx. %3,0,%1\n" \
|
|
|
|
" bne- 1b\n" \
|
|
|
|
"2: " __ARCH_ACQ_INSTR \
|
|
|
|
: "=&r" (__tmp) \
|
|
|
|
: "b" (__memp), "r" (oldval), "r" (newval) \
|
|
|
|
: "cr0", "memory"); \
|
|
|
|
__tmp; \
|
|
|
|
})
|
|
|
|
|
2003-05-13 23:14:28 +02:00
|
|
|
#define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \
|
|
|
|
({ \
|
|
|
|
__typeof (*(mem)) __tmp; \
|
|
|
|
__typeof (mem) __memp = (mem); \
|
|
|
|
__asm __volatile (__ARCH_REL_INSTR "\n" \
|
2007-03-26 22:16:39 +02:00
|
|
|
"1: ldarx %0,0,%1" MUTEX_HINT_REL "\n" \
|
2003-05-13 23:14:28 +02:00
|
|
|
" cmpd %0,%2\n" \
|
|
|
|
" bne 2f\n" \
|
|
|
|
" stdcx. %3,0,%1\n" \
|
|
|
|
" bne- 1b\n" \
|
|
|
|
"2: " \
|
|
|
|
: "=&r" (__tmp) \
|
|
|
|
: "b" (__memp), "r" (oldval), "r" (newval) \
|
|
|
|
: "cr0", "memory"); \
|
|
|
|
__tmp; \
|
|
|
|
})
|
|
|
|
|
2007-03-26 22:16:39 +02:00
|
|
|
#define __arch_atomic_exchange_64_acq(mem, value) \
|
2003-05-13 23:14:28 +02:00
|
|
|
({ \
|
|
|
|
__typeof (*mem) __val; \
|
|
|
|
__asm __volatile (__ARCH_REL_INSTR "\n" \
|
2007-03-26 22:16:39 +02:00
|
|
|
"1: ldarx %0,0,%2" MUTEX_HINT_ACQ "\n" \
|
2003-05-13 23:14:28 +02:00
|
|
|
" stdcx. %3,0,%2\n" \
|
|
|
|
" bne- 1b\n" \
|
|
|
|
" " __ARCH_ACQ_INSTR \
|
|
|
|
: "=&r" (__val), "=m" (*mem) \
|
2004-04-04 05:32:19 +02:00
|
|
|
: "b" (mem), "r" (value), "m" (*mem) \
|
2003-05-13 23:14:28 +02:00
|
|
|
: "cr0", "memory"); \
|
|
|
|
__val; \
|
|
|
|
})
|
|
|
|
|
2007-03-26 22:16:39 +02:00
|
|
|
#define __arch_atomic_exchange_64_rel(mem, value) \
|
2003-04-17 21:19:29 +02:00
|
|
|
({ \
|
|
|
|
__typeof (*mem) __val; \
|
|
|
|
__asm __volatile (__ARCH_REL_INSTR "\n" \
|
2007-03-26 22:16:39 +02:00
|
|
|
"1: ldarx %0,0,%2" MUTEX_HINT_REL "\n" \
|
2003-04-17 21:19:29 +02:00
|
|
|
" stdcx. %3,0,%2\n" \
|
|
|
|
" bne- 1b" \
|
|
|
|
: "=&r" (__val), "=m" (*mem) \
|
2004-04-04 05:32:19 +02:00
|
|
|
: "b" (mem), "r" (value), "m" (*mem) \
|
2003-05-13 23:14:28 +02:00
|
|
|
: "cr0", "memory"); \
|
2003-04-17 21:19:29 +02:00
|
|
|
__val; \
|
|
|
|
})
|
|
|
|
|
2007-03-26 22:16:39 +02:00
|
|
|
#define __arch_atomic_exchange_and_add_64(mem, value) \
|
2003-04-17 21:19:29 +02:00
|
|
|
({ \
|
|
|
|
__typeof (*mem) __val, __tmp; \
|
|
|
|
__asm __volatile ("1: ldarx %0,0,%3\n" \
|
|
|
|
" add %1,%0,%4\n" \
|
|
|
|
" stdcx. %1,0,%3\n" \
|
2014-11-25 20:32:54 +01:00
|
|
|
" bne- 1b" \
|
|
|
|
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
|
|
|
|
: "b" (mem), "r" (value), "m" (*mem) \
|
|
|
|
: "cr0", "memory"); \
|
|
|
|
__val; \
|
|
|
|
})
|
|
|
|
|
|
|
|
#define __arch_atomic_exchange_and_add_64_acq(mem, value) \
|
|
|
|
({ \
|
|
|
|
__typeof (*mem) __val, __tmp; \
|
|
|
|
__asm __volatile ("1: ldarx %0,0,%3" MUTEX_HINT_ACQ "\n" \
|
|
|
|
" add %1,%0,%4\n" \
|
|
|
|
" stdcx. %1,0,%3\n" \
|
|
|
|
" bne- 1b\n" \
|
|
|
|
__ARCH_ACQ_INSTR \
|
|
|
|
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
|
|
|
|
: "b" (mem), "r" (value), "m" (*mem) \
|
|
|
|
: "cr0", "memory"); \
|
|
|
|
__val; \
|
|
|
|
})
|
|
|
|
|
|
|
|
#define __arch_atomic_exchange_and_add_64_rel(mem, value) \
|
|
|
|
({ \
|
|
|
|
__typeof (*mem) __val, __tmp; \
|
|
|
|
__asm __volatile (__ARCH_REL_INSTR "\n" \
|
|
|
|
"1: ldarx %0,0,%3" MUTEX_HINT_REL "\n" \
|
|
|
|
" add %1,%0,%4\n" \
|
|
|
|
" stdcx. %1,0,%3\n" \
|
2003-04-17 21:19:29 +02:00
|
|
|
" bne- 1b" \
|
|
|
|
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
|
2004-04-04 05:32:19 +02:00
|
|
|
: "b" (mem), "r" (value), "m" (*mem) \
|
2004-09-08 08:09:02 +02:00
|
|
|
: "cr0", "memory"); \
|
|
|
|
__val; \
|
|
|
|
})
|
|
|
|
|
2007-03-26 22:16:39 +02:00
|
|
|
#define __arch_atomic_increment_val_64(mem) \
|
2004-09-08 08:09:02 +02:00
|
|
|
({ \
|
|
|
|
__typeof (*(mem)) __val; \
|
|
|
|
__asm __volatile ("1: ldarx %0,0,%2\n" \
|
|
|
|
" addi %0,%0,1\n" \
|
|
|
|
" stdcx. %0,0,%2\n" \
|
|
|
|
" bne- 1b" \
|
|
|
|
: "=&b" (__val), "=m" (*mem) \
|
|
|
|
: "b" (mem), "m" (*mem) \
|
|
|
|
: "cr0", "memory"); \
|
|
|
|
__val; \
|
|
|
|
})
|
|
|
|
|
2007-03-26 22:16:39 +02:00
|
|
|
#define __arch_atomic_decrement_val_64(mem) \
|
2004-09-08 08:09:02 +02:00
|
|
|
({ \
|
|
|
|
__typeof (*(mem)) __val; \
|
|
|
|
__asm __volatile ("1: ldarx %0,0,%2\n" \
|
|
|
|
" subi %0,%0,1\n" \
|
|
|
|
" stdcx. %0,0,%2\n" \
|
|
|
|
" bne- 1b" \
|
|
|
|
: "=&b" (__val), "=m" (*mem) \
|
|
|
|
: "b" (mem), "m" (*mem) \
|
2003-05-13 23:14:28 +02:00
|
|
|
: "cr0", "memory"); \
|
2003-04-17 21:19:29 +02:00
|
|
|
__val; \
|
|
|
|
})
|
|
|
|
|
2007-03-26 22:16:39 +02:00
|
|
|
#define __arch_atomic_decrement_if_positive_64(mem) \
|
2003-04-17 21:19:29 +02:00
|
|
|
({ int __val, __tmp; \
|
|
|
|
__asm __volatile ("1: ldarx %0,0,%3\n" \
|
|
|
|
" cmpdi 0,%0,0\n" \
|
|
|
|
" addi %1,%0,-1\n" \
|
|
|
|
" ble 2f\n" \
|
|
|
|
" stdcx. %1,0,%3\n" \
|
|
|
|
" bne- 1b\n" \
|
|
|
|
"2: " __ARCH_ACQ_INSTR \
|
|
|
|
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
|
2004-04-04 05:32:19 +02:00
|
|
|
: "b" (mem), "m" (*mem) \
|
2003-05-13 23:14:28 +02:00
|
|
|
: "cr0", "memory"); \
|
2003-04-17 21:19:29 +02:00
|
|
|
__val; \
|
|
|
|
})
|
|
|
|
|
2004-04-04 05:32:19 +02:00
|
|
|
/*
|
|
|
|
* All powerpc64 processors support the new "light weight" sync (lwsync).
|
2003-04-17 21:19:29 +02:00
|
|
|
*/
|
2007-03-26 22:16:39 +02:00
|
|
|
#define atomic_read_barrier() __asm ("lwsync" ::: "memory")
|
2004-04-04 05:32:19 +02:00
|
|
|
/*
|
|
|
|
* "light weight" sync can also be used for the release barrier.
|
2003-05-13 23:14:28 +02:00
|
|
|
*/
|
2007-03-26 22:16:39 +02:00
|
|
|
#ifndef UP
|
|
|
|
# define __ARCH_REL_INSTR "lwsync"
|
|
|
|
#endif
|
2014-10-18 01:01:58 +02:00
|
|
|
#define atomic_write_barrier() __asm ("lwsync" ::: "memory")
|
2003-04-17 21:19:29 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Include the rest of the atomic ops macros which are common to both
|
2004-04-04 05:32:19 +02:00
|
|
|
* powerpc32 and powerpc64.
|
2003-04-17 21:19:29 +02:00
|
|
|
*/
|
2015-09-11 22:00:19 +02:00
|
|
|
#include_next <atomic-machine.h>
|