* sysdeps/i386/i486/bits/atomic.h: Add catomic_* support.
This commit is contained in:
parent
6c7e1cf59e
commit
37fb75957c
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@ -1,3 +1,7 @@
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2006-10-11 Ulrich Drepper <drepper@redhat.com>
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* sysdeps/i386/i486/bits/atomic.h: Add catomic_* support.
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2006-10-11 Jakub Jelinek <jakub@redhat.com>
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* malloc/malloc.c (_int_malloc): Remove unused any_larger variable.
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@ -18,6 +18,7 @@
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02111-1307 USA. */
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#include <stdint.h>
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#include <tls.h> /* For tcbhead_t. */
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typedef int8_t atomic8_t;
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@ -76,6 +77,40 @@ typedef uintmax_t uatomic_max_t;
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: "r" (newval), "m" (*mem), "0" (oldval)); \
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ret; })
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#define __arch_c_compare_and_exchange_val_8_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%gs:%P5\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchgb %b2, %1" \
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: "=a" (ret), "=m" (*mem) \
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: "q" (newval), "m" (*mem), "0" (oldval), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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#define __arch_c_compare_and_exchange_val_16_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%gs:%P5\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchgw %w2, %1" \
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: "=a" (ret), "=m" (*mem) \
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: "r" (newval), "m" (*mem), "0" (oldval), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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#define __arch_c_compare_and_exchange_val_32_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%gs:%P5\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchgl %2, %1" \
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: "=a" (ret), "=m" (*mem) \
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: "r" (newval), "m" (*mem), "0" (oldval), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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/* XXX We do not really need 64-bit compare-and-exchange. At least
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not in the moment. Using it would mean causing portability
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problems since not many other 32-bit architectures have support for
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@ -85,6 +120,8 @@ typedef uintmax_t uatomic_max_t;
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#if 1
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# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret = *(mem); abort (); ret = (newval); ret = (oldval); })
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# define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret = *(mem); abort (); ret = (newval); ret = (oldval); })
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#else
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# ifdef __PIC__
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# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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@ -100,6 +137,24 @@ typedef uintmax_t uatomic_max_t;
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& 0xffffffff), \
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"d" (((unsigned long long int) (oldval)) >> 32)); \
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ret; })
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# define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("xchgl %2, %%ebx\n\t" \
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"cmpl $0, %%gs:%P7\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchg8b %1\n\t" \
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"xchgl %2, %%ebx" \
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: "=A" (ret), "=m" (*mem) \
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: "DS" (((unsigned long long int) (newval)) \
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& 0xffffffff), \
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"c" (((unsigned long long int) (newval)) >> 32), \
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"m" (*mem), "a" (((unsigned long long int) (oldval)) \
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& 0xffffffff), \
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"d" (((unsigned long long int) (oldval)) >> 32), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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# else
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# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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@ -112,6 +167,22 @@ typedef uintmax_t uatomic_max_t;
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& 0xffffffff), \
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"d" (((unsigned long long int) (oldval)) >> 32)); \
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ret; })
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# define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%gs:%P7\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchg8b %1" \
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: "=A" (ret), "=m" (*mem) \
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: "b" (((unsigned long long int) (newval)) \
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& 0xffffffff), \
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"c" (((unsigned long long int) (newval)) >> 32), \
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"m" (*mem), "a" (((unsigned long long int) (oldval)) \
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& 0xffffffff), \
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"d" (((unsigned long long int) (oldval)) >> 32), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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# endif
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#endif
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@ -139,21 +210,24 @@ typedef uintmax_t uatomic_max_t;
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result; })
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#define atomic_exchange_and_add(mem, value) \
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#define __arch_exchange_and_add_body(lock, pfx, mem, value) \
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({ __typeof (*mem) __result; \
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__typeof (value) __addval = (value); \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "xaddb %b0, %1" \
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__asm __volatile (lock "xaddb %b0, %1" \
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: "=r" (__result), "=m" (*mem) \
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: "0" (__addval), "m" (*mem)); \
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: "0" (__addval), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "xaddw %w0, %1" \
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__asm __volatile (lock "xaddw %w0, %1" \
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: "=r" (__result), "=m" (*mem) \
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: "0" (__addval), "m" (*mem)); \
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: "0" (__addval), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "xaddl %0, %1" \
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__asm __volatile (lock "xaddl %0, %1" \
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: "=r" (__result), "=m" (*mem) \
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: "0" (__addval), "m" (*mem)); \
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: "0" (__addval), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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{ \
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__typeof (mem) __memp = (mem); \
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__result = *__memp; \
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do \
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__tmpval = __result; \
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while ((__result = __arch_compare_and_exchange_val_64_acq \
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while ((__result = pfx##_compare_and_exchange_val_64_acq \
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(__memp, __result + __addval, __result)) == __tmpval); \
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} \
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__result; })
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#define atomic_exchange_and_add(mem, value) \
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__arch_exchange_and_add_body (LOCK_PREFIX, __arch, mem, value)
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#define atomic_add(mem, value) \
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#define __arch_exchange_and_add_cprefix \
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"cmpl $0, %%gs:%P4\n\tje 0f\n\tlock\n0:\t"
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#define catomic_exchange_and_add(mem, value) \
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__arch_exchange_and_add_body (__arch_exchange_and_add_cprefix, __arch_c, \
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mem, value)
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#define __arch_add_body(lock, pfx, mem, value) \
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do { \
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if (__builtin_constant_p (value) && (value) == 1) \
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atomic_increment (mem); \
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else if (__builtin_constant_p (value) && (value) == -1) \
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atomic_decrement (mem); \
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else if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "addb %b1, %0" \
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__asm __volatile (lock "addb %b1, %0" \
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: "=m" (*mem) \
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: "ir" (value), "m" (*mem)); \
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: "ir" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "addw %w1, %0" \
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__asm __volatile (lock "addw %w1, %0" \
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: "=m" (*mem) \
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: "ir" (value), "m" (*mem)); \
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: "ir" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "addl %1, %0" \
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__asm __volatile (lock "addl %1, %0" \
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: "=m" (*mem) \
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: "ir" (value), "m" (*mem)); \
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: "ir" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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{ \
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__typeof (value) __addval = (value); \
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__typeof (*mem) __tmpval; \
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do \
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__tmpval = __oldval; \
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while ((__oldval = __arch_compare_and_exchange_val_64_acq \
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while ((__oldval = pfx##_compare_and_exchange_val_64_acq \
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(__memp, __oldval + __addval, __oldval)) == __tmpval); \
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} \
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} while (0)
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#define atomic_add(mem, value) \
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__arch_add_body (LOCK_PREFIX, __arch, mem, value)
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#define __arch_add_cprefix \
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"cmpl $0, %%gs:%P3\n\tje 0f\n\tlock\n0:\t"
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#define catomic_add(mem, value) \
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__arch_add_body (__arch_add_cprefix, __arch_c, mem, value)
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#define atomic_add_negative(mem, value) \
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({ unsigned char __result; \
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__result; })
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#define atomic_increment(mem) \
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#define __arch_increment_body(lock, pfx, mem) \
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do { \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "incb %b0" \
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__asm __volatile (lock "incb %b0" \
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: "=m" (*mem) \
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: "m" (*mem)); \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "incw %w0" \
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__asm __volatile (lock "incw %w0" \
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: "=m" (*mem) \
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: "m" (*mem)); \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "incl %0" \
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__asm __volatile (lock "incl %0" \
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: "=m" (*mem) \
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: "m" (*mem)); \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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{ \
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__typeof (mem) __memp = (mem); \
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__typeof (*mem) __tmpval; \
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do \
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__tmpval = __oldval; \
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while ((__oldval = __arch_compare_and_exchange_val_64_acq \
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while ((__oldval = pfx##_compare_and_exchange_val_64_acq \
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(__memp, __oldval + 1, __oldval)) == __tmpval); \
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} \
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} while (0)
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#define atomic_increment(mem) __arch_increment_body (LOCK_PREFIX, __arch, mem)
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#define __arch_increment_cprefix \
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"cmpl $0, %%gs:%P2\n\tje 0f\n\tlock\n0:\t"
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#define catomic_increment(mem) \
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__arch_increment_body (__arch_increment_cprefix, __arch_c, mem)
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#define atomic_increment_and_test(mem) \
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({ unsigned char __result; \
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__result; })
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#define atomic_decrement(mem) \
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#define __arch_decrement_body(lock, pfx, mem) \
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do { \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "decb %b0" \
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__asm __volatile (lock "decb %b0" \
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: "=m" (*mem) \
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: "m" (*mem)); \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "decw %w0" \
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__asm __volatile (lock "decw %w0" \
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: "=m" (*mem) \
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: "m" (*mem)); \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "decl %0" \
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__asm __volatile (lock "decl %0" \
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: "=m" (*mem) \
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: "m" (*mem)); \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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{ \
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__typeof (mem) __memp = (mem); \
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__typeof (*mem) __tmpval; \
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do \
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__tmpval = __oldval; \
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while ((__oldval = __arch_compare_and_exchange_val_64_acq \
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while ((__oldval = pfx##_compare_and_exchange_val_64_acq \
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(__memp, __oldval - 1, __oldval)) == __tmpval); \
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} \
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} while (0)
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#define atomic_decrement(mem) __arch_decrement_body (LOCK_PREFIX, __arch, mem)
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#define __arch_decrement_cprefix \
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"cmpl $0, %%gs:%P2\n\tje 0f\n\tlock\n0:\t"
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#define catomic_decrement(mem) \
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__arch_increment_body (__arch_decrement_cprefix, __arch_c, mem)
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#define atomic_decrement_and_test(mem) \
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({ unsigned char __result; \
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} while (0)
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#define atomic_or(mem, mask) \
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#define __arch_or_body(lock, mem, mask) \
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do { \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "orb %1, %b0" \
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__asm __volatile (lock "orb %1, %b0" \
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: "=m" (*mem) \
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: "ir" (mask), "m" (*mem)); \
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: "ir" (mask), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "orw %1, %w0" \
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__asm __volatile (lock "orw %1, %w0" \
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: "=m" (*mem) \
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: "ir" (mask), "m" (*mem)); \
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: "ir" (mask), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "orl %1, %0" \
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__asm __volatile (lock "orl %1, %0" \
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: "=m" (*mem) \
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: "ir" (mask), "m" (*mem)); \
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: "ir" (mask), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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abort (); \
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} while (0)
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#define atomic_or(mem, mask) __arch_or_body (LOCK_PREFIX, mem, mask)
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#define __arch_or_cprefix \
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"cmpl $0, %%gs:%P3\n\tje 0f\n\tlock\n0:\t"
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#define catomic_or(mem, mask) __arch_or_body (__arch_or_cprefix, mem, mask)
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