From bb4e6db2f55cf703265ac3b6ebb733bb3b4b7e7f Mon Sep 17 00:00:00 2001 From: Roland McGrath Date: Wed, 14 Mar 2012 10:53:13 -0700 Subject: [PATCH 1/7] BZ#13846: manual/llio.texi (Memory-mapped I/O): Fix wrong function name. --- ChangeLog | 5 +++++ manual/llio.texi | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/ChangeLog b/ChangeLog index 41355aeec7..c29aab0a0e 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2012-03-14 Roland McGrath + + [BZ #13846] + * manual/llio.texi (Memory-mapped I/O): Fix wrong function name. + 2012-03-14 Joseph Myers [BZ #13841] diff --git a/manual/llio.texi b/manual/llio.texi index d75fe71502..b33909fac8 100644 --- a/manual/llio.texi +++ b/manual/llio.texi @@ -1458,7 +1458,7 @@ This corresponds with BSD's @code{MADV_DONTNEED}. @end table -@code{msync} returns @math{0} for success and @math{-1} for +@code{madvise} returns @math{0} for success and @math{-1} for error. Errors include: @table @code From e29652e7b2847fb40512e1e70d8ebed970f2cea1 Mon Sep 17 00:00:00 2001 From: Roland McGrath Date: Wed, 14 Mar 2012 11:13:37 -0700 Subject: [PATCH 2/7] NEWS update for BZ#13846 --- NEWS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/NEWS b/NEWS index 2f38ad0307..854daee8f4 100644 --- a/NEWS +++ b/NEWS @@ -14,7 +14,8 @@ Version 2.16 10210, 10545, 10716, 11174, 11322, 11365, 11494, 12047, 13058, 13525, 13526, 13527, 13528, 13529, 13530, 13531, 13532, 13533, 13547, 13551, 13552, 13553, 13555, 13559, 13566, 13583, 13618, 13637, 13656, 13673, - 13695, 13704, 13706, 13726, 13738, 13786, 13792, 13806, 13840, 13841 + 13695, 13704, 13706, 13726, 13738, 13786, 13792, 13806, 13840, 13841, + 13846 * ISO C11 support: From bd951ccbe8597225d0f219425cf8e75d639185cd Mon Sep 17 00:00:00 2001 From: Joseph Myers Date: Wed, 14 Mar 2012 20:09:44 +0000 Subject: [PATCH 3/7] Install bits/syscall.h through install-headers. --- ChangeLog | 12 ++++++++++++ sysdeps/unix/sysv/linux/Makefile | 16 ++++------------ 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/ChangeLog b/ChangeLog index c29aab0a0e..83d5d2b289 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,15 @@ +2012-03-14 Joseph Myers + + * sysdeps/unix/sysv/linux/Makefile (sysdep_headers): Add + bits/syscall.h. + ($(objpfx)syscall-%.h): Rename rule to $(objpfx)bits/syscall%h. + ($(objpfx)syscall-%.d): Rename rule to $(objpfx)bits/syscall%d. + ($(inst_includedir)/bits/syscall.h): Remove rule. + ($(objpfx)bits/syscall.d): Include instead of + $(objpfx)syscall-list.d. + (generated): Change syscall-list.h and syscall-list.d to + bits/syscall.h and bits/syscall.d. + 2012-03-14 Roland McGrath [BZ #13846] diff --git a/sysdeps/unix/sysv/linux/Makefile b/sysdeps/unix/sysv/linux/Makefile index a97487fbc9..120d544289 100644 --- a/sysdeps/unix/sysv/linux/Makefile +++ b/sysdeps/unix/sysv/linux/Makefile @@ -34,9 +34,7 @@ sysdep_headers += sys/mount.h sys/acct.h sys/sysctl.h \ bits/a.out.h sys/inotify.h sys/signalfd.h sys/eventfd.h \ sys/timerfd.h sys/fanotify.h bits/eventfd.h bits/inotify.h \ bits/signalfd.h bits/timerfd.h bits/epoll.h \ - bits/socket_type.h - -install-others += $(inst_includedir)/bits/syscall.h + bits/socket_type.h bits/syscall.h tests += tst-clone @@ -62,7 +60,7 @@ ifndef syscall-list-includes syscall-list-includes := bits/wordsize.h endif -$(objpfx)syscall-%.h $(objpfx)syscall-%.d: ../sysdeps/unix/sysv/linux/sys/syscall.h +$(objpfx)bits/syscall%h $(objpfx)bits/syscall%d: ../sysdeps/unix/sysv/linux/sys/syscall.h $(make-target-directory) { \ echo '/* Generated at libc build time from kernel syscall list. */';\ @@ -97,17 +95,11 @@ endif rm -f $(foreach v,$(syscall-list-variants),$(@:.h=.d)-t$(v)) mv -f $(@:.h=.d)-t3 $(@:.h=.d) -$(inst_includedir)/bits/syscall.h: $(objpfx)syscall-list.h $(+force) - $(make-target-directory) - if test -r $@ && cmp -s $< $@; \ - then echo 'bits/syscall.h unchanged'; \ - else $(INSTALL_DATA) $< $@; fi - ifndef no_deps # Get the generated list of dependencies (probably /usr/include/asm/unistd.h). --include $(objpfx)syscall-list.d +-include $(objpfx)bits/syscall.d endif -generated += syscall-list.h syscall-list.d +generated += bits/syscall.h bits/syscall.d endif ifeq ($(subdir),time) From 7bd951ff59e0443ca1bdd5b0ea58f6f4f641ac73 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Wed, 14 Mar 2012 16:21:40 -0700 Subject: [PATCH 4/7] Small optimization to sparc 64-bit copysign. * sysdeps/sparc/sparc64/fpu/s_copysign.S (__copysign): Use fzeros/fnegs to load 0x80000000 into a float register instead of using the stack. * sysdeps/sparc/sparc64/fpu/s_copysignf.S (__copysignf): Likewise. --- ChangeLog | 6 ++++++ sysdeps/sparc/sparc64/fpu/s_copysign.S | 5 ++--- sysdeps/sparc/sparc64/fpu/s_copysignf.S | 5 ++--- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/ChangeLog b/ChangeLog index 83d5d2b289..4983816df3 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,9 @@ +2012-03-14 David S. Miller + + * sysdeps/sparc/sparc64/fpu/s_copysign.S (__copysign): Use fzeros/fnegs + to load 0x80000000 into a float register instead of using the stack. + * sysdeps/sparc/sparc64/fpu/s_copysignf.S (__copysignf): Likewise. + 2012-03-14 Joseph Myers * sysdeps/unix/sysv/linux/Makefile (sysdep_headers): Add diff --git a/sysdeps/sparc/sparc64/fpu/s_copysign.S b/sysdeps/sparc/sparc64/fpu/s_copysign.S index 571f57cbdc..f7f69fb8d9 100644 --- a/sysdeps/sparc/sparc64/fpu/s_copysign.S +++ b/sysdeps/sparc/sparc64/fpu/s_copysign.S @@ -20,9 +20,8 @@ #include ENTRY (__copysign) - sethi %hi(0x80000000), %g1 - st %g1, [%sp + STACK_BIAS + 128] - ld [%sp + STACK_BIAS + 128], %f7 + fzeros %f7 + fnegs %f7, %f7 fands %f2, %f7, %f9 fandnot2s %f0, %f7, %f0 retl diff --git a/sysdeps/sparc/sparc64/fpu/s_copysignf.S b/sysdeps/sparc/sparc64/fpu/s_copysignf.S index db6a384c60..85577a7170 100644 --- a/sysdeps/sparc/sparc64/fpu/s_copysignf.S +++ b/sysdeps/sparc/sparc64/fpu/s_copysignf.S @@ -20,9 +20,8 @@ #include ENTRY (__copysignf) - sethi %hi(0x80000000), %g1 - st %g1, [%sp + STACK_BIAS + 128] - ld [%sp + STACK_BIAS + 128], %f7 + fzeros %f7 + fnegs %f7, %f7 fands %f3, %f7, %f9 fandnot2s %f1, %f7, %f1 retl From eae47a361821b60ad4274feae1d6e3fa4572cd0a Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Wed, 14 Mar 2012 16:29:47 -0700 Subject: [PATCH 5/7] Add framework for using sparc VIS3 instructions, use it for copysign/signbit. * sysdeps/sparc/configure.in: New file. * sysdeps/sparc/configure: Generate. * configure.in (libc_cv_sparc_as_vis3): Substitute. * configure: Regenerate. * config.h.in (HAVE_AS_VIS3_SUPPORT): New. * config.make.in (have-as-vis3): New. * sysdeps/sparc/sparc32/sparcv9/Makefile (ASFLAGS-*): If VIS3 is available use -Av9d instead of -Av9a. * sysdeps/sparc/sparc64/Makefile: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/Makefile: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_signbit-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.S: New file. --- ChangeLog | 20 +++ config.h.in | 3 + config.make.in | 1 + configure | 2 + configure.in | 1 + sysdeps/sparc/configure | 124 ++++++++++++++++++ sysdeps/sparc/configure.in | 30 +++++ sysdeps/sparc/sparc32/sparcv9/Makefile | 9 ++ .../sparc32/sparcv9/fpu/multiarch/Makefile | 9 ++ .../sparcv9/fpu/multiarch/s_copysign-vis3.S | 30 +++++ .../sparcv9/fpu/multiarch/s_copysign.S | 46 +++++++ .../sparcv9/fpu/multiarch/s_copysignf-vis3.S | 29 ++++ .../sparcv9/fpu/multiarch/s_copysignf.S | 46 +++++++ sysdeps/sparc/sparc64/Makefile | 9 ++ sysdeps/sparc/sparc64/fpu/multiarch/Makefile | 9 ++ .../sparc64/fpu/multiarch/s_signbit-vis3.S | 25 ++++ .../sparc/sparc64/fpu/multiarch/s_signbit.S | 57 ++++++++ .../sparc64/fpu/multiarch/s_signbitf-vis3.S | 25 ++++ .../sparc/sparc64/fpu/multiarch/s_signbitf.S | 46 +++++++ 19 files changed, 521 insertions(+) create mode 100644 sysdeps/sparc/configure create mode 100644 sysdeps/sparc/configure.in create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/Makefile create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_signbit-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.S diff --git a/ChangeLog b/ChangeLog index 4983816df3..b36ecb9287 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,25 @@ 2012-03-14 David S. Miller + * sysdeps/sparc/configure.in: New file. + * sysdeps/sparc/configure: Generate. + * configure.in (libc_cv_sparc_as_vis3): Substitute. + * configure: Regenerate. + * config.h.in (HAVE_AS_VIS3_SUPPORT): New. + * config.make.in (have-as-vis3): New. + * sysdeps/sparc/sparc32/sparcv9/Makefile (ASFLAGS-*): If VIS3 is + available use -Av9d instead of -Av9a. + * sysdeps/sparc/sparc64/Makefile: Likewise. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/Makefile: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_signbit-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.S: New file. + * sysdeps/sparc/sparc64/fpu/s_copysign.S (__copysign): Use fzeros/fnegs to load 0x80000000 into a float register instead of using the stack. * sysdeps/sparc/sparc64/fpu/s_copysignf.S (__copysignf): Likewise. diff --git a/config.h.in b/config.h.in index 7e5f4d4635..3b938f8013 100644 --- a/config.h.in +++ b/config.h.in @@ -90,6 +90,9 @@ /* Defined on SPARC if GCC emits GOTDATA relocations. */ #undef HAVE_GCC_GOTDATA +/* Define on SPARC if AS supports VIS3 instructions. */ +#undef HAVE_AS_VIS3_SUPPORT + /* Define if the linker supports the -z combreloc option. */ #undef HAVE_Z_COMBRELOC diff --git a/config.make.in b/config.make.in index 46a14b4f29..2b9a939e9b 100644 --- a/config.make.in +++ b/config.make.in @@ -58,6 +58,7 @@ enable-check-abi = @enable_check_abi@ have-forced-unwind = @libc_cv_forced_unwind@ have-fpie = @libc_cv_fpie@ have-mfma4 = @libc_cv_cc_fma4@ +have-as-vis3 = @libc_cv_sparc_as_vis3@ gnu89-inline-CFLAGS = @gnu89_inline@ have-ssp = @libc_cv_ssp@ have-selinux = @have_selinux@ diff --git a/configure b/configure index f415389a34..94b15bbe8f 100755 --- a/configure +++ b/configure @@ -616,6 +616,7 @@ shared static ldd_rewrite_script use_ldconfig +libc_cv_sparc_as_vis3 libc_cv_as_i686 libc_cv_cc_fma4 libc_cv_cc_novzeroupper @@ -7645,6 +7646,7 @@ fi + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether -fPIC is default" >&5 diff --git a/configure.in b/configure.in index ee9e3d8eb4..119d5be944 100644 --- a/configure.in +++ b/configure.in @@ -2151,6 +2151,7 @@ AC_SUBST(libc_cv_cc_sse2avx) AC_SUBST(libc_cv_cc_novzeroupper) AC_SUBST(libc_cv_cc_fma4) AC_SUBST(libc_cv_as_i686) +AC_SUBST(libc_cv_sparc_as_vis3) AC_SUBST(use_ldconfig) AC_SUBST(ldd_rewrite_script) diff --git a/sysdeps/sparc/configure b/sysdeps/sparc/configure new file mode 100644 index 0000000000..9ce761b3b8 --- /dev/null +++ b/sysdeps/sparc/configure @@ -0,0 +1,124 @@ + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + + + as_lineno_1=$LINENO as_lineno_1a=$LINENO + as_lineno_2=$LINENO as_lineno_2a=$LINENO + eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" && + test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || { + # Blame Lee E. McMahon (1931-1989) for sed's syntax. :-) + sed -n ' + p + /[$]LINENO/= + ' <$as_myself | + sed ' + s/[$]LINENO.*/&-/ + t lineno + b + :lineno + N + :loop + s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/ + t loop + s/-\n.*// + ' >$as_me.lineno && + chmod +x "$as_me.lineno" || + { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } + + # Don't try to exec as it changes $[0], causing all sort of problems + # (the dirname of $[0] is not the place where we might find the + # original and so on. Autoconf is especially sensitive to this). + . "./$as_me.lineno" + # Exit status is that of the last command. + exit +} + +# This file is generated from configure.in by Autoconf. DO NOT EDIT! + # Local configure fragment for sysdeps/sparc. + +# Check for support of VIS3 et al. instructions in the assembler. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for sparc assembler VIS3 support" >&5 +$as_echo_n "checking for sparc assembler VIS3 support... " >&6; } +if ${libc_cv_sparc_as_vis3+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat > conftest.S <<\EOF + .text +foo: fmadds %f1, %f2, %f3, %f5 + fmaddd %f2, %f4, %f8, %f10 + fhadds %f2, %f3, %f5 + fhaddd %f4, %f8, %f10 + pdistn %f2, %f4, %g1 + movdtox %f10, %o0 + movstouw %f9, %o1 + movstosw %f7, %o2 + movxtod %o3, %f18 + movwtos %o4, %f15 + flcmps %fcc0, %f3, %f5 + flcmpd %fcc1, %f4, %f6 +EOF +if { ac_try='${CC-cc} -c $CFLAGS -Wa,-Av9d conftest.S' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + libc_cv_sparc_as_vis3=yes +else + libc_cv_sparc_as_vis3=no +fi +rm -f conftest* +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_sparc_as_vis3" >&5 +$as_echo "$libc_cv_sparc_as_vis3" >&6; } +if test $libc_cv_sparc_as_vis3 = yes; then + $as_echo "#define HAVE_AS_VIS3_SUPPORT 1" >>confdefs.h + +fi diff --git a/sysdeps/sparc/configure.in b/sysdeps/sparc/configure.in new file mode 100644 index 0000000000..b80d9cbf59 --- /dev/null +++ b/sysdeps/sparc/configure.in @@ -0,0 +1,30 @@ +GLIBC_PROVIDES dnl See aclocal.m4 in the top level source directory. +# Local configure fragment for sysdeps/sparc. + +# Check for support of VIS3 et al. instructions in the assembler. +AC_CACHE_CHECK(for sparc assembler VIS3 support, libc_cv_sparc_as_vis3, [dnl +cat > conftest.S <<\EOF + .text +foo: fmadds %f1, %f2, %f3, %f5 + fmaddd %f2, %f4, %f8, %f10 + fhadds %f2, %f3, %f5 + fhaddd %f4, %f8, %f10 + pdistn %f2, %f4, %g1 + movdtox %f10, %o0 + movstouw %f9, %o1 + movstosw %f7, %o2 + movxtod %o3, %f18 + movwtos %o4, %f15 + flcmps %fcc0, %f3, %f5 + flcmpd %fcc1, %f4, %f6 +EOF +dnl +if AC_TRY_COMMAND([${CC-cc} -c $CFLAGS -Wa,-Av9d conftest.S]); then + libc_cv_sparc_as_vis3=yes +else + libc_cv_sparc_as_vis3=no +fi +rm -f conftest*]) +if test $libc_cv_sparc_as_vis3 = yes; then + AC_DEFINE(HAVE_AS_VIS3_SUPPORT) +fi diff --git a/sysdeps/sparc/sparc32/sparcv9/Makefile b/sysdeps/sparc/sparc32/sparcv9/Makefile index 58f5759b3f..8a9330f7a6 100644 --- a/sysdeps/sparc/sparc32/sparcv9/Makefile +++ b/sysdeps/sparc/sparc32/sparcv9/Makefile @@ -5,9 +5,18 @@ sysdep_routines += hp-timing elide-routines.os += hp-timing endif +ifeq ($(have-as-vis3),yes) +ASFLAGS-.o += -Wa,-Av9d +ASFLAGS-.os += -Wa,-Av9d +ASFLAGS-.op += -Wa,-Av9d +ASFLAGS-.og += -Wa,-Av9d +ASFLAGS-.ob += -Wa,-Av9d +ASFLAGS-.oS += -Wa,-Av9d +else ASFLAGS-.o += -Wa,-Av9a ASFLAGS-.os += -Wa,-Av9a ASFLAGS-.op += -Wa,-Av9a ASFLAGS-.og += -Wa,-Av9a ASFLAGS-.ob += -Wa,-Av9a ASFLAGS-.oS += -Wa,-Av9a +endif diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile new file mode 100644 index 0000000000..33b03ac6aa --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile @@ -0,0 +1,9 @@ +ifeq ($(subdir),math) +ifeq ($(have-as-vis3),yes) +libm-sysdep_routines += m_copysignf-vis3 m_copysign-vis3 +sysdep_routines += s_copysignf-vis3 s_copysign-vis3 + +CFLAGS-s_copysignf-vis3.S = -Wa,-Av9d +CFLAGS-s_copysign-vis3.S = -Wa,-Av9d +endif +endif \ No newline at end of file diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign-vis3.S new file mode 100644 index 0000000000..db27bb7f52 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign-vis3.S @@ -0,0 +1,30 @@ +/* copysign function, sparc32 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__copysign_vis3) + sethi %hi(0x80000000), %g1 + and %o2, %g1, %o4 + andn %o0, %g1, %o0 + or %o0, %o4, %o0 + movwtos %o0, %f0 + retl + movwtos %o1, %f1 +END (__copysign_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.S new file mode 100644 index 0000000000..7179058f06 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__copysign) + .type __copysign, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__copysign_vis3), %o1 + xor %o1, %gdop_lox10(__copysign_vis3), %o1 +# else + set __copysign_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__copysign_generic), %o1 + xor %o1, %gdop_lox10(__copysign_generic), %o1 +# else + set __copysign_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__copysign) +weak_alias (__copysign, copysign) + +# undef weak_alias +# define weak_alias(a, b) + +#define __copysign __copysign_generic + +#include "../../../fpu/s_copysign.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf-vis3.S new file mode 100644 index 0000000000..7cdc540842 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf-vis3.S @@ -0,0 +1,29 @@ +/* float copysign function, sparc32 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__copysignf_vis3) + sethi %hi(0x80000000), %g1 + and %o1, %g1, %o4 + andn %o0, %g1, %o0 + or %o0, %o4, %o0 + retl + movwtos %o0, %f0 +END (__copysignf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.S new file mode 100644 index 0000000000..4d055f2df5 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__copysignf) + .type __copysignf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__copysignf_vis3), %o1 + xor %o1, %gdop_lox10(__copysignf_vis3), %o1 +# else + set __copysignf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__copysignf_generic), %o1 + xor %o1, %gdop_lox10(__copysignf_generic), %o1 +# else + set __copysignf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__copysignf) +weak_alias (__copysignf, copysignf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __copysignf __copysignf_generic + +#include "../../../fpu/s_copysignf.S" diff --git a/sysdeps/sparc/sparc64/Makefile b/sysdeps/sparc/sparc64/Makefile index fb8b011d53..2b7b83035a 100644 --- a/sysdeps/sparc/sparc64/Makefile +++ b/sysdeps/sparc/sparc64/Makefile @@ -6,3 +6,12 @@ endif ifeq ($(subdir),string) sysdep_routines += align-cpy endif + +ifeq ($(have-as-vis3),yes) +ASFLAGS-.o += -Wa,-Av9d +ASFLAGS-.os += -Wa,-Av9d +ASFLAGS-.op += -Wa,-Av9d +ASFLAGS-.og += -Wa,-Av9d +ASFLAGS-.ob += -Wa,-Av9d +ASFLAGS-.oS += -Wa,-Av9d +endif diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/Makefile b/sysdeps/sparc/sparc64/fpu/multiarch/Makefile new file mode 100644 index 0000000000..b03884de0d --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/Makefile @@ -0,0 +1,9 @@ +ifeq ($(subdir),math) +ifeq ($(have-as-vis3),yes) +libm-sysdep_routines += m_signbitf-vis3 m_signbit-vis3 +sysdep_routines += s_signbitf-vis3 s_signbit-vis3 + +CFLAGS-s_signbitf-vis3.S = -Wa,-Av9d +CFLAGS-s_signbit-vis3.S = -Wa,-Av9d +endif +endif \ No newline at end of file diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit-vis3.S new file mode 100644 index 0000000000..8d54e32ac4 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit-vis3.S @@ -0,0 +1,25 @@ +/* signbit(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__signbit_vis3) + movdtox %f0, %o0 + retl + srlx %o0, 63, %o0 +END (__signbit_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.S new file mode 100644 index 0000000000..a8e9728935 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.S @@ -0,0 +1,57 @@ +#include + + .text +ENTRY(__signbit) + .type __signbit, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__signbit_vis3), %o1 + xor %o1, %gdop_lox10(__signbit_vis3), %o1 +# else + set __signbit_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__signbit_generic), %o1 + xor %o1, %gdop_lox10(__signbit_generic), %o1 +# else + set __signbit_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__signbit) +weak_alias (__signbit, signbit) + +/* On 64-bit the double version will also always work for + long-double-precision since in both cases the word with the + sign bit in it is passed always in register %f0. */ +strong_alias (__signbit, __signbitl) +hidden_def (__signbitl) +weak_alias (__signbitl, signbitl) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __signbit __signbit_generic + +#include "../s_signbit.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf-vis3.S new file mode 100644 index 0000000000..004b0870d6 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf-vis3.S @@ -0,0 +1,25 @@ +/* signbitf(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__signbitf_vis3) + movstouw %f1, %o0 + retl + srl %o0, 31, %o0 +END (__signbitf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.S new file mode 100644 index 0000000000..721bc7fe4a --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__signbitf) + .type __signbitf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__signbitf_vis3), %o1 + xor %o1, %gdop_lox10(__signbitf_vis3), %o1 +# else + set __signbitf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__signbitf_generic), %o1 + xor %o1, %gdop_lox10(__signbitf_generic), %o1 +# else + set __signbitf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__signbitf) +weak_alias (__signbitf, signbitf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __signbitf __signbitf_generic + +#include "../s_signbitf.S" From 5a1c1e32435486a52561d2801dece286b1c32984 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Wed, 14 Mar 2012 17:25:35 -0700 Subject: [PATCH 6/7] Update sparc ULPs for newly added csqrt tests. * sysdeps/sparc/fpu/libm-test-ulps: Update. --- ChangeLog | 2 ++ sysdeps/sparc/fpu/libm-test-ulps | 34 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/ChangeLog b/ChangeLog index b36ecb9287..f79bcbf353 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,7 @@ 2012-03-14 David S. Miller + * sysdeps/sparc/fpu/libm-test-ulps: Update. + * sysdeps/sparc/configure.in: New file. * sysdeps/sparc/configure: Generate. * configure.in (libc_cv_sparc_as_vis3): Substitute. diff --git a/sysdeps/sparc/fpu/libm-test-ulps b/sysdeps/sparc/fpu/libm-test-ulps index 29e732c282..fab55801f9 100644 --- a/sysdeps/sparc/fpu/libm-test-ulps +++ b/sysdeps/sparc/fpu/libm-test-ulps @@ -923,6 +923,34 @@ ldouble: 1 Test "Imaginary part of: csqrt (0.75 + 1.25 i) == 1.05065169626078392338656675760808326 + 0.594868882070379067881984030639932657 i": ildouble: 1 ldouble: 1 +Test "Imaginary part of: csqrt (0x1.fffffep+127 + 1.0 i) == 1.844674352395372953599975585936590505260e+19 + 2.710505511993121390769065968615872097053e-20 i": +float: 1 +ifloat: 1 +Test "Real part of: csqrt (0x1.fffffffffffffp+1023 + 0x1.fffffffffffffp+1023 i) == 1.473094556905565378990473658199034571917e+154 + 6.101757441282702188537080005372547713595e+153 i": +double: 1 +idouble: 1 +Test "Imaginary part of: csqrt (0x1.fffffffffffffp+1023 + 0x1.fffffffffffffp+1023 i) == 1.473094556905565378990473658199034571917e+154 + 6.101757441282702188537080005372547713595e+153 i": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: csqrt (0x1.fffffffffffffp+1023 + 0x1p+1023 i) == 1.379778091031440685006200821918878702861e+154 + 3.257214233483129514781233066898042490248e+153 i": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 +Test "Real part of: csqrt (0x1.fp+16383 + 0x1.fp+16383 i) == 1.179514222452201722651836720466795901016e+2466 + 4.885707879516577666702435054303191575148e+2465 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: csqrt (0x1.fp+16383 + 0x1.fp+16383 i) == 1.179514222452201722651836720466795901016e+2466 + 4.885707879516577666702435054303191575148e+2465 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: csqrt (0x1.fp+16383 + 0x1p+16383 i) == 1.106698967236475180613254276996359485630e+2466 + 2.687568007603946993388538156299100955642e+2465 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: csqrt (0x1p-16440 + 0x1p-16441 i) == 3.514690655930285351254618340783294558136e-2475 + 8.297059146828716918029689466551384219370e-2476 i": +ildouble: 1 +ldouble: 1 # ctan Test "Real part of: ctan (-2 - 3 i) == 0.376402564150424829275122113032269084e-2 - 1.00323862735360980144635859782192726 i": @@ -2079,12 +2107,18 @@ idouble: 1 ifloat: 1 Function: Real part of "csqrt": +double: 1 float: 1 +idouble: 1 ifloat: 1 ildouble: 1 ldouble: 1 Function: Imaginary part of "csqrt": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 ildouble: 1 ldouble: 1 From 559398ab746fd7dbbe09e847813a1b917b9ded14 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Thu, 15 Mar 2012 00:11:17 -0700 Subject: [PATCH 7/7] Add more sparc VIS3 optimized math routines. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/Makefile: Add new VIS3 routines. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile: Add new VIS3 routines. * sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies: New file. --- ChangeLog | 58 ++++++++++++++ .../sparc32/sparcv9/fpu/multiarch/Makefile | 10 +-- .../sparcv9/fpu/multiarch/s_ceil-vis3.S | 78 ++++++++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_ceil.S | 46 +++++++++++ .../sparcv9/fpu/multiarch/s_ceilf-vis3.S | 74 +++++++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_ceilf.S | 46 +++++++++++ .../sparcv9/fpu/multiarch/s_fabs-vis3.S | 26 ++++++ .../sparc32/sparcv9/fpu/multiarch/s_fabs.S | 46 +++++++++++ .../sparcv9/fpu/multiarch/s_fabsf-vis3.S | 26 ++++++ .../sparc32/sparcv9/fpu/multiarch/s_fabsf.S | 46 +++++++++++ .../sparcv9/fpu/multiarch/s_floor-vis3.S | 79 +++++++++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_floor.S | 46 +++++++++++ .../sparcv9/fpu/multiarch/s_floorf-vis3.S | 74 +++++++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_floorf.S | 46 +++++++++++ .../sparcv9/fpu/multiarch/s_llrint-vis3.S | 58 ++++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_llrint.S | 51 ++++++++++++ .../sparcv9/fpu/multiarch/s_llrintf-vis3.S | 54 +++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_llrintf.S | 51 ++++++++++++ .../sparcv9/fpu/multiarch/s_rint-vis3.S | 55 +++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_rint.S | 46 +++++++++++ .../sparcv9/fpu/multiarch/s_rintf-vis3.S | 51 ++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_rintf.S | 46 +++++++++++ .../sparcv9/fpu/multiarch/w_sqrt-vis3.S | 49 ++++++++++++ .../sparc32/sparcv9/fpu/multiarch/w_sqrt.S | 46 +++++++++++ .../sparcv9/fpu/multiarch/w_sqrtf-vis3.S | 47 +++++++++++ .../sparc32/sparcv9/fpu/multiarch/w_sqrtf.S | 46 +++++++++++ .../fpu/unix/sysv/linux/multiarch/Implies | 4 + sysdeps/sparc/sparc64/fpu/multiarch/Makefile | 16 ++-- .../sparc/sparc64/fpu/multiarch/s_ceil-vis3.S | 75 ++++++++++++++++++ sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S | 46 +++++++++++ .../sparc64/fpu/multiarch/s_ceilf-vis3.S | 73 +++++++++++++++++ sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S | 46 +++++++++++ .../sparc64/fpu/multiarch/s_finite-vis3.S | 28 +++++++ .../sparc/sparc64/fpu/multiarch/s_finite.S | 49 ++++++++++++ .../sparc64/fpu/multiarch/s_finitef-vis3.S | 28 +++++++ .../sparc/sparc64/fpu/multiarch/s_finitef.S | 49 ++++++++++++ .../sparc64/fpu/multiarch/s_floor-vis3.S | 75 ++++++++++++++++++ sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S | 46 +++++++++++ .../sparc64/fpu/multiarch/s_floorf-vis3.S | 73 +++++++++++++++++ .../sparc/sparc64/fpu/multiarch/s_floorf.S | 46 +++++++++++ .../sparc64/fpu/multiarch/s_isinf-vis3.S | 31 ++++++++ sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S | 49 ++++++++++++ .../sparc64/fpu/multiarch/s_isinff-vis3.S | 30 +++++++ .../sparc/sparc64/fpu/multiarch/s_isinff.S | 49 ++++++++++++ .../sparc64/fpu/multiarch/s_isnan-vis3.S | 30 +++++++ sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S | 49 ++++++++++++ .../sparc64/fpu/multiarch/s_isnanf-vis3.S | 29 +++++++ .../sparc/sparc64/fpu/multiarch/s_isnanf.S | 49 ++++++++++++ .../sparc64/fpu/multiarch/s_lrint-vis3.S | 52 ++++++++++++ sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S | 51 ++++++++++++ .../sparc64/fpu/multiarch/s_lrintf-vis3.S | 51 ++++++++++++ .../sparc/sparc64/fpu/multiarch/s_lrintf.S | 51 ++++++++++++ .../sparc/sparc64/fpu/multiarch/s_rint-vis3.S | 50 ++++++++++++ sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S | 46 +++++++++++ .../sparc64/fpu/multiarch/s_rintf-vis3.S | 49 ++++++++++++ sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S | 46 +++++++++++ 56 files changed, 2656 insertions(+), 11 deletions(-) create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S create mode 100644 sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S diff --git a/ChangeLog b/ChangeLog index f79bcbf353..48823daae1 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,63 @@ 2012-03-14 David S. Miller + * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/Makefile: Add new VIS3 routines. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile: Add new VIS3 routines. + + * sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies: + New file. + * sysdeps/sparc/fpu/libm-test-ulps: Update. * sysdeps/sparc/configure.in: New file. diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile index 33b03ac6aa..3a7a389380 100644 --- a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile @@ -1,9 +1,9 @@ ifeq ($(subdir),math) ifeq ($(have-as-vis3),yes) -libm-sysdep_routines += m_copysignf-vis3 m_copysign-vis3 +libm-sysdep_routines += m_copysignf-vis3 m_copysign-vis3 s_ceilf-vis3 \ + s_ceil-vis3 s_fabs-vis3 s_fabsf-vis3 s_floor-vis3 \ + s_floorf-vis3 s_llrintf-vis3 s_llrint-vis3 \ + s_rintf-vis3 s_rint-vis3 w_sqrt-vis3 w_sqrtf-vis3 sysdep_routines += s_copysignf-vis3 s_copysign-vis3 - -CFLAGS-s_copysignf-vis3.S = -Wa,-Av9d -CFLAGS-s_copysign-vis3.S = -Wa,-Av9d endif -endif \ No newline at end of file +endif diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S new file mode 100644 index 0000000000..be41219cef --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S @@ -0,0 +1,78 @@ +/* ceil function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ +#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceil_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + sethi %hi(ONE_DOT_ZERO), %o3 + or %o0, %o1, %o0 + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fzero ZERO + sllx %o3, 32, %o3 + + fnegd ZERO, SIGN_BIT + + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f18 + fsubd %f18, %f16, %f18 + fcmpd %fcc2, %f18, %f0 + movxtod %o3, %f20 + + fmovduge %fcc2, ZERO, %f20 + faddd %f18, %f20, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__ceil_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S new file mode 100644 index 0000000000..f91fda61b9 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__ceil) + .type __ceil, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__ceil_vis3), %o1 + xor %o1, %gdop_lox10(__ceil_vis3), %o1 +# else + set __ceil_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__ceil_generic), %o1 + xor %o1, %gdop_lox10(__ceil_generic), %o1 +# else + set __ceil_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__ceil) +weak_alias (__ceil, ceil) + +# undef weak_alias +# define weak_alias(a, b) + +#define __ceil __ceil_generic + +#include "../s_ceil.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S new file mode 100644 index 0000000000..c35a85f24f --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S @@ -0,0 +1,74 @@ +/* Float ceil function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ +#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceilf_vis3) + movwtos %o0, %f0 + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f0, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f0, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f0, %f16, %f1 + fsubs %f1, %f16, %f1 + fcmps %fcc2, %f1, %f0 + movwtos %o3, %f9 + + fmovsuge %fcc2, ZERO, %f9 + fadds %f1, %f9, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__ceilf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S new file mode 100644 index 0000000000..048b6195d8 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__ceilf) + .type __ceilf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__ceilf_vis3), %o1 + xor %o1, %gdop_lox10(__ceilf_vis3), %o1 +# else + set __ceilf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__ceilf_generic), %o1 + xor %o1, %gdop_lox10(__ceilf_generic), %o1 +# else + set __ceilf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__ceilf) +weak_alias (__ceilf, ceilf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __ceilf __ceilf_generic + +#include "../s_ceilf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S new file mode 100644 index 0000000000..733ec90e42 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S @@ -0,0 +1,26 @@ +/* Float absolute value, sparc32+v9 vis3 version. + Copyright (C) 2011 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__fabs_vis3) + movwtos %o0, %f0 + movwtos %o1, %f1 + retl + fabsd %f0, %f0 +END (__fabs_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S new file mode 100644 index 0000000000..ed70e4be2c --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__fabs) + .type __fabs, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__fabs_vis3), %o1 + xor %o1, %gdop_lox10(__fabs_vis3), %o1 +# else + set __fabs_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__fabs_generic), %o1 + xor %o1, %gdop_lox10(__fabs_generic), %o1 +# else + set __fabs_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__fabs) +weak_alias (__fabs, fabs) + +# undef weak_alias +# define weak_alias(a, b) + +#define __fabs __fabs_generic + +#include "../s_fabs.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S new file mode 100644 index 0000000000..82b577580e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S @@ -0,0 +1,26 @@ +/* Float absolute value, sparc32 vis3 version. + Copyright (C) 2006 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek , 2006. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__fabsf_vis3) + movwtos %o0, %f0 + retl + fabss %f0, %f0 +END (__fabsf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S new file mode 100644 index 0000000000..4b7351fc2e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__fabsf) + .type __fabsf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__fabsf_vis3), %o1 + xor %o1, %gdop_lox10(__fabsf_vis3), %o1 +# else + set __fabsf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__fabsf_generic), %o1 + xor %o1, %gdop_lox10(__fabsf_generic), %o1 +# else + set __fabsf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__fabsf) +weak_alias (__fabsf, fabsf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __fabsf __fabsf_generic + +#include "../../../fpu/s_fabsf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S new file mode 100644 index 0000000000..d7e5d24c17 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S @@ -0,0 +1,79 @@ +/* floor function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ +#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floor_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + sethi %hi(ONE_DOT_ZERO), %o3 + or %o0, %o1, %o0 + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fzero ZERO + sllx %o3, 32, %o3 + + fnegd ZERO, SIGN_BIT + + stx %o2, [%sp + 72] + fabsd %f0, %f14 + + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f18 + fsubd %f18, %f16, %f18 + fcmpd %fcc2, %f18, %f0 + movxtod %o3, %f20 + + fmovdule %fcc2, ZERO, %f20 + fsubd %f18, %f20, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__floor_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S new file mode 100644 index 0000000000..1cdc53fb84 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__floor) + .type __floor, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__floor_vis3), %o1 + xor %o1, %gdop_lox10(__floor_vis3), %o1 +# else + set __floor_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__floor_generic), %o1 + xor %o1, %gdop_lox10(__floor_generic), %o1 +# else + set __floor_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__floor) +weak_alias (__floor, floor) + +# undef weak_alias +# define weak_alias(a, b) + +#define __floor __floor_generic + +#include "../s_floor.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S new file mode 100644 index 0000000000..24c8764fa6 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S @@ -0,0 +1,74 @@ +/* Float floor function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ +#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floorf_vis3) + movwtos %o0, %f0 + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f0, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f0, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f0, %f16, %f1 + fsubs %f1, %f16, %f1 + fcmps %fcc2, %f1, %f0 + movwtos %o3, %f9 + + fmovsule %fcc2, ZERO, %f9 + fsubs %f1, %f9, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__floorf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S new file mode 100644 index 0000000000..0dcd0e1431 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__floorf) + .type __floorf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__floorf_vis3), %o1 + xor %o1, %gdop_lox10(__floorf_vis3), %o1 +# else + set __floorf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__floorf_generic), %o1 + xor %o1, %gdop_lox10(__floorf_generic), %o1 +# else + set __floorf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__floorf) +weak_alias (__floorf, floorf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __floorf __floorf_generic + +#include "../s_floorf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S new file mode 100644 index 0000000000..8a90722b54 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S @@ -0,0 +1,58 @@ +/* llrint(), sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__llrint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + + or %o0, %o1, %o0 + fzero ZERO + + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + fdtox %f0, %f4 + movstouw %f4, %o0 + retl + movstouw %f5, %o1 +END (__llrint_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S new file mode 100644 index 0000000000..3a9294d3a8 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S @@ -0,0 +1,51 @@ +#include + + .text +ENTRY(__llrint) + .type __llrint, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__llrint_vis3), %o1 + xor %o1, %gdop_lox10(__llrint_vis3), %o1 +# else + set __llrint_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__llrint_generic), %o1 + xor %o1, %gdop_lox10(__llrint_generic), %o1 +# else + set __llrint_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__llrint) +weak_alias (__llrint, llrint) + +strong_alias (__llrint, __lllrint) +weak_alias (__lllrint, lllrint) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __llrint __llrint_generic + +#include "../s_llrint.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S new file mode 100644 index 0000000000..8590af2bb4 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S @@ -0,0 +1,54 @@ +/* llrintf(), sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__llrintf_vis3) + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + fstox %f0, %f4 + movstouw %f4, %o0 + retl + movstouw %f5, %o1 +END (__llrintf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S new file mode 100644 index 0000000000..f2236f0eec --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S @@ -0,0 +1,51 @@ +#include + + .text +ENTRY(__llrintf) + .type __llrintf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__llrintf_vis3), %o1 + xor %o1, %gdop_lox10(__llrintf_vis3), %o1 +# else + set __llrintf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__llrintf_generic), %o1 + xor %o1, %gdop_lox10(__llrintf_generic), %o1 +# else + set __llrintf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__llrintf) +weak_alias (__llrintf, llrintf) + +strong_alias (__llrintf, __lllrintf) +weak_alias (__lllrintf, lllrintf) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __llrintf __llrintf_generic + +#include "../s_llrintf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S new file mode 100644 index 0000000000..6c4a3e00dd --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S @@ -0,0 +1,55 @@ +/* Round float to int floating-point values, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + + or %o0, %o1, %o0 + fzero ZERO + + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__rint_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S new file mode 100644 index 0000000000..3872ae299e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__rint) + .type __rint, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__rint_vis3), %o1 + xor %o1, %gdop_lox10(__rint_vis3), %o1 +# else + set __rint_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__rint_generic), %o1 + xor %o1, %gdop_lox10(__rint_generic), %o1 +# else + set __rint_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__rint) +weak_alias (__rint, rint) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rint __rint_generic + +#include "../s_rint.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S new file mode 100644 index 0000000000..ec0bb37b13 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S @@ -0,0 +1,51 @@ +/* Round float to int floating-point values, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rintf_vis3) + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__rintf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S new file mode 100644 index 0000000000..9918929220 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__rintf) + .type __rintf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__rintf_vis3), %o1 + xor %o1, %gdop_lox10(__rintf_vis3), %o1 +# else + set __rintf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__rintf_generic), %o1 + xor %o1, %gdop_lox10(__rintf_generic), %o1 +# else + set __rintf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__rintf) +weak_alias (__rintf, rintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rintf __rintf_generic + +#include "../s_rintf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S new file mode 100644 index 0000000000..3880da0d8e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S @@ -0,0 +1,49 @@ +/* sqrt function. sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__sqrt_vis3) + movwtos %o0, %f0 + fzero %f8 + movwtos %o1, %f1 + fcmpd %f0, %f8 + fbl 1f + nop +8: retl + fsqrtd %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o2 + mov %o1, %o3 + mov 26, %o4 + mov %o7, %g1 + call __kernel_standard + mov %g1, %o7 +END (__sqrt_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S new file mode 100644 index 0000000000..80b15767ce --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__sqrt) + .type __sqrt, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__sqrt_vis3), %o1 + xor %o1, %gdop_lox10(__sqrt_vis3), %o1 +# else + set __sqrt_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__sqrt_generic), %o1 + xor %o1, %gdop_lox10(__sqrt_generic), %o1 +# else + set __sqrt_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__sqrt) +weak_alias (__sqrt, sqrt) + +# undef weak_alias +# define weak_alias(a, b) + +#define __sqrt __sqrt_generic + +#include "../w_sqrt.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S new file mode 100644 index 0000000000..2d4270f9cd --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S @@ -0,0 +1,47 @@ +/* sqrtf function. sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__sqrtf_vis3) + movwtos %o0, %f0 + fzeros %f8 + fcmps %f0, %f8 + fbl 1f + nop +8: retl + fsqrts %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o1 + mov 126, %o2 + mov %o7, %g1 + call __kernel_standard_f + mov %g1, %o7 +END (__sqrtf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S new file mode 100644 index 0000000000..a700a4e876 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__sqrtf) + .type __sqrtf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__sqrtf_vis3), %o1 + xor %o1, %gdop_lox10(__sqrtf_vis3), %o1 +# else + set __sqrtf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__sqrtf_generic), %o1 + xor %o1, %gdop_lox10(__sqrtf_generic), %o1 +# else + set __sqrtf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__sqrtf) +weak_alias (__sqrtf, sqrtf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __sqrtf __sqrtf_generic + +#include "../w_sqrtf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies b/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies new file mode 100644 index 0000000000..a380d8a739 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies @@ -0,0 +1,4 @@ +# We must list this here to move it ahead of the ldbl-opt code. +sparc/sparc32/sparcv9/fpu/multiarch +sparc/sparc32/sparcv9/fpu +sparc/sparc32/fpu diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/Makefile b/sysdeps/sparc/sparc64/fpu/multiarch/Makefile index b03884de0d..564ed26c3d 100644 --- a/sysdeps/sparc/sparc64/fpu/multiarch/Makefile +++ b/sysdeps/sparc/sparc64/fpu/multiarch/Makefile @@ -1,9 +1,13 @@ ifeq ($(subdir),math) ifeq ($(have-as-vis3),yes) -libm-sysdep_routines += m_signbitf-vis3 m_signbit-vis3 -sysdep_routines += s_signbitf-vis3 s_signbit-vis3 - -CFLAGS-s_signbitf-vis3.S = -Wa,-Av9d -CFLAGS-s_signbit-vis3.S = -Wa,-Av9d +libm-sysdep_routines += m_signbitf-vis3 m_signbit-vis3 s_ceilf-vis3 \ + s_ceil-vis3 m_finitef-vis3 m_finite-vis3 \ + s_floorf-vis3 s_floor-vis3 m_isinff-vis3 \ + m_isinf-vis3 m_isnanf-vis3 m_isnan-vis3 \ + s_lrintf-vis3 s_lrint-vis3 s_rintf-vis3 \ + s_rint-vis3 +sysdep_routines += s_signbitf-vis3 s_signbit-vis3 s_finitef-vis3 \ + s_finite-vis3 s_isinff-vis3 s_isinf-vis3 \ + s_isnanf-vis3 s_isnan-vis3 +endif endif -endif \ No newline at end of file diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S new file mode 100644 index 0000000000..ebf9d80b89 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S @@ -0,0 +1,75 @@ +/* ceil function, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ +#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceil_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzero ZERO + + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + sllx %o3, 32, %o3 + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f18 + fsubd %f18, %f16, %f18 + fcmpd %fcc2, %f18, %f0 + movxtod %o3, %f20 + + fmovduge %fcc2, ZERO, %f20 + faddd %f18, %f20, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__ceil_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S new file mode 100644 index 0000000000..f91fda61b9 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__ceil) + .type __ceil, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__ceil_vis3), %o1 + xor %o1, %gdop_lox10(__ceil_vis3), %o1 +# else + set __ceil_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__ceil_generic), %o1 + xor %o1, %gdop_lox10(__ceil_generic), %o1 +# else + set __ceil_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__ceil) +weak_alias (__ceil, ceil) + +# undef weak_alias +# define weak_alias(a, b) + +#define __ceil __ceil_generic + +#include "../s_ceil.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S new file mode 100644 index 0000000000..09d2d3dbe3 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S @@ -0,0 +1,73 @@ +/* Float ceil function, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ +#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceilf_vis3) + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f5 + fcmps %fcc2, %f5, %f1 + movwtos %o3, %f9 + + fmovsuge %fcc2, ZERO, %f9 + fadds %f5, %f9, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__ceilf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S new file mode 100644 index 0000000000..048b6195d8 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__ceilf) + .type __ceilf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__ceilf_vis3), %o1 + xor %o1, %gdop_lox10(__ceilf_vis3), %o1 +# else + set __ceilf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__ceilf_generic), %o1 + xor %o1, %gdop_lox10(__ceilf_generic), %o1 +# else + set __ceilf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__ceilf) +weak_alias (__ceilf, ceilf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __ceilf __ceilf_generic + +#include "../s_ceilf.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S new file mode 100644 index 0000000000..6929b56ba2 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S @@ -0,0 +1,28 @@ +/* finite(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__finite_vis3) + fabsd %f0, %f0 + movstouw %f0, %o0 + sethi %hi(0x7ff00000), %o2 + sub %o0, %o2, %o0 + retl + srl %o0, 31, %o0 +END (__finite_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S new file mode 100644 index 0000000000..f4bfdcef96 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S @@ -0,0 +1,49 @@ +#include + + .text +ENTRY(__finite) + .type __finite, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__finite_vis3), %o1 + xor %o1, %gdop_lox10(__finite_vis3), %o1 +# else + set __finite_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__finite_generic), %o1 + xor %o1, %gdop_lox10(__finite_generic), %o1 +# else + set __finite_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__finite) +hidden_def (__finite) +weak_alias (__finite, finite) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __finite __finite_generic + +#include "../s_finite.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S new file mode 100644 index 0000000000..93420ff6a7 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S @@ -0,0 +1,28 @@ +/* finitef(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__finitef_vis3) + fabss %f1, %f0 + movstouw %f0, %o0 + sethi %hi(0x7f800000), %o2 + sub %o0, %o2, %o0 + retl + srl %o0, 31, %o0 +END (__finitef_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S new file mode 100644 index 0000000000..65ca7fd1c6 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S @@ -0,0 +1,49 @@ +#include + + .text +ENTRY(__finitef) + .type __finitef, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__finitef_vis3), %o1 + xor %o1, %gdop_lox10(__finitef_vis3), %o1 +# else + set __finitef_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__finitef_generic), %o1 + xor %o1, %gdop_lox10(__finitef_generic), %o1 +# else + set __finitef_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__finitef) +hidden_def (__finitef) +weak_alias (__finitef, finitef) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __finitef __finitef_generic + +#include "../s_finitef.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S new file mode 100644 index 0000000000..86ed1ae92b --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S @@ -0,0 +1,75 @@ +/* floor function, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ +#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floor_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzero ZERO + + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + sllx %o3, 32, %o3 + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f18 + fsubd %f18, %f16, %f18 + fcmpd %fcc2, %f18, %f0 + movxtod %o3, %f20 + + fmovdule %fcc2, ZERO, %f20 + fsubd %f18, %f20, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__floor_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S new file mode 100644 index 0000000000..1cdc53fb84 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__floor) + .type __floor, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__floor_vis3), %o1 + xor %o1, %gdop_lox10(__floor_vis3), %o1 +# else + set __floor_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__floor_generic), %o1 + xor %o1, %gdop_lox10(__floor_generic), %o1 +# else + set __floor_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__floor) +weak_alias (__floor, floor) + +# undef weak_alias +# define weak_alias(a, b) + +#define __floor __floor_generic + +#include "../s_floor.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S new file mode 100644 index 0000000000..b663b64753 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S @@ -0,0 +1,73 @@ +/* Float floor function, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ +#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floorf_vis3) + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f5 + fcmps %fcc2, %f5, %f1 + movwtos %o3, %f9 + + fmovsule %fcc2, ZERO, %f9 + fsubs %f5, %f9, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__floorf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S new file mode 100644 index 0000000000..0dcd0e1431 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__floorf) + .type __floorf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__floorf_vis3), %o1 + xor %o1, %gdop_lox10(__floorf_vis3), %o1 +# else + set __floorf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__floorf_generic), %o1 + xor %o1, %gdop_lox10(__floorf_generic), %o1 +# else + set __floorf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__floorf) +weak_alias (__floorf, floorf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __floorf __floorf_generic + +#include "../s_floorf.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S new file mode 100644 index 0000000000..7f7cd5ee69 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S @@ -0,0 +1,31 @@ +/* isinf(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__isinf_vis3) + movdtox %f0, %g1 + sethi %hi(0x7ff00000), %o2 + sllx %o2, 32, %o2 + sllx %g1, 1, %o4 + srlx %o4, 1, %o5 + srax %g1, 62, %o0 + xor %o5, %o2, %o3 + retl + movrne %o3, %g0, %o0 +END (__isinf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S new file mode 100644 index 0000000000..8b47267f6b --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S @@ -0,0 +1,49 @@ +#include + + .text +ENTRY(__isinf) + .type __isinf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__isinf_vis3), %o1 + xor %o1, %gdop_lox10(__isinf_vis3), %o1 +# else + set __isinf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__isinf_generic), %o1 + xor %o1, %gdop_lox10(__isinf_generic), %o1 +# else + set __isinf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__isinf) +hidden_def (__isinf) +weak_alias (__isinf, isinf) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isinf __isinf_generic + +#include "../s_isinf.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S new file mode 100644 index 0000000000..7d59d5db3f --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S @@ -0,0 +1,30 @@ +/* isinff(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__isinff_vis3) + movstouw %f1, %g1 + sethi %hi(0x7f800000), %o2 + sll %g1, 1, %o4 + srl %o4, 1, %o5 + sra %g1, 30, %o0 + xor %o5, %o2, %o3 + retl + movrne %o3, %g0, %o0 +END (__isinff_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S new file mode 100644 index 0000000000..9a42a01d40 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S @@ -0,0 +1,49 @@ +#include + + .text +ENTRY(__isinff) + .type __isinff, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__isinff_vis3), %o1 + xor %o1, %gdop_lox10(__isinff_vis3), %o1 +# else + set __isinff_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__isinff_generic), %o1 + xor %o1, %gdop_lox10(__isinff_generic), %o1 +# else + set __isinff_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__isinff) +hidden_def (__isinff) +weak_alias (__isinff, isinff) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isinff __isinff_generic + +#include "../s_isinff.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S new file mode 100644 index 0000000000..b3b1014443 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S @@ -0,0 +1,30 @@ +/* isnan(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__isnan_vis3) + movdtox %f0, %o0 + sethi %hi(0x7ff00000), %g1 + sllx %g1, 32, %g1 + sllx %o0, 1, %o0 + srlx %o0, 1, %o0 + sub %g1, %o0, %o0 + retl + srlx %o0, 63, %o0 +END (__isnan_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S new file mode 100644 index 0000000000..d75077cfec --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S @@ -0,0 +1,49 @@ +#include + + .text +ENTRY(__isnan) + .type __isnan, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__isnan_vis3), %o1 + xor %o1, %gdop_lox10(__isnan_vis3), %o1 +# else + set __isnan_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__isnan_generic), %o1 + xor %o1, %gdop_lox10(__isnan_generic), %o1 +# else + set __isnan_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__isnan) +hidden_def (__isnan) +weak_alias (__isnan, isnan) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isnan __isnan_generic + +#include "../s_isnan.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S new file mode 100644 index 0000000000..cd60d3e563 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S @@ -0,0 +1,29 @@ +/* isnanf(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__isnanf_vis3) + movstouw %f1, %o0 + sethi %hi(0x7f800000), %g1 + sll %o0, 1, %o0 + srl %o0, 1, %o0 + sub %g1, %o0, %o0 + retl + srl %o0, 31, %o0 +END (__isnanf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S new file mode 100644 index 0000000000..6d11dd4b4e --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S @@ -0,0 +1,49 @@ +#include + + .text +ENTRY(__isnanf) + .type __isnanf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__isnanf_vis3), %o1 + xor %o1, %gdop_lox10(__isnanf_vis3), %o1 +# else + set __isnanf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__isnanf_generic), %o1 + xor %o1, %gdop_lox10(__isnanf_generic), %o1 +# else + set __isnanf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__isnanf) +hidden_def (__isnanf) +weak_alias (__isnanf, isnanf) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isnanf __isnanf_generic + +#include "../s_isnanf.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S new file mode 100644 index 0000000000..4633017fc5 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S @@ -0,0 +1,52 @@ +/* lrint(), sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__lrint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + fzero ZERO + + fnegd ZERO, SIGN_BIT + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + fdtox %f0, %f4 + retl + movdtox %f4, %o0 +END (__lrint_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S new file mode 100644 index 0000000000..e63e83343b --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S @@ -0,0 +1,51 @@ +#include + + .text +ENTRY(__lrint) + .type __lrint, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__lrint_vis3), %o1 + xor %o1, %gdop_lox10(__lrint_vis3), %o1 +# else + set __lrint_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__lrint_generic), %o1 + xor %o1, %gdop_lox10(__lrint_generic), %o1 +# else + set __lrint_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__lrint) +weak_alias (__lrint, lrint) + +strong_alias (__lrint, __llrint) +weak_alias (__llrint, llrint) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __lrint __lrint_generic + +#include "../s_lrint.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S new file mode 100644 index 0000000000..6358732f12 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S @@ -0,0 +1,51 @@ +/* lrintf(), sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__lrintf_vis3) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + fstox %f0, %f4 + retl + movdtox %f4, %o0 +END (__lrintf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S new file mode 100644 index 0000000000..809aaa8a14 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S @@ -0,0 +1,51 @@ +#include + + .text +ENTRY(__lrintf) + .type __lrintf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__lrintf_vis3), %o1 + xor %o1, %gdop_lox10(__lrintf_vis3), %o1 +# else + set __lrintf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__lrintf_generic), %o1 + xor %o1, %gdop_lox10(__lrintf_generic), %o1 +# else + set __lrintf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__lrintf) +weak_alias (__lrintf, lrintf) + +strong_alias (__lrintf, __llrintf) +weak_alias (__llrintf, llrintf) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __lrintf __lrintf_generic + +#include "../s_lrintf.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S new file mode 100644 index 0000000000..d4fcd19d9b --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S @@ -0,0 +1,50 @@ +/* Round float to int floating-point values, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + fzero ZERO + + fnegd ZERO, SIGN_BIT + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__rint_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S new file mode 100644 index 0000000000..3872ae299e --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__rint) + .type __rint, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__rint_vis3), %o1 + xor %o1, %gdop_lox10(__rint_vis3), %o1 +# else + set __rint_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__rint_generic), %o1 + xor %o1, %gdop_lox10(__rint_generic), %o1 +# else + set __rint_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__rint) +weak_alias (__rint, rint) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rint __rint_generic + +#include "../s_rint.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S new file mode 100644 index 0000000000..ea640589e4 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S @@ -0,0 +1,49 @@ +/* Round float to int floating-point values, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rintf_vis3) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__rintf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S new file mode 100644 index 0000000000..9918929220 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__rintf) + .type __rintf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__rintf_vis3), %o1 + xor %o1, %gdop_lox10(__rintf_vis3), %o1 +# else + set __rintf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__rintf_generic), %o1 + xor %o1, %gdop_lox10(__rintf_generic), %o1 +# else + set __rintf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__rintf) +weak_alias (__rintf, rintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rintf __rintf_generic + +#include "../s_rintf.S"