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powerpc: Simplify encoding of POWER8 instruction

This commit is contained in:
Adhemerval Zanella 2014-11-05 08:01:09 -05:00
parent 29955b5d96
commit 7110166d4f
7 changed files with 22 additions and 36 deletions
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17
ChangeLog
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@ -1,4 +1,19 @@
2014-10-30 Arjun Shankar <arjun.is@lostca.se>
2014-11-05 Adhemerval Zanella <azanella@linux.vnet.ibm.com>
* sysdeps/powerpc/powerpc64/power8/memset.S (MTVSRD_V1_R4): Simplify
definition.
* sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S (MFVSRD_R3_V1):
Likwise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S (MFVSRD_R3_V1):
Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S (MFVSRD_R3_V1):
Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S (MFVSRD_R3_V1):
Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S (MFVSRD_R3_V1):
Likewise.
2014-11-05 Arjun Shankar <arjun.is@lostca.se>
* catgets/test-gencat.c: Use test-skeleton.c.
* catgets/tst-catgets.c: Likewise.

7
sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S
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@ -17,14 +17,9 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
#include <endian.h>
#include <math_ldbl_opt.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */
#else
#define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */
#endif
#define MFVSRD_R3_V1 .long 0x7c230066 /* mfvsrd r3,vs1 */
/* int [r3] __finite ([fp1] x) */

7
sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S
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@ -17,14 +17,9 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
#include <endian.h>
#include <math_ldbl_opt.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */
#else
#define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */
#endif
#define MFVSRD_R3_V1 .long 0x7c230066 /* mfvsrd r3,vs1 */
/* int [r3] __isinf([fp1] x) */

7
sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S
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@ -17,14 +17,9 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
#include <endian.h>
#include <math_ldbl_opt.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */
#else
#define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */
#endif
#define MFVSRD_R3_V1 .long 0x7c230066 /* mfvsrd r3,vs1 */
/* int [r3] __isnan([f1] x) */

7
sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S
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@ -17,14 +17,9 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
#include <endian.h>
#include <math_ldbl_opt.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */
#else
#define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */
#endif
#define MFVSRD_R3_V1 .long 0x7c230066 /* mfvsrd r3,vs1 */
/* long long int[r3] __llrint (double x[fp1]) */
ENTRY (__llrint)

6
sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S
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@ -20,11 +20,7 @@
#include <endian.h>
#include <math_ldbl_opt.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */
#else
#define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */
#endif
#define MFVSRD_R3_V1 .long 0x7c230066 /* mfvsrd r3,vs1 */
/* long long [r3] llround (float x [fp1]) */

7
sysdeps/powerpc/powerpc64/power8/memset.S
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@ -17,13 +17,8 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
#include <endian.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define MTVSRD_V1_R4 .byte 0x66,0x01,0x24,0x7c /* mtvsrd v1,r4 */
#else
#define MTVSRD_V1_R4 .byte 0x7c,0x24,0x01,0x66
#endif
#define MTVSRD_V1_R4 .long 0x7c240166 /* mtvsrd v1,r4 */
/* __ptr_t [r3] memset (__ptr_t s [r3], int c [r4], size_t n [r5]));
Returns 's'. */