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Remove atomic_compare_and_exchange_bool_rel. 

atomic_compare_and_exchange_bool_rel and
catomic_compare_and_exchange_bool_rel are removed and replaced with the
new C11-like atomic_compare_exchange_weak_release.  The concurrent code
in nscd/cache.c has not been reviewed yet, so this patch does not add
detailed comments.

	* nscd/cache.c (cache_add): Use new C11-like atomic operation instead
	of atomic_compare_and_exchange_bool_rel.
	* nptl/pthread_mutex_unlock.c (__pthread_mutex_unlock_full): Likewise.
	* include/atomic.h (atomic_compare_and_exchange_bool_rel,
	catomic_compare_and_exchange_bool_rel): Remove.
	* sysdeps/aarch64/atomic-machine.h
	(atomic_compare_and_exchange_bool_rel): Likewise.
	* sysdeps/alpha/atomic-machine.h
	(atomic_compare_and_exchange_bool_rel): Likewise.
	* sysdeps/arm/atomic-machine.h
	(atomic_compare_and_exchange_bool_rel): Likewise.
	* sysdeps/mips/atomic-machine.h
	(atomic_compare_and_exchange_bool_rel): Likewise.
	* sysdeps/tile/atomic-machine.h
	(atomic_compare_and_exchange_bool_rel): Likewise.
This commit is contained in:
Torvald Riegel 2016-06-14 15:12:00 +02:00
parent 40244be372
commit 76a0b73e81
13 changed files with 58 additions and 124 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
ChangeLog
View File

@ -1,3 +1,33 @@
2016-06-24 Torvald Riegel <triegel@redhat.com>
* nscd/cache.c (cache_add): Use new C11-like atomic operation instead
of atomic_compare_and_exchange_bool_rel.
* nptl/pthread_mutex_unlock.c (__pthread_mutex_unlock_full): Likewise.
* include/atomic.h (atomic_compare_and_exchange_bool_rel,
catomic_compare_and_exchange_bool_rel): Remove.
* sysdeps/aarch64/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/alpha/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/arm/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/mips/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/microblaze/atomic-machine.h
( __arch_compare_and_exchange_bool_8_rel,
__arch_compare_and_exchange_bool_16_rel): Likewise.
* sysdeps/powerpc/atomic-machine.h
( __arch_compare_and_exchange_bool_8_rel,
__arch_compare_and_exchange_bool_16_rel): Likewise.
* sysdeps/powerpc/powerpc32/atomic-machine.h
( __arch_compare_and_exchange_bool_32_rel,
__arch_compare_and_exchange_bool_64_rel): Likewise.
* sysdeps/powerpc/powerpc64/atomic-machine.h
( __arch_compare_and_exchange_bool_32_rel,
__arch_compare_and_exchange_bool_64_rel): Likewise.
* sysdeps/tile/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
2016-06-23 Joseph Myers <joseph@codesourcery.com>
[BZ #20296]

17
include/atomic.h
View File

@ -159,23 +159,6 @@
#endif
#ifndef catomic_compare_and_exchange_bool_rel
# ifndef atomic_compare_and_exchange_bool_rel
# define catomic_compare_and_exchange_bool_rel(mem, newval, oldval) \
catomic_compare_and_exchange_bool_acq (mem, newval, oldval)
# else
# define catomic_compare_and_exchange_bool_rel(mem, newval, oldval) \
atomic_compare_and_exchange_bool_rel (mem, newval, oldval)
# endif
#endif
#ifndef atomic_compare_and_exchange_bool_rel
# define atomic_compare_and_exchange_bool_rel(mem, newval, oldval) \
atomic_compare_and_exchange_bool_acq (mem, newval, oldval)
#endif
/* Store NEWVALUE in *MEM and return the old value. */
#ifndef atomic_exchange_acq
# define atomic_exchange_acq(mem, newvalue) \

34
nptl/pthread_mutex_unlock.c
View File

@ -237,15 +237,24 @@ __pthread_mutex_unlock_full (pthread_mutex_t *mutex, int decr)
int private = (robust
? PTHREAD_ROBUST_MUTEX_PSHARED (mutex)
: PTHREAD_MUTEX_PSHARED (mutex));
if ((mutex->__data.__lock & FUTEX_WAITERS) != 0
|| atomic_compare_and_exchange_bool_rel (&mutex->__data.__lock, 0,
THREAD_GETMEM (THREAD_SELF,
tid)))
/* Unlock the mutex using a CAS unless there are futex waiters or our
TID is not the value of __lock anymore, in which case we let the
kernel take care of the situation. Use release MO in the CAS to
synchronize with acquire MO in lock acquisitions. */
int l = atomic_load_relaxed (&mutex->__data.__lock);
do
{
INTERNAL_SYSCALL_DECL (__err);
INTERNAL_SYSCALL (futex, __err, 2, &mutex->__data.__lock,
__lll_private_flag (FUTEX_UNLOCK_PI, private));
if (((l & FUTEX_WAITERS) != 0)
|| (l != THREAD_GETMEM (THREAD_SELF, tid)))
{
INTERNAL_SYSCALL_DECL (__err);
INTERNAL_SYSCALL (futex, __err, 2, &mutex->__data.__lock,
__lll_private_flag (FUTEX_UNLOCK_PI, private));
break;
}
}
while (!atomic_compare_exchange_weak_release (&mutex->__data.__lock,
&l, 0));
THREAD_SETMEM (THREAD_SELF, robust_head.list_op_pending, NULL);
break;
@ -278,15 +287,16 @@ __pthread_mutex_unlock_full (pthread_mutex_t *mutex, int decr)
/* One less user. */
--mutex->__data.__nusers;
/* Unlock. */
int newval, oldval;
/* Unlock. Use release MO in the CAS to synchronize with acquire MO in
lock acquisitions. */
int newval;
int oldval = atomic_load_relaxed (&mutex->__data.__lock);
do
{
oldval = mutex->__data.__lock;
newval = oldval & PTHREAD_MUTEX_PRIO_CEILING_MASK;
}
while (atomic_compare_and_exchange_bool_rel (&mutex->__data.__lock,
newval, oldval));
while (!atomic_compare_exchange_weak_release (&mutex->__data.__lock,
&oldval, newval));
if ((oldval & ~PTHREAD_MUTEX_PRIO_CEILING_MASK) > 1)
lll_futex_wake (&mutex->__data.__lock, 1,

12
nscd/cache.c
View File

@ -178,12 +178,12 @@ cache_add (int type, const void *key, size_t len, struct datahead *packet,
assert ((newp->packet & BLOCK_ALIGN_M1) == 0);
/* Put the new entry in the first position. */
do
newp->next = table->head->array[hash];
while (atomic_compare_and_exchange_bool_rel (&table->head->array[hash],
(ref_t) ((char *) newp
- table->data),
(ref_t) newp->next));
/* TODO Review concurrency. Use atomic_exchange_release. */
newp->next = atomic_load_relaxed (&table->head->array[hash]);
while (!atomic_compare_exchange_weak_release (&table->head->array[hash],
(ref_t *) &newp->next,
(ref_t) ((char *) newp
- table->data)));
/* Update the statistics. */
if (packet->notfound)

4
sysdeps/aarch64/atomic-machine.h
View File

@ -115,10 +115,6 @@ typedef uintmax_t uatomic_max_t;
/* Compare and exchange with "release" semantics, ie barrier before. */
# define atomic_compare_and_exchange_bool_rel(mem, new, old) \
__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
mem, new, old, __ATOMIC_RELEASE)
# define atomic_compare_and_exchange_val_rel(mem, new, old) \
__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
mem, new, old, __ATOMIC_RELEASE)

4
sysdeps/alpha/atomic-machine.h
View File

@ -210,10 +210,6 @@ typedef uintmax_t uatomic_max_t;
/* Compare and exchange with "release" semantics, ie barrier before. */
#define atomic_compare_and_exchange_bool_rel(mem, new, old) \
__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
mem, new, old, __MB, "")
#define atomic_compare_and_exchange_val_rel(mem, new, old) \
__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
mem, new, old, __MB, "")

4
sysdeps/arm/atomic-machine.h
View File

@ -87,10 +87,6 @@ void __arm_link_error (void);
/* Compare and exchange with "release" semantics, ie barrier before. */
# define atomic_compare_and_exchange_bool_rel(mem, new, old) \
__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
mem, new, old, __ATOMIC_RELEASE)
# define atomic_compare_and_exchange_val_rel(mem, new, old) \
__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
mem, new, old, __ATOMIC_RELEASE)

6
sysdeps/microblaze/atomic-machine.h
View File

@ -47,12 +47,6 @@ typedef uintmax_t uatomic_max_t;
#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
(abort (), 0)
#define __arch_compare_and_exchange_bool_8_rel(mem, newval, oldval) \
(abort (), 0)
#define __arch_compare_and_exchange_bool_16_rel(mem, newval, oldval) \
(abort (), 0)
#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
({ \
__typeof (*(mem)) __tmp; \

8
sysdeps/mips/atomic-machine.h
View File

@ -149,10 +149,6 @@ typedef uintmax_t uatomic_max_t;
/* Compare and exchange with "release" semantics, ie barrier before. */
# define atomic_compare_and_exchange_bool_rel(mem, new, old) \
__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
mem, new, old, __ATOMIC_RELEASE)
# define atomic_compare_and_exchange_val_rel(mem, new, old) \
__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
mem, new, old, __ATOMIC_RELEASE)
@ -330,10 +326,6 @@ typedef uintmax_t uatomic_max_t;
/* Compare and exchange with "release" semantics, ie barrier before. */
# define atomic_compare_and_exchange_bool_rel(mem, new, old) \
__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
mem, new, old, MIPS_SYNC_STR, "")
# define atomic_compare_and_exchange_val_rel(mem, new, old) \
__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
mem, new, old, MIPS_SYNC_STR, "")

6
sysdeps/powerpc/atomic-machine.h
View File

@ -53,12 +53,6 @@ typedef uintmax_t uatomic_max_t;
#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
(abort (), 0)
#define __arch_compare_and_exchange_bool_8_rel(mem, newval, oldval) \
(abort (), 0)
#define __arch_compare_and_exchange_bool_16_rel(mem, newval, oldval) \
(abort (), 0)
#ifdef UP
# define __ARCH_ACQ_INSTR ""
# define __ARCH_REL_INSTR ""

19
sysdeps/powerpc/powerpc32/atomic-machine.h
View File

@ -58,22 +58,6 @@
__tmp != 0; \
})
#define __arch_compare_and_exchange_bool_32_rel(mem, newval, oldval) \
({ \
unsigned int __tmp; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
"1: lwarx %0,0,%1" MUTEX_HINT_REL "\n" \
" subf. %0,%2,%0\n" \
" bne 2f\n" \
" stwcx. %3,0,%1\n" \
" bne- 1b\n" \
"2: " \
: "=&r" (__tmp) \
: "b" (mem), "r" (oldval), "r" (newval) \
: "cr0", "memory"); \
__tmp != 0; \
})
/* Powerpc32 processors don't implement the 64-bit (doubleword) forms of
load and reserve (ldarx) and store conditional (stdcx.) instructions.
So for powerpc32 we stub out the 64-bit forms. */
@ -83,9 +67,6 @@
#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
#define __arch_compare_and_exchange_bool_64_rel(mem, newval, oldval) \
(abort (), 0)
#define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)

33
sysdeps/powerpc/powerpc64/atomic-machine.h
View File

@ -58,23 +58,6 @@
__tmp != 0; \
})
#define __arch_compare_and_exchange_bool_32_rel(mem, newval, oldval) \
({ \
unsigned int __tmp, __tmp2; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
" clrldi %1,%1,32\n" \
"1: lwarx %0,0,%2" MUTEX_HINT_REL "\n" \
" subf. %0,%1,%0\n" \
" bne 2f\n" \
" stwcx. %4,0,%2\n" \
" bne- 1b\n" \
"2: " \
: "=&r" (__tmp), "=r" (__tmp2) \
: "b" (mem), "1" (oldval), "r" (newval) \
: "cr0", "memory"); \
__tmp != 0; \
})
/*
* Only powerpc64 processors support Load doubleword and reserve index (ldarx)
* and Store doubleword conditional indexed (stdcx) instructions. So here
@ -96,22 +79,6 @@
__tmp != 0; \
})
#define __arch_compare_and_exchange_bool_64_rel(mem, newval, oldval) \
({ \
unsigned long __tmp; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
"1: ldarx %0,0,%1" MUTEX_HINT_REL "\n" \
" subf. %0,%2,%0\n" \
" bne 2f\n" \
" stdcx. %3,0,%1\n" \
" bne- 1b\n" \
"2: " \
: "=&r" (__tmp) \
: "b" (mem), "r" (oldval), "r" (newval) \
: "cr0", "memory"); \
__tmp != 0; \
})
#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
({ \
__typeof (*(mem)) __tmp; \

5
sysdeps/tile/atomic-machine.h
View File

@ -55,11 +55,6 @@ typedef uintmax_t uatomic_max_t;
atomic_full_barrier (); \
atomic_compare_and_exchange_val_acq ((mem), (n), (o)); \
})
#define atomic_compare_and_exchange_bool_rel(mem, n, o) \
({ \
atomic_full_barrier (); \
atomic_compare_and_exchange_bool_acq ((mem), (n), (o)); \
})
#define atomic_exchange_rel(mem, n) \
({ \
atomic_full_barrier (); \