Check the HTT bit before counting logical threads
Skip counting logical threads for Intel processors if the HTT bit is 0 which indicates there is only a single logical processor. * sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting logical threads if the HTT bit is 0. * sysdeps/x86/cpu-features.h (bit_cpu_HTT): New. (index_cpu_HTT): Likewise. (reg_HTT): Likewise.
This commit is contained in:
H.J. Lu
parent
eb2c88c7c8
commit
7c08d791ee
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@ -1,3 +1,11 @@
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2016-05-19 H.J. Lu <hongjiu.lu@intel.com>
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* sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting
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logical threads if the HTT bit is 0.
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* sysdeps/x86/cpu-features.h (bit_cpu_HTT): New.
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(index_cpu_HTT): Likewise.
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(reg_HTT): Likewise.
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2016-05-19 H.J. Lu <hongjiu.lu@intel.com>
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[BZ #20115]
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@ -506,99 +506,105 @@ init_cacheinfo (void)
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shared = core;
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}
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/* Figure out the number of logical threads that share the
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highest cache level. */
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if (max_cpuid >= 4)
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/* A value of 0 for the HTT bit indicates there is only a single
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logical processor. */
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if (HAS_CPU_FEATURE (HTT))
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{
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unsigned int family = GLRO(dl_x86_cpu_features).family;
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unsigned int model = GLRO(dl_x86_cpu_features).model;
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int i = 0;
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/* Query until desired cache level is enumerated. */
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do
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/* Figure out the number of logical threads that share the
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highest cache level. */
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if (max_cpuid >= 4)
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{
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__cpuid_count (4, i++, eax, ebx, ecx, edx);
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unsigned int family = GLRO(dl_x86_cpu_features).family;
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unsigned int model = GLRO(dl_x86_cpu_features).model;
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/* There seems to be a bug in at least some Pentium Ds
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which sometimes fail to iterate all cache parameters.
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Do not loop indefinitely here, stop in this case and
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assume there is no such information. */
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if ((eax & 0x1f) == 0)
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goto intel_bug_no_cache_info;
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}
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while (((eax >> 5) & 0x7) != level);
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int i = 0;
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/* Check if cache is inclusive of lower cache levels. */
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inclusive_cache = (edx & 0x2) != 0;
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threads = (eax >> 14) & 0x3ff;
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/* If max_cpuid >= 11, THREADS is the maximum number of
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addressable IDs for logical processors sharing the
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cache, instead of the maximum number of threads
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sharing the cache. */
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if (threads && max_cpuid >= 11)
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{
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/* Find the number of logical processors shipped in
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one core and apply count mask. */
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i = 0;
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while (1)
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/* Query until desired cache level is enumerated. */
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do
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{
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__cpuid_count (11, i++, eax, ebx, ecx, edx);
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__cpuid_count (4, i++, eax, ebx, ecx, edx);
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int shipped = ebx & 0xff;
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int type = ecx & 0xff0;
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if (shipped == 0 || type == 0)
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break;
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else if (type == 0x200)
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/* There seems to be a bug in at least some Pentium Ds
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which sometimes fail to iterate all cache parameters.
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Do not loop indefinitely here, stop in this case and
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assume there is no such information. */
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if ((eax & 0x1f) == 0)
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goto intel_bug_no_cache_info;
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}
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while (((eax >> 5) & 0x7) != level);
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/* Check if cache is inclusive of lower cache levels. */
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inclusive_cache = (edx & 0x2) != 0;
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threads = (eax >> 14) & 0x3ff;
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/* If max_cpuid >= 11, THREADS is the maximum number of
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addressable IDs for logical processors sharing the
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cache, instead of the maximum number of threads
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sharing the cache. */
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if (threads && max_cpuid >= 11)
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{
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/* Find the number of logical processors shipped in
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one core and apply count mask. */
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i = 0;
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while (1)
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{
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int count_mask;
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__cpuid_count (11, i++, eax, ebx, ecx, edx);
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/* Compute count mask. */
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asm ("bsr %1, %0"
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: "=r" (count_mask) : "g" (threads));
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count_mask = ~(-1 << (count_mask + 1));
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threads = (shipped - 1) & count_mask;
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int shipped = ebx & 0xff;
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int type = ecx & 0xff0;
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if (shipped == 0 || type == 0)
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break;
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else if (type == 0x200)
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{
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int count_mask;
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/* Compute count mask. */
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asm ("bsr %1, %0"
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: "=r" (count_mask) : "g" (threads));
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count_mask = ~(-1 << (count_mask + 1));
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threads = (shipped - 1) & count_mask;
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break;
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}
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}
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}
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threads += 1;
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if (threads > 2 && level == 2 && family == 6)
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{
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switch (model)
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{
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case 0x57:
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/* Knights Landing has L2 cache shared by 2 cores. */
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case 0x37:
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case 0x4a:
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case 0x4d:
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case 0x5a:
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case 0x5d:
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/* Silvermont has L2 cache shared by 2 cores. */
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threads = 2;
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break;
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default:
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break;
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}
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}
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}
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threads += 1;
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if (threads > 2 && level == 2 && family == 6)
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else
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{
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switch (model)
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{
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case 0x57:
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/* Knights Landing has L2 cache shared by 2 cores. */
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case 0x37:
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case 0x4a:
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case 0x4d:
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case 0x5a:
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case 0x5d:
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/* Silvermont has L2 cache shared by 2 cores. */
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threads = 2;
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break;
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default:
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break;
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}
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intel_bug_no_cache_info:
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/* Assume that all logical threads share the highest cache
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level. */
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threads
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= ((GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].ebx
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>> 16) & 0xff);
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}
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}
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else
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{
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intel_bug_no_cache_info:
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/* Assume that all logical threads share the highest cache level. */
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threads
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= ((GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].ebx
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>> 16) & 0xff);
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/* Cap usage of highest cache level to the number of supported
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threads. */
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if (shared > 0 && threads > 0)
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shared /= threads;
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}
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/* Cap usage of highest cache level to the number of supported
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threads. */
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if (shared > 0 && threads > 0)
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shared /= threads;
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/* Account for non-inclusive L2 and L3 caches. */
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if (level == 3 && !inclusive_cache)
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shared += core;
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@ -51,6 +51,7 @@
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#define bit_cpu_POPCOUNT (1 << 23)
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#define bit_cpu_FMA (1 << 12)
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#define bit_cpu_FMA4 (1 << 16)
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#define bit_cpu_HTT (1 << 28)
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/* COMMON_CPUID_INDEX_7. */
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#define bit_cpu_ERMS (1 << 9)
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@ -235,6 +236,7 @@ extern const struct cpu_features *__get_cpu_features (void)
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# define index_cpu_FMA4 COMMON_CPUID_INDEX_80000001
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# define index_cpu_POPCOUNT COMMON_CPUID_INDEX_1
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# define index_cpu_OSXSAVE COMMON_CPUID_INDEX_1
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# define index_cpu_HTT COMMON_CPUID_INDEX_1
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# define reg_CX8 edx
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# define reg_CMOV edx
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@ -252,6 +254,7 @@ extern const struct cpu_features *__get_cpu_features (void)
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# define reg_FMA4 ecx
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# define reg_POPCOUNT ecx
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# define reg_OSXSAVE ecx
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# define reg_HTT edx
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# define index_arch_Fast_Rep_String FEATURE_INDEX_1
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# define index_arch_Fast_Copy_Backward FEATURE_INDEX_1
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