aarch64: Optimized memchr specific to AmpereComputing emag
This version uses general register based memory instruction to load
data, because vector register based is slightly slower in emag.
Character-matching is performed on 16-byte (both size and alignment)
memory block in parallel each iteration.
* sysdeps/aarch64/memchr.S (__memchr): Rename to MEMCHR.
[!MEMCHR](MEMCHR): Set to __memchr.
* sysdeps/aarch64/multiarch/Makefile (sysdep_routines):
Add memchr_generic and memchr_nosimd.
* sysdeps/aarch64/multiarch/ifunc-impl-list.c
(__libc_ifunc_impl_list): Add memchr ifuncs.
* sysdeps/aarch64/multiarch/memchr.c: New file.
* sysdeps/aarch64/multiarch/memchr_generic.S: Likewise.
* sysdeps/aarch64/multiarch/memchr_nosimd.S: Likewise.
This commit is contained in:
Feng Xue
parent
c7d3890ff5
commit
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12
ChangeLog
12
ChangeLog
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@ -1,3 +1,15 @@
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2019-02-01 Feng Xue <fxue@os.amperecomputing.com>
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* sysdeps/aarch64/memchr.S (__memchr): Rename to MEMCHR.
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[!MEMCHR](MEMCHR): Set to __memchr.
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* sysdeps/aarch64/multiarch/Makefile (sysdep_routines):
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Add memchr_generic and memchr_nosimd.
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* sysdeps/aarch64/multiarch/ifunc-impl-list.c
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(__libc_ifunc_impl_list): Add memchr ifuncs.
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* sysdeps/aarch64/multiarch/memchr.c: New file.
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* sysdeps/aarch64/multiarch/memchr_generic.S: Likewise.
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* sysdeps/aarch64/multiarch/memchr_nosimd.S: Likewise.
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2019-02-01 Feng Xue <fxue@os.amperecomputing.com>
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* sysdeps/aarch64/multiarch/Makefile (sysdep_routines):
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@ -26,6 +26,10 @@
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* Neon Available.
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*/
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#ifndef MEMCHR
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# define MEMCHR __memchr
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#endif
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/* Arguments and results. */
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#define srcin x0
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#define chrin w1
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@ -59,7 +63,7 @@
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* identify exactly which byte has matched.
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*/
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ENTRY (__memchr)
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ENTRY (MEMCHR)
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/* Do not dereference srcin if no bytes to compare. */
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cbz cntin, L(zero_length)
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/*
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@ -152,6 +156,6 @@ L(tail):
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L(zero_length):
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mov result, #0
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ret
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END (__memchr)
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weak_alias (__memchr, memchr)
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END (MEMCHR)
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weak_alias (MEMCHR, memchr)
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libc_hidden_builtin_def (memchr)
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@ -2,5 +2,6 @@ ifeq ($(subdir),string)
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sysdep_routines += memcpy_generic memcpy_thunderx memcpy_thunderx2 \
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memcpy_falkor memmove_falkor \
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memset_generic memset_falkor memset_emag \
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memchr_generic memchr_nosimd \
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strlen_generic strlen_asimd
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endif
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@ -53,6 +53,9 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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IFUNC_IMPL_ADD (array, i, memset, (zva_size == 64), __memset_falkor)
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IFUNC_IMPL_ADD (array, i, memset, (zva_size == 64), __memset_emag)
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IFUNC_IMPL_ADD (array, i, memset, 1, __memset_generic))
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IFUNC_IMPL (i, name, memchr,
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IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_nosimd)
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IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_generic))
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IFUNC_IMPL (i, name, strlen,
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IFUNC_IMPL_ADD (array, i, strlen, 1, __strlen_asimd)
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@ -0,0 +1,41 @@
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/* Multiple versions of memchr. AARCH64 version.
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Copyright (C) 2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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/* Define multiple versions only for the definition in libc. */
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#if IS_IN (libc)
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/* Redefine memchr so that the compiler won't complain about the type
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mismatch with the IFUNC selector in strong_alias, below. */
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# undef memchr
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# define memchr __redirect_memchr
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# include <string.h>
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# include <init-arch.h>
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extern __typeof (__redirect_memchr) __memchr;
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extern __typeof (__redirect_memchr) __memchr_generic attribute_hidden;
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extern __typeof (__redirect_memchr) __memchr_nosimd attribute_hidden;
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libc_ifunc (__memchr,
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((IS_EMAG (midr)
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? __memchr_nosimd
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: __memchr_generic)));
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# undef memchr
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strong_alias (__memchr, memchr);
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#endif
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@ -0,0 +1,33 @@
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/* Memchr for aarch64, default version for internal use.
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Copyright (C) 2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#if IS_IN (libc)
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# define MEMCHR __memchr_generic
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/* Do not hide the generic version of memchr, we use it internally. */
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# undef libc_hidden_builtin_def
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# define libc_hidden_builtin_def(name)
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/* Add a hidden definition for use within libc.so. */
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# ifdef SHARED
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.globl __GI_memchr; __GI_memchr = __memchr_generic
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# endif
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#endif
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# include "../memchr.S"
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@ -0,0 +1,223 @@
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/* memchr - find a character in a memory zone using base integer registers
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Copyright (C) 2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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/* Assumptions:
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*
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* ARMv8-a, AArch64
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* Use base integer registers.
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*/
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#ifndef MEMCHR
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# define MEMCHR __memchr_nosimd
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#endif
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/* Arguments and results. */
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#define srcin x0
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#define chrin x1
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#define cntin x2
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#define result x0
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#define repchr x1
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#define tmp1 x2
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#define tmp2 x3
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#define tmp3 x4
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#define tmp4 x5
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#define src x6
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#define srcend x7
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#define srcend16 x8
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#define anymore x9
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#define zeroones x10
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#define data1 x11
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#define data2 x12
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#define has_chr1 x13
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#define has_chr2 x14
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#define REP8_01 0x0101010101010101
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#define REP8_7f 0x7f7f7f7f7f7f7f7f
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ENTRY_ALIGN (MEMCHR, 6)
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DELOUSE (0)
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DELOUSE (2)
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/* Do not dereference srcin if no bytes to compare. */
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cbz cntin, L(none_chr)
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/* Start address is 16-byte aligned or not? */
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tst srcin, 15
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bic src, srcin, 15
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mov zeroones, REP8_01
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and repchr, chrin, 255
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/* Generate a qword integer as |c|c|c|c|c|c|c|c|. */
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mul repchr, repchr, zeroones
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add srcend, srcin, cntin
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/*
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* srcend16 is address of the block following the last block.
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*
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* [A block is 16-byte aligned and sized.]
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*/
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add srcend16, srcend, 15
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bic srcend16, srcend16, 15
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b.eq L(loop)
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/* Load the first block containing start address. */
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ldp data1, data2, [src], 16
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lsl tmp1, srcin, 3
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mov tmp2, ~0
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#ifdef __AARCH64EB__
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lsr tmp3, tmp2, tmp1
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#else
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lsl tmp3, tmp2, tmp1
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#endif
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/* Start address is in the first or the second qword? */
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tst srcin, 8
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/*
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* Transform any byte in the block to zero using XOR operation,
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* if that byte equals the char to search. In this way, searching
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* the char becomes detecting zero in the resulting two qwords.
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*/
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eor data1, data1, repchr
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eor data2, data2, repchr
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/*
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* Set those unused bytes(before start address) to 0xff, so
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* that they will not hit any zero detection.
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*/
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orn tmp1, data1, tmp3
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orn tmp2, data2, tmp3
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csinv data1, tmp1, xzr, eq
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csel data2, data2, tmp2, eq
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/*
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* When the first and last block are the same, there are two cases:
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* o. Memory range to search is just in one block.
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* ( start address - end address) < 0
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*
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* o. Memory range is so large that end address wrap-around.
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* ( start address - end address) > 0
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*/
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cmp srcin, srcend
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ccmp src, srcend16, 0, mi
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csetm anymore, ne
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b L(find_chr)
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.p2align 4
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L(loop):
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ldp data1, data2, [src], 16
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subs anymore, src, srcend16
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/*
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* Transform any byte in the block to zero using XOR operation,
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* if that byte equals the char to search.
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*/
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eor data1, data1, repchr
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eor data2, data2, repchr
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L(find_chr):
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/*
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* Use the following integer test to find out if any byte in a
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* qword is zero. If do not contain zero-valued byte, test result
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* is zero.
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*
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* (qword - 0x0101010101010101) & ~(qword) & 0x8080808080808080
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* =
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* (qword - 0x0101010101010101) & ~(qword | 0x7f7f7f7f7f7f7f7f)
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*
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*/
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sub tmp1, data1, zeroones
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sub tmp2, data2, zeroones
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orr tmp3, data1, REP8_7f
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orr tmp4, data2, REP8_7f
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bic has_chr1, tmp1, tmp3
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bic has_chr2, tmp2, tmp4
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orr tmp1, has_chr1, has_chr2
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ccmp tmp1, 0, 0, ne
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b.eq L(loop)
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cbz has_chr1, 1f
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sub result, src, 16
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#ifdef __AARCH64EB__
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rev data1, data1
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#else
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rev has_chr1, has_chr1
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#endif
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b L(done)
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1: cbz has_chr2, L(none_chr)
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sub result, src, 8
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#ifdef __AARCH64EB__
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rev data1, data2
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#else
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rev has_chr1, has_chr2
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#endif
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L(done):
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#ifdef __AARCH64EB__
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/*
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* For big-endian, can not directly use has_chr1/has_chr2 because
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* two qwords has been reversed after loading from memory.
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* Thus, have to perform char detection on two qwords again, which
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* should be byte-swapped this time.
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*/
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sub tmp1, data1, zeroones
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orr tmp3, data1, REP8_7f
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bic has_chr1, tmp1, tmp3
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rev has_chr1, has_chr1
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#endif
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/*
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* If the specified char is found in a qword, the corresponding
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* byte of in has_chr has value of 1, while this is only true for
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* the first occurrence, not other occurrences.
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*/
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cmp anymore, 0
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clz tmp1, has_chr1
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add result, result, tmp1, lsr 3
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ccmp result, srcend, 8, eq /* NZCV = 8000 */
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csel result, result, xzr, mi
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ret
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L(none_chr):
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mov result, 0
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ret
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END (MEMCHR)
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libc_hidden_builtin_def (MEMCHR)
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