Simplify tile assembly definitions
With tilepro removal, the uppercase instruction are not anymore required to be defines as potentially macros. This is a mechanical change done by the following shell script: --- INSNS="LD LD4U ST ST4 BNEZ BEQZ BEQZT BGTZ CMPEQI CMPEQ CMOVEQZ CMOVNEZ" FILES=$(find sysdeps/tile sysdeps/unix/sysv/linux/tile -iname *.S) for insn in $INSNS; do repl=$(echo $insn | tr '[:upper:]' '[:lower:]') sed -i 's/\b'$insn'\b/'$repl'/g' $FILES done --- Checked with a build for tilegx-linux-gnu and tilegx-linux-gnu-32 with and without the patch, there is no difference in generated binary with a dissassemble. * sysdeps/tile/__longjmp.S (__longjmp): Use lowercase instructions. * sysdeps/tile/__tls_get_addr.S (__tls_get_addr): Likewise. * sysdeps/tile/_mcount.S (__mcount): Likewise. * sysdeps/tile/crti.S (_init, _fini): Likewise. * sysdeps/tile/crtn.S: Likewise. * sysdeps/tile/dl-start.S (_start): Likewise. * sysdeps/tile/dl-trampoline.S: Likewise. * sysdeps/tile/setjmp.S (__sigsetjmp): Likewise. * sysdeps/tile/start.S (_start): Likewise. * sysdeps/unix/sysv/linux/tile/clone.S (_clone): Likewise. * sysdeps/unix/sysv/linux/tile/getcontext.S (__getcontext): Likewise. * sysdeps/unix/sysv/linux/tile/ioctl.S (__ioctl): Likewise. * sysdeps/unix/sysv/linux/tile/setcontext.S (__setcontext): Likewise. * sysdeps/unix/sysv/linux/tile/swapcontext.S (__swapcontext): Likewise. * sysdeps/unix/sysv/linux/tile/syscall.S (syscall): Likewise. * sysdeps/unix/sysv/linux/tile/vfork.S (__vfork): Likewise.
This commit is contained in:
Adhemerval Zanella
parent
24d1d8ec9e
commit
8d2d239cb7
17
ChangeLog
17
ChangeLog
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@ -1,5 +1,22 @@
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2017-12-20 Adhemerval Zanella <adhemerval.zanella@linaro.org>
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* sysdeps/tile/__longjmp.S (__longjmp): Use lowercase instructions.
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* sysdeps/tile/__tls_get_addr.S (__tls_get_addr): Likewise.
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* sysdeps/tile/_mcount.S (__mcount): Likewise.
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* sysdeps/tile/crti.S (_init, _fini): Likewise.
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* sysdeps/tile/crtn.S: Likewise.
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* sysdeps/tile/dl-start.S (_start): Likewise.
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* sysdeps/tile/dl-trampoline.S: Likewise.
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* sysdeps/tile/setjmp.S (__sigsetjmp): Likewise.
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* sysdeps/tile/start.S (_start): Likewise.
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* sysdeps/unix/sysv/linux/tile/clone.S (_clone): Likewise.
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* sysdeps/unix/sysv/linux/tile/getcontext.S (__getcontext): Likewise.
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* sysdeps/unix/sysv/linux/tile/ioctl.S (__ioctl): Likewise.
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* sysdeps/unix/sysv/linux/tile/setcontext.S (__setcontext): Likewise.
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* sysdeps/unix/sysv/linux/tile/swapcontext.S (__swapcontext): Likewise.
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* sysdeps/unix/sysv/linux/tile/syscall.S (syscall): Likewise.
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* sysdeps/unix/sysv/linux/tile/vfork.S (__vfork): Likewise.
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* stdlib/bug-getcontext.c (do_test): Remove tilepro mention in
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comment.
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* sysdeps/tile/preconfigure: Remove tilegx folder.
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@ -28,7 +28,7 @@
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ENTRY (__longjmp)
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FEEDBACK_ENTER(__longjmp)
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#define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE }
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#define RESTORE(r) { ld r, r0 ; ADDI_PTR r0, r0, REGSIZE }
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FOR_EACH_CALLEE_SAVED_REG(RESTORE)
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/* Make longjmp(buf, 0) return "1" instead.
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@ -36,9 +36,9 @@ ENTRY (__longjmp)
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we can validly load EX_CONTEXT for iret without being
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interrupted halfway through. */
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{
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LD r2, r0 /* retrieve ICS bit from jmp_buf */
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ld r2, r0 /* retrieve ICS bit from jmp_buf */
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movei r3, 1
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CMPEQI r0, r1, 0
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cmpeqi r0, r1, 0
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}
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{
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mtspr INTERRUPT_CRITICAL_SECTION, r3
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@ -53,20 +53,20 @@ ENTRY (__tls_get_addr)
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}
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{
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LD_PTR r29, r29 /* r29 = ti_offset */
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CMPEQ r25, r28, r25 /* r25 nonzero if generation OK */
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cmpeq r25, r28, r25 /* r25 nonzero if generation OK */
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shli r28, r26, LOG_SIZEOF_DTV_T /* byte index into dtv array */
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}
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{
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BEQZ r25, .Lslowpath
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CMPEQI r25, r26, -1 /* r25 nonzero if ti_module invalid */
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beqz r25, .Lslowpath
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cmpeqi r25, r26, -1 /* r25 nonzero if ti_module invalid */
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}
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{
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BNEZ r25, .Lslowpath
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bnez r25, .Lslowpath
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ADD_PTR r28, r28, r27 /* pointer into module array */
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}
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LD_PTR r26, r28 /* r26 = module TLS pointer */
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CMPEQI r25, r26, -1 /* check r26 == TLS_DTV_UNALLOCATED */
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BNEZ r25, .Lslowpath
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cmpeqi r25, r26, -1 /* check r26 == TLS_DTV_UNALLOCATED */
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bnez r25, .Lslowpath
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{
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ADD_PTR r0, r26, r29
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jrp lr
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@ -74,68 +74,68 @@ ENTRY (__tls_get_addr)
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.Lslowpath:
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{
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ST sp, lr
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st sp, lr
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ADDLI_PTR r29, sp, - (25 * REGSIZE)
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}
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cfi_offset (lr, 0)
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{
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ST r29, sp
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st r29, sp
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ADDLI_PTR sp, sp, - (26 * REGSIZE)
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}
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cfi_def_cfa_offset (26 * REGSIZE)
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ADDI_PTR r29, sp, (2 * REGSIZE)
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{ ST r29, r1; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r2; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r3; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r4; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r5; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r6; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r7; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r8; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r9; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r10; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r11; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r12; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r13; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r14; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r15; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r16; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r17; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r18; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r19; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r20; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r21; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r22; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r23; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r24; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r1; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r2; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r3; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r4; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r5; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r6; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r7; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r8; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r9; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r10; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r11; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r12; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r13; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r14; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r15; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r16; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r17; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r18; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r19; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r20; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r21; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r22; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r23; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r24; ADDI_PTR r29, r29, REGSIZE }
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.hidden __tls_get_addr_slow
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jal __tls_get_addr_slow
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ADDI_PTR r29, sp, (2 * REGSIZE)
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{ LD r1, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r2, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r3, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r4, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r5, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r6, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r7, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r8, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r9, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r10, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r11, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r12, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r13, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r14, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r15, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r16, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r17, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r18, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r19, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r20, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r21, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r22, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r23, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r24, r29; ADDLI_PTR sp, sp, (26 * REGSIZE) }
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{ ld r1, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r2, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r3, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r4, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r5, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r6, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r7, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r8, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r9, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r10, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r11, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r12, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r13, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r14, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r15, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r16, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r17, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r18, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r19, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r20, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r21, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r22, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r23, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r24, r29; ADDLI_PTR sp, sp, (26 * REGSIZE) }
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cfi_def_cfa_offset (0)
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LD lr, sp
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ld lr, sp
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jrp lr
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END (__tls_get_addr)
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@ -33,27 +33,27 @@
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.text
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ENTRY(__mcount)
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{
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ST sp, lr
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st sp, lr
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ADDI_PTR r29, sp, - (12 * REGSIZE)
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}
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cfi_offset (lr, 0)
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{
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ADDI_PTR sp, sp, - (13 * REGSIZE)
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ST r29, sp
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st r29, sp
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ADDI_PTR r29, r29, REGSIZE
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}
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cfi_def_cfa_offset (13 * REGSIZE)
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{ ST r29, r0; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r1; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r2; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r3; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r4; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r5; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r6; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r7; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r8; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r9; ADDI_PTR r29, r29, REGSIZE }
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{ ST r29, r10; ADDI_PTR r29, r29, REGSIZE; move r0, r10 }
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{ st r29, r0; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r1; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r2; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r3; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r4; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r5; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r6; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r7; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r8; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r9; ADDI_PTR r29, r29, REGSIZE }
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{ st r29, r10; ADDI_PTR r29, r29, REGSIZE; move r0, r10 }
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{
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move r1, lr
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jal __mcount_internal
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@ -61,20 +61,20 @@ ENTRY(__mcount)
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{
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ADDI_PTR r29, sp, (2 * REGSIZE)
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}
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{ LD r0, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r1, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r2, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r3, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r4, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r5, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r6, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r7, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r8, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r9, r29; ADDI_PTR r29, r29, REGSIZE }
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{ LD r10, r29; ADDI_PTR sp, sp, (13 * REGSIZE) }
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{ ld r0, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r1, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r2, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r3, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r4, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r5, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r6, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r7, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r8, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r9, r29; ADDI_PTR r29, r29, REGSIZE }
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{ ld r10, r29; ADDI_PTR sp, sp, (13 * REGSIZE) }
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cfi_def_cfa_offset (0)
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{
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LD lr, sp
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ld lr, sp
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}
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{
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move lr, r10
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@ -63,10 +63,10 @@ _init:
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{
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move r29, sp
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ADDI_PTR r28, sp, -REGSIZE
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ST sp, lr
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st sp, lr
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}
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ADDI_PTR sp, sp, -(2 * REGSIZE)
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ST r28, r29
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st r28, r29
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#if PREINIT_FUNCTION_WEAK
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lnk r2
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0:
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@ -82,7 +82,7 @@ _init:
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ADD_PTR r0, r0, r1
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ADD_PTR r0, r0, r2
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LD_PTR r0, r0
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BEQZ r0, .Lno_weak_fn
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beqz r0, .Lno_weak_fn
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jalr r0
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#elif !defined(NO_PLT_PCREL)
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/* Since we are calling from the start of the object to the PLT,
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@ -107,7 +107,7 @@ _fini:
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{
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move r29, sp
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ADDI_PTR r28, sp, -REGSIZE
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ST sp, lr
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st sp, lr
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}
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ADDI_PTR sp, sp, -(2 * REGSIZE)
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ST r28, r29
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st r28, r29
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@ -42,7 +42,7 @@
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ADDI_PTR r29, sp, (2 * REGSIZE)
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{
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ADDI_PTR sp, sp, (2 * REGSIZE)
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LD lr, r29
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ld lr, r29
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}
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jrp lr
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@ -50,6 +50,6 @@
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ADDI_PTR r29, sp, (2 * REGSIZE)
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{
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ADDI_PTR sp, sp, (2 * REGSIZE)
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LD lr, r29
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ld lr, r29
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}
|
||||
jrp lr
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ ENTRY (_start)
|
|||
/* Save zero for caller sp in our 'caller' save area, and make
|
||||
sure lr has a zero value, to limit backtraces. */
|
||||
move lr, zero
|
||||
ST r4, zero
|
||||
st r4, zero
|
||||
}
|
||||
{
|
||||
move r0, r52
|
||||
|
|
@ -56,8 +56,8 @@ ENTRY (_start)
|
|||
in which case we have to adjust the argument vector. */
|
||||
lnk r51; .Llink:
|
||||
pic_addr r4, _dl_skip_args
|
||||
LD4U r4, r4
|
||||
BEQZT r4, .Lno_skip
|
||||
ld4u r4, r4
|
||||
beqzt r4, .Lno_skip
|
||||
|
||||
/* Load the argc word at the initial sp and adjust it.
|
||||
We basically jump "sp" up over the first few argv entries
|
||||
|
|
|
|||
|
|
@ -73,8 +73,8 @@
|
|||
f(r20); f(r21); f(r22); f(r23); \
|
||||
f(r24); f(r25)
|
||||
|
||||
#define SAVE(REG) { ST r27, REG; ADDI_PTR r27, r27, REGSIZE }
|
||||
#define RESTORE(REG) { LD REG, r27; ADDI_PTR r27, r27, REGSIZE }
|
||||
#define SAVE(REG) { st r27, REG; ADDI_PTR r27, r27, REGSIZE }
|
||||
#define RESTORE(REG) { ld REG, r27; ADDI_PTR r27, r27, REGSIZE }
|
||||
|
||||
.macro dl_resolve, name, profile, framesize
|
||||
.text
|
||||
|
|
@ -86,7 +86,7 @@
|
|||
\name:
|
||||
cfi_startproc
|
||||
{
|
||||
ST sp, lr
|
||||
st sp, lr
|
||||
move r26, sp
|
||||
}
|
||||
{
|
||||
|
|
@ -95,24 +95,24 @@
|
|||
}
|
||||
cfi_def_cfa_offset (\framesize)
|
||||
{
|
||||
ST r27, r26
|
||||
st r27, r26
|
||||
ADDI_PTR r27, r27, FRAME_REGS - FRAME_SP
|
||||
}
|
||||
FOR_EACH_REG(SAVE)
|
||||
{
|
||||
ST r27, lr
|
||||
st r27, lr
|
||||
ADDLI_PTR r27, sp, FRAME_TPNT
|
||||
}
|
||||
cfi_offset (lr, FRAME_LR - \framesize)
|
||||
.if \profile
|
||||
{
|
||||
move r0, r28 /* tpnt value */
|
||||
ST r27, r28
|
||||
st r27, r28
|
||||
ADDI_PTR r27, r27, FRAME_INDEX - FRAME_TPNT
|
||||
}
|
||||
{
|
||||
move r1, r29 /* PLT index */
|
||||
ST r27, r29
|
||||
st r27, r29
|
||||
}
|
||||
{
|
||||
move r2, lr /* retaddr */
|
||||
|
|
@ -124,7 +124,7 @@
|
|||
}
|
||||
ADDLI_PTR r28, sp, FRAME_STACKFRAME
|
||||
LD_PTR r28, r28
|
||||
BGTZ r28, 1f
|
||||
bgtz r28, 1f
|
||||
.else
|
||||
{
|
||||
move r0, r28 /* tpnt value 1 */
|
||||
|
|
@ -141,12 +141,12 @@
|
|||
FOR_EACH_REG(RESTORE)
|
||||
.if \profile
|
||||
ADDLI_PTR r28, sp, FRAME_STACKFRAME
|
||||
LD r28, r28
|
||||
BGTZ r28, 1f
|
||||
ld r28, r28
|
||||
bgtz r28, 1f
|
||||
.endif
|
||||
{
|
||||
/* Restore original user return address. */
|
||||
LD lr, r27
|
||||
ld lr, r27
|
||||
/* Pop off our stack frame. */
|
||||
ADDLI_PTR sp, sp, \framesize
|
||||
}
|
||||
|
|
@ -162,11 +162,11 @@
|
|||
}
|
||||
FOR_EACH_REG(SAVE)
|
||||
{
|
||||
LD r0, r28
|
||||
ld r0, r28
|
||||
ADDI_PTR r28, r28, FRAME_INDEX - FRAME_TPNT
|
||||
}
|
||||
{
|
||||
LD r1, r28
|
||||
ld r1, r28
|
||||
ADDLI_PTR r2, sp, FRAME_REGS
|
||||
}
|
||||
{
|
||||
|
|
@ -179,7 +179,7 @@
|
|||
}
|
||||
FOR_EACH_REG(RESTORE)
|
||||
{
|
||||
LD lr, lr
|
||||
ld lr, lr
|
||||
ADDLI_PTR sp, sp, \framesize
|
||||
}
|
||||
jrp lr
|
||||
|
|
|
|||
|
|
@ -36,11 +36,11 @@ ENTRY(__sigsetjmp)
|
|||
1:
|
||||
move r2, r0
|
||||
|
||||
#define SAVE(r) { ST r2, r ; ADDI_PTR r2, r2, REGSIZE }
|
||||
#define SAVE(r) { st r2, r ; ADDI_PTR r2, r2, REGSIZE }
|
||||
FOR_EACH_CALLEE_SAVED_REG(SAVE)
|
||||
|
||||
mfspr r3, INTERRUPT_CRITICAL_SECTION
|
||||
ST r2, r3
|
||||
st r2, r3
|
||||
j plt(__sigjmp_save)
|
||||
jrp lr /* Keep the backtracer happy. */
|
||||
END(__sigsetjmp)
|
||||
|
|
|
|||
|
|
@ -109,11 +109,11 @@ _start:
|
|||
|
||||
/* Zero out callee space for return address. Unnecessary but free.
|
||||
This is just paranoia to help backtracing not go awry. */
|
||||
ST sp, zero
|
||||
st sp, zero
|
||||
}
|
||||
{
|
||||
/* Zero out our frame pointer for __libc_start_main. */
|
||||
ST r12, zero
|
||||
st r12, zero
|
||||
|
||||
/* Zero out lr to make __libc_start_main the end of backtrace. */
|
||||
move lr, zero
|
||||
|
|
|
|||
|
|
@ -44,32 +44,32 @@ ENTRY (__clone)
|
|||
/* Create a stack frame so we can pass callee-saves to new task. */
|
||||
{
|
||||
move r10, sp
|
||||
ST sp, lr
|
||||
st sp, lr
|
||||
ADDI_PTR sp, sp, -FRAME_SIZE
|
||||
}
|
||||
cfi_offset (lr, 0)
|
||||
cfi_def_cfa_offset (FRAME_SIZE)
|
||||
ADDI_PTR r11, sp, FRAME_SP
|
||||
{
|
||||
ST r11, r10
|
||||
st r11, r10
|
||||
ADDI_PTR r11, sp, FRAME_R30
|
||||
}
|
||||
{
|
||||
ST r11, r30
|
||||
st r11, r30
|
||||
ADDI_PTR r11, sp, FRAME_R31
|
||||
}
|
||||
cfi_offset (r30, FRAME_R30 - FRAME_SIZE)
|
||||
{
|
||||
ST r11, r31
|
||||
st r11, r31
|
||||
ADDI_PTR r11, sp, FRAME_R32
|
||||
}
|
||||
cfi_offset (r31, FRAME_R31 - FRAME_SIZE)
|
||||
ST r11, r32
|
||||
st r11, r32
|
||||
cfi_offset (r32, FRAME_R32 - FRAME_SIZE)
|
||||
|
||||
/* sanity check arguments */
|
||||
BEQZ r0, .Linvalid
|
||||
BEQZ r1, .Linvalid
|
||||
beqz r0, .Linvalid
|
||||
beqz r1, .Linvalid
|
||||
|
||||
/* Make sure child stack is properly aligned, and set up the
|
||||
top frame so that we can call out of it immediately in the
|
||||
|
|
@ -79,7 +79,7 @@ ENTRY (__clone)
|
|||
ADDI_PTR r1, r1, -C_ABI_SAVE_AREA_SIZE
|
||||
andi r1, r1, -C_ABI_SAVE_AREA_SIZE
|
||||
ADDI_PTR r9, r1, REGSIZE /* sp of this frame on entry, i.e. zero */
|
||||
ST r9, zero
|
||||
st r9, zero
|
||||
|
||||
/* We need to switch the argument convention around from
|
||||
libc to kernel:
|
||||
|
|
@ -118,30 +118,30 @@ ENTRY (__clone)
|
|||
moveli TREG_SYSCALL_NR_NAME, __NR_clone
|
||||
}
|
||||
swint1
|
||||
BEQZ r0, .Lthread_start /* If in child task. */
|
||||
beqz r0, .Lthread_start /* If in child task. */
|
||||
|
||||
.Ldone:
|
||||
/* Restore the callee-saved registers and return. */
|
||||
ADDLI_PTR lr, sp, FRAME_SIZE
|
||||
{
|
||||
LD lr, lr
|
||||
ld lr, lr
|
||||
ADDLI_PTR r30, sp, FRAME_R30
|
||||
}
|
||||
{
|
||||
LD r30, r30
|
||||
ld r30, r30
|
||||
ADDLI_PTR r31, sp, FRAME_R31
|
||||
}
|
||||
{
|
||||
LD r31, r31
|
||||
ld r31, r31
|
||||
ADDLI_PTR r32, sp, FRAME_R32
|
||||
}
|
||||
{
|
||||
LD r32, r32
|
||||
ld r32, r32
|
||||
ADDI_PTR sp, sp, FRAME_SIZE
|
||||
}
|
||||
cfi_def_cfa_offset (0)
|
||||
|
||||
BNEZ r1, .Lerror
|
||||
bnez r1, .Lerror
|
||||
jrp lr
|
||||
|
||||
.Lerror:
|
||||
|
|
|
|||
|
|
@ -33,38 +33,38 @@ ENTRY (__getcontext)
|
|||
Save value "1" to uc_flags to later recognize getcontext(). */
|
||||
{ movei r11, 1; ADDI_PTR r10, r0, UC_FLAGS_OFFSET }
|
||||
{ ST_PTR r10, r11; addli r10, r0, UC_REG(30) }
|
||||
{ ST r10, r30; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r31; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r32; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r33; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r34; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r35; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r36; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r37; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r38; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r39; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r40; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r41; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r42; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r43; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r44; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r45; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r46; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r47; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r48; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r49; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r50; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r51; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, r52; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, tp; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, sp; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ST r10, lr; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r30; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r31; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r32; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r33; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r34; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r35; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r36; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r37; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r38; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r39; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r40; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r41; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r42; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r43; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r44; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r45; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r46; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r47; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r48; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r49; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r50; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r51; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r52; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, tp; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, sp; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, lr; ADDI_PTR r10, r10, REGSIZE }
|
||||
lnk r11 /* Point PC at the "jrp lr" instruction. */
|
||||
addli r11, r11, .Lreturn - .
|
||||
{ ST r10, r11; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ st r10, r11; ADDI_PTR r10, r10, REGSIZE }
|
||||
mfspr r11, INTERRUPT_CRITICAL_SECTION
|
||||
{
|
||||
ST r10, r11
|
||||
st r10, r11
|
||||
movei r1, 0
|
||||
}
|
||||
|
||||
|
|
@ -78,7 +78,7 @@ ENTRY (__getcontext)
|
|||
moveli TREG_SYSCALL_NR_NAME, __NR_rt_sigprocmask
|
||||
}
|
||||
swint1
|
||||
BNEZ r1, .Lsyscall_error
|
||||
bnez r1, .Lsyscall_error
|
||||
|
||||
.Lreturn:
|
||||
{
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ ENTRY (__ioctl)
|
|||
moveli TREG_SYSCALL_NR_NAME, __NR_ioctl
|
||||
}
|
||||
swint1
|
||||
BNEZ r1, 0f
|
||||
bnez r1, 0f
|
||||
jrp lr
|
||||
PSEUDO_END (__ioctl)
|
||||
libc_hidden_def (__ioctl)
|
||||
|
|
|
|||
|
|
@ -39,15 +39,15 @@ ENTRY (__setcontext)
|
|||
#endif
|
||||
LD_PTR r10, r0
|
||||
{
|
||||
BEQZ r10, .Lsigreturn
|
||||
beqz r10, .Lsigreturn
|
||||
addi r10, r10, -1 /* Confirm that it has value "1". */
|
||||
}
|
||||
BNEZ r10, .Lbadcontext
|
||||
bnez r10, .Lbadcontext
|
||||
|
||||
/* Save lr and r0 briefly on the stack and set the signal mask:
|
||||
rt_sigprocmask (SIG_SETMASK, &ucp->uc_sigmask, NULL, _NSIG / 8). */
|
||||
{
|
||||
ST sp, lr
|
||||
st sp, lr
|
||||
ADDI_PTR r11, sp, -(2 * REGSIZE)
|
||||
move r10, sp
|
||||
}
|
||||
|
|
@ -55,11 +55,11 @@ ENTRY (__setcontext)
|
|||
cfi_def_cfa_offset (3 * REGSIZE)
|
||||
cfi_offset (lr, 0)
|
||||
{
|
||||
ST r11, r10
|
||||
st r11, r10
|
||||
ADDI_PTR r10, sp, (2 * REGSIZE)
|
||||
}
|
||||
{
|
||||
ST r10, r0
|
||||
st r10, r0
|
||||
ADDLI_PTR r1, r0, UC_SIGMASK_OFFSET
|
||||
}
|
||||
cfi_offset (r0, -REGSIZE)
|
||||
|
|
@ -74,62 +74,62 @@ ENTRY (__setcontext)
|
|||
swint1
|
||||
ADDI_PTR r11, sp, 2 * REGSIZE /* Restore uc_context to r11. */
|
||||
{
|
||||
LD r11, r11
|
||||
ld r11, r11
|
||||
ADDI_PTR sp, sp, 3 * REGSIZE
|
||||
}
|
||||
cfi_def_cfa_offset (0)
|
||||
LD lr, sp
|
||||
ld lr, sp
|
||||
{
|
||||
ADDI_PTR r10, r11, UC_REG(0)
|
||||
BNEZ r1, .Lsyscall_error
|
||||
bnez r1, .Lsyscall_error
|
||||
}
|
||||
|
||||
/* Restore the argument registers; note they will be random
|
||||
unless makecontext() has been called. */
|
||||
{ LD r0, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r1, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r2, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r3, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r4, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r5, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r6, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r7, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r8, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r9, r10; ADDLI_PTR r10, r10, UC_REG(30) - UC_REG(9) }
|
||||
{ ld r0, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r1, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r2, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r3, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r4, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r5, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r6, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r7, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r8, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r9, r10; ADDLI_PTR r10, r10, UC_REG(30) - UC_REG(9) }
|
||||
|
||||
/* Restore the callee-saved GPRs. */
|
||||
{ LD r30, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r31, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r32, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r33, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r34, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r35, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r36, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r37, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r38, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r39, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r40, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r41, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r42, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r43, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r44, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r45, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r46, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r47, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r48, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r49, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r50, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r51, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r52, r10; ADDI_PTR r10, r10, REGSIZE * 2 }
|
||||
{ ld r30, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r31, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r32, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r33, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r34, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r35, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r36, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r37, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r38, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r39, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r40, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r41, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r42, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r43, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r44, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r45, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r46, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r47, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r48, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r49, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r50, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r51, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r52, r10; ADDI_PTR r10, r10, REGSIZE * 2 }
|
||||
/* Skip tp since it must not change for a given thread. */
|
||||
{ LD sp, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD lr, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ LD r11, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld sp, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld lr, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
{ ld r11, r10; ADDI_PTR r10, r10, REGSIZE }
|
||||
|
||||
/* Construct an iret context; we set ICS so we can validly load
|
||||
EX_CONTEXT for iret without being interrupted halfway through. */
|
||||
{
|
||||
LD r12, r10
|
||||
ld r12, r10
|
||||
movei r13, 1
|
||||
}
|
||||
{
|
||||
|
|
@ -157,15 +157,15 @@ ENTRY (__setcontext)
|
|||
cfi_def_cfa_offset (C_ABI_SAVE_AREA_SIZE + SI_MAX_SIZE + UC_SIZE)
|
||||
moveli r2, UC_SIZE / REGSIZE
|
||||
0: {
|
||||
LD r10, r0
|
||||
ld r10, r0
|
||||
ADDI_PTR r0, r0, REGSIZE
|
||||
}
|
||||
{
|
||||
ST r1, r10
|
||||
st r1, r10
|
||||
ADDI_PTR r1, r1, REGSIZE
|
||||
addi r2, r2, -1
|
||||
}
|
||||
BNEZ r2, 0b
|
||||
bnez r2, 0b
|
||||
moveli TREG_SYSCALL_NR_NAME, __NR_rt_sigreturn
|
||||
swint1
|
||||
|
||||
|
|
@ -193,7 +193,7 @@ ENTRY (__startcontext)
|
|||
cfi_undefined (lr)
|
||||
FEEDBACK_ENTER(__startcontext)
|
||||
jalr r31
|
||||
BEQZ r30, 1f
|
||||
beqz r30, 1f
|
||||
{
|
||||
move r0, r30
|
||||
jal __setcontext
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ ENTRY (__swapcontext)
|
|||
FEEDBACK_ENTER(__swapcontext)
|
||||
/* Set up a frame and save r0 and r1. */
|
||||
{
|
||||
ST sp, lr
|
||||
st sp, lr
|
||||
ADDI_PTR r11, sp, -(3 * REGSIZE)
|
||||
move r10, sp
|
||||
}
|
||||
|
|
@ -35,43 +35,43 @@ ENTRY (__swapcontext)
|
|||
cfi_def_cfa_offset (4 * REGSIZE)
|
||||
cfi_offset (lr, 0)
|
||||
{
|
||||
ST r11, r10
|
||||
st r11, r10
|
||||
ADDI_PTR r10, sp, (2 * REGSIZE)
|
||||
}
|
||||
{
|
||||
ST r10, r0
|
||||
st r10, r0
|
||||
ADDI_PTR r10, sp, (3 * REGSIZE)
|
||||
}
|
||||
ST r10, r1
|
||||
st r10, r1
|
||||
|
||||
/* Save the current context. */
|
||||
jal __getcontext
|
||||
|
||||
/* Tear down the frame and restore r0, r1, and lr. */
|
||||
{
|
||||
BNEZ r0, .Lerror
|
||||
bnez r0, .Lerror
|
||||
ADDI_PTR r1, sp, 3 * REGSIZE
|
||||
}
|
||||
{
|
||||
LD r1, r1
|
||||
ld r1, r1
|
||||
ADDI_PTR r0, sp, 2 * REGSIZE
|
||||
}
|
||||
{
|
||||
LD r0, r0
|
||||
ld r0, r0
|
||||
ADDI_PTR sp, sp, 4 * REGSIZE
|
||||
}
|
||||
cfi_def_cfa_offset (0)
|
||||
{
|
||||
LD lr, sp
|
||||
ld lr, sp
|
||||
ADDLI_PTR r10, r0, UC_REG(54)
|
||||
}
|
||||
|
||||
/* Update the stored sp and lr. */
|
||||
{
|
||||
ST r10, sp
|
||||
st r10, sp
|
||||
ADDLI_PTR r10, r0, UC_REG(55)
|
||||
}
|
||||
ST r10, lr
|
||||
st r10, lr
|
||||
|
||||
/* Tail-call setcontext to finish up. */
|
||||
{
|
||||
|
|
@ -82,7 +82,7 @@ ENTRY (__swapcontext)
|
|||
.Lerror:
|
||||
ADDI_PTR sp, sp, 4 * REGSIZE
|
||||
cfi_def_cfa_offset (0)
|
||||
LD lr, sp
|
||||
ld lr, sp
|
||||
jrp lr
|
||||
END (__swapcontext)
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,6 @@ ENTRY (syscall)
|
|||
{ move r3, r4; move r4, r5 }
|
||||
{ move r5, r6; move r6, r7 }
|
||||
swint1
|
||||
BNEZ r1, 0f
|
||||
bnez r1, 0f
|
||||
jrp lr
|
||||
PSEUDO_END (syscall)
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ ENTRY (__vfork)
|
|||
moveli TREG_SYSCALL_NR_NAME, __NR_clone
|
||||
swint1
|
||||
|
||||
BNEZ r1, 0f
|
||||
bnez r1, 0f
|
||||
jrp lr
|
||||
PSEUDO_END (__vfork)
|
||||
libc_hidden_def (__vfork)
|
||||
|
|
|
|||
Loading…
Reference in New Issue