diff --git a/ChangeLog b/ChangeLog
index dd40484e70..3e8df42d31 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2015-03-31  H.J. Lu  <hongjiu.lu@intel.com>
+
+	[BZ #18185]
+	* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads
+	sharing L2 cache to 2 for Silvermont/Knights Landing.
+
 2015-03-31  H.J. Lu  <hongjiu.lu@intel.com>
 
 	[BZ #17711]
diff --git a/NEWS b/NEWS
index b66c1b1daa..d2651b3a8d 100644
--- a/NEWS
+++ b/NEWS
@@ -15,7 +15,7 @@ Version 2.22
   17932, 17944, 17949, 17964, 17965, 17967, 17969, 17978, 17987, 17991,
   17996, 17998, 17999, 18019, 18020, 18029, 18030, 18032, 18036, 18038,
   18039, 18042, 18043, 18046, 18047, 18068, 18080, 18093, 18100, 18104,
-  18110, 18111, 18128, 18138.
+  18110, 18111, 18128, 18138, 18185.
 
 * A powerpc and powerpc64 optimization for TLS, similar to TLS descriptors
   for LD and GD on x86 and x86-64, has been implemented.  You will need
diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c
index f1cbf50957..b99fb9a762 100644
--- a/sysdeps/x86_64/cacheinfo.c
+++ b/sysdeps/x86_64/cacheinfo.c
@@ -585,6 +585,10 @@ init_cacheinfo (void)
       __cpuid (1, eax, ebx_1, ecx, edx);
 #endif
 
+      unsigned int family = (eax >> 8) & 0x0f;
+      unsigned int model = (eax >> 4) & 0x0f;
+      unsigned int extended_model = (eax >> 12) & 0xf0;
+
 #ifndef DISABLE_PREFERRED_MEMORY_INSTRUCTION
       /* Intel prefers SSSE3 instructions for memory/string routines
 	 if they are available.  */
@@ -647,6 +651,25 @@ init_cacheinfo (void)
 		}
 	    }
 	  threads += 1;
+	  if (threads > 2 && level == 2 && family == 6)
+	    {
+	      model += extended_model;
+	      switch (model)
+		{
+		case 0x57:
+		  /* Knights Landing has L2 cache shared by 2 cores.  */
+		case 0x37:
+		case 0x4a:
+		case 0x4d:
+		case 0x5a:
+		case 0x5d:
+		  /* Silvermont has L2 cache shared by 2 cores.  */
+		  threads = 2;
+		  break;
+		default:
+		  break;
+		}
+	    }
 	}
       else
 	{