S/390: Fix rt_sigprocmask syscall invocation in get/set/swapcontext.
This commit is contained in:
Andreas Krebbel
parent
cfb6382a4f
commit
c3e94a9533
11
ChangeLog
11
ChangeLog
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@ -1,3 +1,14 @@
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2013-03-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* sysdeps/unix/sysv/linux/s390/s390-32/getcontext.S: Set the
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fourth parameter needed for rt_sigprocmask syscall.
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* sysdeps/unix/sysv/linux/s390/s390-32/setcontext.S:
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* sysdeps/unix/sysv/linux/s390/s390-32/swapcontext.S: Likewise.
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* sysdeps/unix/sysv/linux/s390/s390-64/getcontext.S: Likewise.
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* sysdeps/unix/sysv/linux/s390/s390-64/setcontext.S: Likewise.
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* sysdeps/unix/sysv/linux/s390/s390-64/swapcontext.S: Likewise.
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* sysdeps/unix/sysv/linux/s390/ucontext_i.sym: Define _NSIG8.
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2013-03-04 Joseph Myers <joseph@codesourcery.com>
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[BZ #13550]
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@ -31,41 +31,42 @@
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other than the PRESERVED state. */
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ENTRY(__getcontext)
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lr %r5,%r2
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lr %r1,%r2
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/* sigprocmask (SIG_BLOCK, NULL, &sc->sc_mask). */
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la %r2,SIG_BLOCK
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slr %r3,%r3
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la %r4,SC_MASK(%r5)
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la %r4,SC_MASK(%r1)
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lhi %r5,_NSIG8
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svc SYS_ify(rt_sigprocmask)
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/* Store fpu context. */
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stfpc SC_FPC(%r5)
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std %f0,SC_FPRS(%r5)
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std %f1,SC_FPRS+8(%r5)
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std %f2,SC_FPRS+16(%r5)
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std %f3,SC_FPRS+24(%r5)
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std %f4,SC_FPRS+32(%r5)
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std %f5,SC_FPRS+40(%r5)
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std %f6,SC_FPRS+48(%r5)
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std %f7,SC_FPRS+56(%r5)
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std %f8,SC_FPRS+64(%r5)
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std %f9,SC_FPRS+72(%r5)
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std %f10,SC_FPRS+80(%r5)
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std %f11,SC_FPRS+88(%r5)
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std %f12,SC_FPRS+96(%r5)
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std %f13,SC_FPRS+104(%r5)
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std %f14,SC_FPRS+112(%r5)
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std %f15,SC_FPRS+120(%r5)
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stfpc SC_FPC(%r1)
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std %f0,SC_FPRS(%r1)
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std %f1,SC_FPRS+8(%r1)
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std %f2,SC_FPRS+16(%r1)
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std %f3,SC_FPRS+24(%r1)
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std %f4,SC_FPRS+32(%r1)
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std %f5,SC_FPRS+40(%r1)
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std %f6,SC_FPRS+48(%r1)
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std %f7,SC_FPRS+56(%r1)
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std %f8,SC_FPRS+64(%r1)
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std %f9,SC_FPRS+72(%r1)
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std %f10,SC_FPRS+80(%r1)
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std %f11,SC_FPRS+88(%r1)
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std %f12,SC_FPRS+96(%r1)
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std %f13,SC_FPRS+104(%r1)
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std %f14,SC_FPRS+112(%r1)
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std %f15,SC_FPRS+120(%r1)
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/* Set __getcontext return value to 0. */
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slr %r2,%r2
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/* Store access registers. */
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stam %a0,%a15,SC_ACRS(%r5)
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stam %a0,%a15,SC_ACRS(%r1)
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/* Store general purpose registers. */
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stm %r0,%r15,SC_GPRS(%r5)
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stm %r0,%r15,SC_GPRS(%r1)
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/* Return. */
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br %r14
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@ -31,38 +31,39 @@
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other than the PRESERVED state. */
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ENTRY(__setcontext)
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lr %r5,%r2
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lr %r1,%r2
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/* sigprocmask (SIG_SETMASK, &sc->sc_mask, NULL). */
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la %r2,SIG_BLOCK
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la %r3,SC_MASK(%r5)
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la %r3,SC_MASK(%r1)
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slr %r4,%r4
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lhi %r5,_NSIG8
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svc SYS_ify(rt_sigprocmask)
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/* Load fpu context. */
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lfpc SC_FPC(%r5)
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ld %f0,SC_FPRS(%r5)
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ld %f1,SC_FPRS+8(%r5)
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ld %f2,SC_FPRS+16(%r5)
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ld %f3,SC_FPRS+24(%r5)
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ld %f4,SC_FPRS+32(%r5)
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ld %f5,SC_FPRS+40(%r5)
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ld %f6,SC_FPRS+48(%r5)
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ld %f7,SC_FPRS+56(%r5)
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ld %f8,SC_FPRS+64(%r5)
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ld %f9,SC_FPRS+72(%r5)
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ld %f10,SC_FPRS+80(%r5)
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ld %f11,SC_FPRS+88(%r5)
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ld %f12,SC_FPRS+96(%r5)
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ld %f13,SC_FPRS+104(%r5)
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ld %f14,SC_FPRS+112(%r5)
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ld %f15,SC_FPRS+120(%r5)
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lfpc SC_FPC(%r1)
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ld %f0,SC_FPRS(%r1)
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ld %f1,SC_FPRS+8(%r1)
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ld %f2,SC_FPRS+16(%r1)
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ld %f3,SC_FPRS+24(%r1)
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ld %f4,SC_FPRS+32(%r1)
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ld %f5,SC_FPRS+40(%r1)
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ld %f6,SC_FPRS+48(%r1)
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ld %f7,SC_FPRS+56(%r1)
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ld %f8,SC_FPRS+64(%r1)
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ld %f9,SC_FPRS+72(%r1)
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ld %f10,SC_FPRS+80(%r1)
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ld %f11,SC_FPRS+88(%r1)
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ld %f12,SC_FPRS+96(%r1)
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ld %f13,SC_FPRS+104(%r1)
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ld %f14,SC_FPRS+112(%r1)
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ld %f15,SC_FPRS+120(%r1)
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/* Don't touch %a0, used for thread purposes. */
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lam %a1,%a15,SC_ACRS+4(%r5)
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lam %a1,%a15,SC_ACRS+4(%r1)
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/* Load general purpose registers. */
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lm %r0,%r15,SC_GPRS(%r5)
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lm %r0,%r15,SC_GPRS(%r1)
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/* Return. */
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br %r14
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@ -34,12 +34,13 @@
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ENTRY(__swapcontext)
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lr %r1,%r2
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lr %r5,%r3
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lr %r0,%r3
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/* sigprocmask (SIG_BLOCK, NULL, &sc->sc_mask). */
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la %r2,SIG_BLOCK
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slr %r3,%r3
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la %r4,SC_MASK(%r1)
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lhi %r5,_NSIG8
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svc SYS_ify(rt_sigprocmask)
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/* Store fpu context. */
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@ -72,11 +73,14 @@ ENTRY(__swapcontext)
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/* sigprocmask (SIG_SETMASK, &sc->sc_mask, NULL). */
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la %r2,SIG_BLOCK
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lr %r5,%r0
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la %r3,SC_MASK(%r5)
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slr %r4,%r4
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lhi %r5,_NSIG8
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svc SYS_ify(rt_sigprocmask)
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/* Load fpu context. */
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lr %r5,%r0
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lfpc SC_FPC(%r5)
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ld %f0,SC_FPRS(%r5)
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ld %f1,SC_FPRS+8(%r5)
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@ -31,41 +31,42 @@
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other than the PRESERVED state. */
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ENTRY(__getcontext)
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lgr %r5,%r2
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lgr %r1,%r2
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/* sigprocmask (SIG_BLOCK, NULL, &sc->sc_mask). */
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la %r2,SIG_BLOCK
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slgr %r3,%r3
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la %r4,SC_MASK(%r5)
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la %r4,SC_MASK(%r1)
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lghi %r5,_NSIG8
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svc SYS_ify(rt_sigprocmask)
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/* Store fpu context. */
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stfpc SC_FPC(%r5)
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std %f0,SC_FPRS(%r5)
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std %f1,SC_FPRS+8(%r5)
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std %f2,SC_FPRS+16(%r5)
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std %f3,SC_FPRS+24(%r5)
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std %f4,SC_FPRS+32(%r5)
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std %f5,SC_FPRS+40(%r5)
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std %f6,SC_FPRS+48(%r5)
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std %f7,SC_FPRS+56(%r5)
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std %f8,SC_FPRS+64(%r5)
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std %f9,SC_FPRS+72(%r5)
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std %f10,SC_FPRS+80(%r5)
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std %f11,SC_FPRS+88(%r5)
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std %f12,SC_FPRS+96(%r5)
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std %f13,SC_FPRS+104(%r5)
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std %f14,SC_FPRS+112(%r5)
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std %f15,SC_FPRS+120(%r5)
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stfpc SC_FPC(%r1)
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std %f0,SC_FPRS(%r1)
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std %f1,SC_FPRS+8(%r1)
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std %f2,SC_FPRS+16(%r1)
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std %f3,SC_FPRS+24(%r1)
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std %f4,SC_FPRS+32(%r1)
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std %f5,SC_FPRS+40(%r1)
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std %f6,SC_FPRS+48(%r1)
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std %f7,SC_FPRS+56(%r1)
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std %f8,SC_FPRS+64(%r1)
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std %f9,SC_FPRS+72(%r1)
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std %f10,SC_FPRS+80(%r1)
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std %f11,SC_FPRS+88(%r1)
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std %f12,SC_FPRS+96(%r1)
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std %f13,SC_FPRS+104(%r1)
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std %f14,SC_FPRS+112(%r1)
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std %f15,SC_FPRS+120(%r1)
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/* Set __getcontext return value to 0. */
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slgr %r2,%r2
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/* Store access registers. */
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stam %a0,%a15,SC_ACRS(%r5)
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stam %a0,%a15,SC_ACRS(%r1)
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/* Store general purpose registers. */
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stmg %r0,%r15,SC_GPRS(%r5)
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stmg %r0,%r15,SC_GPRS(%r1)
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/* Return. */
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br %r14
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@ -31,38 +31,39 @@
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other than the PRESERVED state. */
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ENTRY(__setcontext)
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lgr %r5,%r2
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lgr %r1,%r2
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/* sigprocmask (SIG_SETMASK, &sc->sc_mask, NULL). */
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la %r2,SIG_BLOCK
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la %r3,SC_MASK(%r5)
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la %r3,SC_MASK(%r1)
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slgr %r4,%r4
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lghi %r5,_NSIG8
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svc SYS_ify(rt_sigprocmask)
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/* Load fpu context. */
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lfpc SC_FPC(%r5)
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ld %f0,SC_FPRS(%r5)
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ld %f1,SC_FPRS+8(%r5)
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ld %f2,SC_FPRS+16(%r5)
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ld %f3,SC_FPRS+24(%r5)
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ld %f4,SC_FPRS+32(%r5)
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ld %f5,SC_FPRS+40(%r5)
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ld %f6,SC_FPRS+48(%r5)
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ld %f7,SC_FPRS+56(%r5)
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ld %f8,SC_FPRS+64(%r5)
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ld %f9,SC_FPRS+72(%r5)
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ld %f10,SC_FPRS+80(%r5)
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ld %f11,SC_FPRS+88(%r5)
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ld %f12,SC_FPRS+96(%r5)
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ld %f13,SC_FPRS+104(%r5)
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ld %f14,SC_FPRS+112(%r5)
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ld %f15,SC_FPRS+120(%r5)
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lfpc SC_FPC(%r1)
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ld %f0,SC_FPRS(%r1)
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ld %f1,SC_FPRS+8(%r1)
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ld %f2,SC_FPRS+16(%r1)
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ld %f3,SC_FPRS+24(%r1)
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ld %f4,SC_FPRS+32(%r1)
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ld %f5,SC_FPRS+40(%r1)
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ld %f6,SC_FPRS+48(%r1)
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ld %f7,SC_FPRS+56(%r1)
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ld %f8,SC_FPRS+64(%r1)
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ld %f9,SC_FPRS+72(%r1)
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ld %f10,SC_FPRS+80(%r1)
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ld %f11,SC_FPRS+88(%r1)
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ld %f12,SC_FPRS+96(%r1)
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ld %f13,SC_FPRS+104(%r1)
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ld %f14,SC_FPRS+112(%r1)
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ld %f15,SC_FPRS+120(%r1)
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/* Don't touch %a0 and %a1, used for thread purposes. */
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lam %a2,%a15,SC_ACRS+8(%r5)
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lam %a2,%a15,SC_ACRS+8(%r1)
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/* Load general purpose registers. */
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lmg %r0,%r15,SC_GPRS(%r5)
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lmg %r0,%r15,SC_GPRS(%r1)
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/* Return. */
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br %r14
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@ -34,12 +34,13 @@
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ENTRY(__swapcontext)
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lgr %r1,%r2
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lgr %r5,%r3
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lgr %r0,%r3
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/* sigprocmask (SIG_BLOCK, NULL, &sc->sc_mask). */
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la %r2,SIG_BLOCK
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slgr %r3,%r3
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la %r4,SC_MASK(%r1)
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lghi %r5,_NSIG8
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svc SYS_ify(rt_sigprocmask)
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/* Store fpu context. */
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@ -72,11 +73,14 @@ ENTRY(__swapcontext)
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/* sigprocmask (SIG_SETMASK, &sc->sc_mask, NULL). */
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la %r2,SIG_BLOCK
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lgr %r5,%r0
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la %r3,SC_MASK(%r5)
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lghi %r5,_NSIG8
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slgr %r4,%r4
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svc SYS_ify(rt_sigprocmask)
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/* Load fpu context. */
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lgr %r5,%r0
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lfpc SC_FPC(%r5)
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ld %f0,SC_FPRS(%r5)
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ld %f1,SC_FPRS+8(%r5)
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@ -8,6 +8,8 @@ SIG_BLOCK
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SIG_UNBLOCK
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SIG_SETMASK
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_NSIG8 (_NSIG / 8)
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#define ucontext(member) offsetof (ucontext_t, member)
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#define mcontext(member) ucontext (uc_mcontext.member)
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