Update longlong.h from GCC
This commit is contained in:
Andreas Schwab
Ulrich Drepper
parent
f50ef8f1ef
commit
def7fbd6c6
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@ -1,3 +1,7 @@
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2011-05-20 Andreas Schwab <schwab@redhat.com>
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* stdlib/longlong.h: Update from GCC.
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2011-05-23 Andreas Schwab <schwab@redhat.com>
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* sysdeps/unix/sysv/linux/ia64/sysconf.c (HAS_CPUCLOCK): Add
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@ -1,6 +1,7 @@
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/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
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Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
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2002, 2003, 2004, 2005, 2006, 2009 Free Software Foundation, Inc.
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2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
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Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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@ -9,6 +10,15 @@
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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In addition to the permissions in the GNU Lesser General Public
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License, the Free Software Foundation gives you unlimited
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permission to link the compiled version of this file into
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combinations with other programs, and to distribute those
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combinations without any restriction coming from the use of this
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file. (The Lesser General Public License restrictions do apply in
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other respects; for example, they cover modification of the file,
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and distribution when not linked into a combine executable.)
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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@ -16,8 +26,8 @@
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA. */
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/* You have to define the following before including this file:
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@ -45,6 +55,11 @@
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#define UDWtype UDItype
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#endif
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/* Used in glibc only. */
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#ifndef attribute_hidden
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#define attribute_hidden
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#endif
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extern const UQItype __clz_tab[256] attribute_hidden;
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/* Define auxiliary asm macros.
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@ -303,6 +318,7 @@ UDItype __umulsidi3 (USItype, USItype);
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#endif
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#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
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#if !defined (__zarch__)
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#define smul_ppmm(xh, xl, m0, m1) \
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do { \
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union {DItype __ll; \
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@ -324,6 +340,28 @@ UDItype __umulsidi3 (USItype, USItype);
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: "0" (__x.__ll), "r" (d)); \
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(q) = __x.__i.__l; (r) = __x.__i.__h; \
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} while (0)
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#else
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#define smul_ppmm(xh, xl, m0, m1) \
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do { \
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register SItype r0 __asm__ ("0"); \
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register SItype r1 __asm__ ("1") = m0; \
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\
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__asm__ ("mr\t%%r0,%3" \
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: "=r" (r0), "=r" (r1) \
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: "r" (r1), "r" (m1)); \
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(xh) = r1; (xl) = r0; \
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} while (0)
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#define sdiv_qrnnd(q, r, n1, n0, d) \
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do { \
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register SItype r0 __asm__ ("0") = n0; \
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register SItype r1 __asm__ ("1") = n1; \
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\
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__asm__ ("dr\t%%r0,%3" \
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: "=r" (r0), "=r" (r1) \
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: "r" (r0), "r" (r1), "r" (d)); \
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(q) = r0; (r) = r1; \
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} while (0)
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#endif /* __zarch__ */
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#endif
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#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
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@ -417,6 +455,55 @@ UDItype __umulsidi3 (USItype, USItype);
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__w; })
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#endif /* __i960__ */
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#if defined (__ia64) && W_TYPE_SIZE == 64
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/* This form encourages gcc (pre-release 3.4 at least) to emit predicated
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"sub r=r,r" and "sub r=r,r,1", giving a 2 cycle latency. The generic
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code using "al<bl" arithmetically comes out making an actual 0 or 1 in a
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register, which takes an extra cycle. */
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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do { \
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UWtype __x; \
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__x = (al) - (bl); \
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if ((al) < (bl)) \
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(sh) = (ah) - (bh) - 1; \
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else \
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(sh) = (ah) - (bh); \
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(sl) = __x; \
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} while (0)
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/* Do both product parts in assembly, since that gives better code with
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all gcc versions. Some callers will just use the upper part, and in
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that situation we waste an instruction, but not any cycles. */
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#define umul_ppmm(ph, pl, m0, m1) \
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__asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0" \
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: "=&f" (ph), "=f" (pl) \
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: "f" (m0), "f" (m1))
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#define count_leading_zeros(count, x) \
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do { \
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UWtype _x = (x), _y, _a, _c; \
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__asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x)); \
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__asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y)); \
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_c = (_a - 1) << 3; \
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_x >>= _c; \
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if (_x >= 1 << 4) \
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_x >>= 4, _c += 4; \
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if (_x >= 1 << 2) \
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_x >>= 2, _c += 2; \
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_c += _x >> 1; \
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(count) = W_TYPE_SIZE - 1 - _c; \
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} while (0)
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/* similar to what gcc does for __builtin_ffs, but 0 based rather than 1
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based, and we don't need a special case for x==0 here */
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#define count_trailing_zeros(count, x) \
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do { \
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UWtype __ctz_x = (x); \
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__asm__ ("popcnt %0 = %1" \
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: "=r" (count) \
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: "r" ((__ctz_x-1) & ~__ctz_x)); \
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} while (0)
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#define UMUL_TIME 14
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#endif
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#if defined (__M32R__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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/* The cmp clears the condition bit. */ \
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@ -631,6 +718,43 @@ UDItype __umulsidi3 (USItype, USItype);
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#endif /* __mc88110__ */
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#endif /* __m88000__ */
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#if defined (__mn10300__)
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# if defined (__AM33__)
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# define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
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# define umul_ppmm(w1, w0, u, v) \
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asm("mulu %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
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# define smul_ppmm(w1, w0, u, v) \
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asm("mul %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
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# else
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# define umul_ppmm(w1, w0, u, v) \
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asm("nop; nop; mulu %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
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# define smul_ppmm(w1, w0, u, v) \
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asm("nop; nop; mul %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
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# endif
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# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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do { \
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DWunion __s, __a, __b; \
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__a.s.low = (al); __a.s.high = (ah); \
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__b.s.low = (bl); __b.s.high = (bh); \
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__s.ll = __a.ll + __b.ll; \
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(sl) = __s.s.low; (sh) = __s.s.high; \
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} while (0)
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# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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do { \
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DWunion __s, __a, __b; \
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__a.s.low = (al); __a.s.high = (ah); \
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__b.s.low = (bl); __b.s.high = (bh); \
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__s.ll = __a.ll - __b.ll; \
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(sl) = __s.s.low; (sh) = __s.s.high; \
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} while (0)
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# define udiv_qrnnd(q, r, nh, nl, d) \
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asm("divu %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
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# define sdiv_qrnnd(q, r, nh, nl, d) \
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asm("div %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
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# define UMUL_TIME 3
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# define UDIV_TIME 38
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#endif
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#if defined (__mips__) && W_TYPE_SIZE == 32
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#define umul_ppmm(w1, w0, u, v) \
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do { \
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@ -926,8 +1050,7 @@ UDItype __umulsidi3 (USItype, USItype);
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("clrt;subc %5,%1; subc %4,%0" \
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: "=r" (sh), "=r" (sl) \
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: "0" (ah), "1" (al), "r" (bh), "r" (bl) \
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: "t")
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: "0" (ah), "1" (al), "r" (bh), "r" (bl) : "t")
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#endif /* __sh__ */
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@ -1261,6 +1384,28 @@ UDItype __umulsidi3 (USItype, USItype);
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#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
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#endif /* __xtensa__ */
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#if defined xstormy16
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extern UHItype __stormy16_count_leading_zeros (UHItype);
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#define count_leading_zeros(count, x) \
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do \
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{ \
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UHItype size; \
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\
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/* We assume that W_TYPE_SIZE is a multiple of 16... */ \
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for ((count) = 0, size = W_TYPE_SIZE; size; size -= 16) \
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{ \
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UHItype c; \
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\
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c = __clzhi2 ((x) >> (size - 16)); \
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(count) += c; \
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if (c != 16) \
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break; \
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} \
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} \
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while (0)
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#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
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#endif
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#if defined (__z8000__) && W_TYPE_SIZE == 16
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
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