S390: Use cu24 instruction for converting from utf16 to utf32.
This patch adds an ifunc variant to use the cu instruction on arch12 CPUs.
This new ifunc variant can be built if binutils support z13 vector
instructions. At runtime, HWCAP_S390_VXE decides if we can use the
cu24 instruction.
ChangeLog:
* sysdeps/s390/utf16-utf32-z9.c (__from_utf16_loop_vx_cu):
Use vector and cu24 instruction.
* sysdeps/s390/multiarch/utf16-utf32-z9.c:
Add __from_utf16_loop_vx_cu in ifunc resolver.
This commit is contained in:
Stefan Liebler
parent
593e4da186
commit
f0137ff31d
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@ -1,3 +1,8 @@
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2017-06-27 Stefan Liebler <stli@linux.vnet.ibm.com>
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* sysdeps/s390/utf16-utf32-z9.c (__from_utf16_loop_vx_cu):
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Use vector and cu24 instruction.
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2017-06-27 Stefan Liebler <stli@linux.vnet.ibm.com>
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* sysdeps/s390/utf16-utf32-z9.c (__to_utf16_loop_vx_cu):
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@ -32,9 +32,11 @@ strong_alias (SINGLE_NAME (TO_LOOP_DEFAULT), SINGLE_NAME (TO_LOOP))
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/* Generate ifunc'ed loop functions for FROM/TO_LOOP. */
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s390_libc_ifunc_expr (FROM_LOOP_DEFAULT, FROM_LOOP,
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(HAVE_FROM_VX && (hwcap & HWCAP_S390_VX))
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? FROM_LOOP_VX
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: FROM_LOOP_DEFAULT);
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(HAVE_FROM_VX_CU && (hwcap & HWCAP_S390_VXE))
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? FROM_LOOP_VX_CU
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: (HAVE_FROM_VX && (hwcap & HWCAP_S390_VX))
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? FROM_LOOP_VX
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: FROM_LOOP_DEFAULT);
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s390_libc_ifunc_expr (TO_LOOP_DEFAULT, TO_LOOP,
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(HAVE_TO_VX_CU && (hwcap & HWCAP_S390_VXE))
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@ -39,10 +39,12 @@
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#if defined HAVE_S390_VX_ASM_SUPPORT && defined USE_MULTIARCH
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# define HAVE_FROM_VX 1
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# define HAVE_FROM_VX_CU 1
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# define HAVE_TO_VX 1
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# define HAVE_TO_VX_CU 1
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#else
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# define HAVE_FROM_VX 0
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# define HAVE_FROM_VX_CU 0
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# define HAVE_TO_VX 0
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# define HAVE_TO_VX_CU 0
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#endif
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@ -383,7 +385,6 @@ gconv_end (struct __gconv_step *data)
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STANDARD_FROM_LOOP_ERR_HANDLER (2); \
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}
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/* Generate loop-function with hardware vector instructions. */
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# define MIN_NEEDED_INPUT MIN_NEEDED_FROM
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# define MAX_NEEDED_INPUT MAX_NEEDED_FROM
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@ -397,6 +398,116 @@ gconv_end (struct __gconv_step *data)
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# define FROM_LOOP_VX NULL
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#endif /* HAVE_FROM_VX != 1 */
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#if HAVE_FROM_VX_CU == 1
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#define BODY_FROM_VX_CU \
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{ \
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register const unsigned char* pInput asm ("8") = inptr; \
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register size_t inlen asm ("9") = inend - inptr; \
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register unsigned char* pOutput asm ("10") = outptr; \
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register size_t outlen asm ("11") = outend - outptr; \
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unsigned long tmp, tmp2, tmp3; \
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asm volatile (".machine push\n\t" \
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".machine \"z13\"\n\t" \
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".machinemode \"zarch_nohighgprs\"\n\t" \
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/* Setup to check for surrogates. */ \
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" larl %[R_TMP],9f\n\t" \
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" vlm %%v30,%%v31,0(%[R_TMP])\n\t" \
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CONVERT_32BIT_SIZE_T ([R_INLEN]) \
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CONVERT_32BIT_SIZE_T ([R_OUTLEN]) \
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/* Loop which handles UTF-16 chars <0xd800, >0xdfff. */ \
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"0: clgijl %[R_INLEN],16,20f\n\t" \
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" clgijl %[R_OUTLEN],32,20f\n\t" \
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"1: vl %%v16,0(%[R_IN])\n\t" \
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/* Check for surrogate chars. */ \
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" vstrchs %%v19,%%v16,%%v30,%%v31\n\t" \
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" jno 10f\n\t" \
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/* Enlarge to UTF-32. */ \
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" vuplhh %%v17,%%v16\n\t" \
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" la %[R_IN],16(%[R_IN])\n\t" \
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" vupllh %%v18,%%v16\n\t" \
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" aghi %[R_INLEN],-16\n\t" \
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/* Store 32 bytes to buf_out. */ \
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" vstm %%v17,%%v18,0(%[R_OUT])\n\t" \
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" aghi %[R_OUTLEN],-32\n\t" \
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" la %[R_OUT],32(%[R_OUT])\n\t" \
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" clgijl %[R_INLEN],16,20f\n\t" \
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" clgijl %[R_OUTLEN],32,20f\n\t" \
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" j 1b\n\t" \
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/* Setup to check for ch >= 0xd800 && ch <= 0xdfff. (v30, v31) */ \
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"9: .short 0xd800,0xdfff,0x0,0x0,0x0,0x0,0x0,0x0\n\t" \
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" .short 0xa000,0xc000,0x0,0x0,0x0,0x0,0x0,0x0\n\t" \
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/* At least one uint16_t is in range of surrogates. \
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Store the preceding chars. */ \
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"10: vlgvb %[R_TMP],%%v19,7\n\t" \
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" vuplhh %%v17,%%v16\n\t" \
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" sllg %[R_TMP3],%[R_TMP],1\n\t" /* Number of out bytes. */ \
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" ahik %[R_TMP2],%[R_TMP3],-1\n\t" /* Highest index to store. */ \
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" jl 20f\n\t" \
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" vstl %%v17,%[R_TMP2],0(%[R_OUT])\n\t" \
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" vupllh %%v18,%%v16\n\t" \
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" ahi %[R_TMP2],-16\n\t" \
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" jl 11f\n\t" \
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" vstl %%v18,%[R_TMP2],16(%[R_OUT])\n\t" \
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"11: \n\t" /* Update pointers. */ \
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" la %[R_IN],0(%[R_TMP],%[R_IN])\n\t" \
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" slgr %[R_INLEN],%[R_TMP]\n\t" \
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" la %[R_OUT],0(%[R_TMP3],%[R_OUT])\n\t" \
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" slgr %[R_OUTLEN],%[R_TMP3]\n\t" \
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/* Handles UTF16 surrogates with convert instruction. */ \
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"20: cu24 %[R_OUT],%[R_IN],1\n\t" \
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" jo 0b\n\t" /* Try vector implemenation again. */ \
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" lochil %[R_RES],%[RES_OUT_FULL]\n\t" /* cc == 1. */ \
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" lochih %[R_RES],%[RES_IN_ILL]\n\t" /* cc == 2. */ \
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".machine pop" \
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: /* outputs */ [R_IN] "+a" (pInput) \
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, [R_INLEN] "+d" (inlen), [R_OUT] "+a" (pOutput) \
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, [R_OUTLEN] "+d" (outlen), [R_TMP] "=a" (tmp) \
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, [R_TMP2] "=d" (tmp2), [R_TMP3] "=a" (tmp3) \
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, [R_RES] "+d" (result) \
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: /* inputs */ \
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[RES_OUT_FULL] "i" (__GCONV_FULL_OUTPUT) \
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, [RES_IN_ILL] "i" (__GCONV_ILLEGAL_INPUT) \
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: /* clobber list */ "memory", "cc" \
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ASM_CLOBBER_VR ("v16") ASM_CLOBBER_VR ("v17") \
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ASM_CLOBBER_VR ("v18") ASM_CLOBBER_VR ("v19") \
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ASM_CLOBBER_VR ("v30") ASM_CLOBBER_VR ("v31") \
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); \
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inptr = pInput; \
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outptr = pOutput; \
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\
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if (__glibc_likely (inlen == 0) \
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|| result == __GCONV_FULL_OUTPUT) \
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break; \
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if (inlen == 1) \
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{ \
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/* Input does not contain a complete utf16 character. */ \
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result = __GCONV_INCOMPLETE_INPUT; \
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break; \
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} \
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else if (result != __GCONV_ILLEGAL_INPUT) \
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{ \
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/* Input is >= 2 and < 4 bytes (as cu24 would have processed \
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a possible next utf16 character) and not illegal. \
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=> we have a single high surrogate at end of input. */ \
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result = __GCONV_INCOMPLETE_INPUT; \
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break; \
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} \
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\
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STANDARD_FROM_LOOP_ERR_HANDLER (2); \
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}
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/* Generate loop-function with hardware vector and utf-convert instructions. */
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# define MIN_NEEDED_INPUT MIN_NEEDED_FROM
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# define MAX_NEEDED_INPUT MAX_NEEDED_FROM
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# define MIN_NEEDED_OUTPUT MIN_NEEDED_TO
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# define FROM_LOOP_VX_CU __from_utf16_loop_vx_cu
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# define LOOPFCT FROM_LOOP_VX_CU
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# define LOOP_NEED_FLAGS
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# define BODY BODY_FROM_VX_CU
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# include <iconv/loop.c>
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#else
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# define FROM_LOOP_VX_CU NULL
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#endif /* HAVE_FROM_VX_CU != 1 */
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/* Conversion from UTF-32 internal/BE to UTF-16. */
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