Commit Graph

464 Commits

Author SHA1 Message Date
Steve Ellcey 5b04bb073c 2013-09-19 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/fpu_control.h (_FPU_RC_MASK): New.
2013-09-23 09:34:15 -07:00
Steve Ellcey 2487f2e6a5 2013-09-23 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/fpu_control.h (comments): Add capitalization and
	periods to match GNU standard.
2013-09-23 09:29:58 -07:00
Carlos O'Donell c61b4d41c9 BZ #15754: CVE-2013-4788
The pointer guard used for pointer mangling was not initialized for
static applications resulting in the security feature being disabled.
The pointer guard is now correctly initialized to a random value for
static applications. Existing static applications need to be
recompiled to take advantage of the fix.

The test tst-ptrguard1-static and tst-ptrguard1 add regression
coverage to ensure the pointer guards are sufficiently random
and initialized to a default value.
2013-09-23 00:52:09 -04:00
Andreas Schwab 5bb43a4319 Make __ffs hidden 2013-09-20 21:25:31 +02:00
Steve Ellcey c7ae84fa4c Remove trailing space. 2013-09-20 10:31:05 -07:00
Steve Ellcey 4f864b3500 2013-09-20 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/memset.S: Change prefetching and add loop unrolling.
	* sysdeps/mips/mips64/memset.S: Remove.
2013-09-20 10:29:51 -07:00
Steve Ellcey 79440ec78c 2013-09-20 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/memset.S: Change prefetching and add loop unrolling.
	* sysdeps/mips/mips64/memset.S: Remove.
2013-09-20 10:29:25 -07:00
Maxim Kuvyrkov d70d6205fa Improve atomic locking for ARM.
[BZ #15640]
	* sysdeps/arm/bits/atomic.h (atomic_exchange_acq, atomic_exchange_rel)
	(atomic_compare_and_exchange_bool_acq)
	(atomic_compare_and_exchange_val_acq)
	(atomic_compare_and_exchange_bool_rel)
	(atomic_compare_and_exchange_val_rel): Use __atomic_exchange_n and
	__atomic_compare_exchange_n builtins when GCC supports them.
2013-09-19 18:50:17 +12:00
Maciej W. Rozycki 9c21573c02 MIPS: IEEE 754-2008 NaN encoding support
It has been a long practice for software using IEEE 754 floating-point
arithmetic run on MIPS processors to use an encoding of Not-a-Number
(NaN) data different to one used by software run on other processors.
And as of IEEE 754-2008 revision [1] this encoding does not follow one
recommended in the standard, as specified in section 6.2.1, where it
is stated that quiet NaNs should have the first bit (d1) of their
significand set to 1 while signalling NaNs should have that bit set to
0, but MIPS software interprets the two bits in the opposite manner.

As from revision 3.50 [2][3] the MIPS Architecture provides for
processors that support the IEEE 754-2008 preferred NaN encoding format.
As the two formats (further referred to as "legacy NaN" and "2008 NaN")
are incompatible to each other, tools have to provide support for the
two formats to help people avoid using incompatible binary modules.

The change is comprised of two functional groups of features, both of
which are required for correct support.

1. Dynamic linker support.

   To enforce the NaN encoding requirement in dynamic linking a new ELF
   file header flag has been defined.  This flag is set for 2008-NaN
   shared modules and executables and clear for legacy-NaN ones.  The
   dynamic linker silently ignores any incompatible modules it
   encounters in dependency processing.

   To avoid unnecessary processing of incompatible modules in the
   presence of a shared module cache, a set of new cache flags has been
   defined to mark 2008-NaN modules for the three ABIs supported.
   Changes to sysdeps/unix/sysv/linux/mips/readelflib.c have been made
   following an earlier code quality suggestion made here:

   http://sourceware.org/ml/libc-ports/2009-03/msg00036.html

   and are therefore a little bit more extensive than the minimum
   required.

   Finally a new name has been defined for the dynamic linker so that
   2008-NaN and legacy-NaN binaries can coexist on a single system that
   supports dual-mode operation and that a legacy dynamic linker that
   does not support verifying the 2008-NaN ELF file header flag is not
   chosen to interpret a 2008-NaN binary by accident.

2. Floating environment support.

   IEEE 754-2008 features are controlled in the Floating-Point Control
   and Status (FCSR) register and updates are needed to floating
   environment support so that the 2008-NaN flag is set correctly and
   the kernel default, inferred from the 2008-NaN ELF file header flag
   at the time an executable is loaded, respected.

As the NaN encoding format is a property of GCC code generation that is
both a user-selected GCC configuration default and can be overridden
with GCC options, code that needs to know what NaN encoding standard it
has been configured for checks for the __mips_nan2008 macro that is
defined internally by GCC whenever the 2008-NaN mode has been selected.
This mode is determined at the glibc configuration time and therefore a
few consistency checks have been added to catch cases where compilation
flags have been overridden by the user.

The 2008 NaN set of features relies on kernel support as the in-kernel
floating-point emulator needs to be aware of the NaN encoding used even
on hard-float processors and configure the FPU context according to the
value of the 2008 NaN ELF file header flag of the executable being
started.  As at this time work on kernel support is still in progress
and the relevant changes have not made their way yet to linux.org master
repository.

Therefore the minimum version supported has been artificially set to
10.0.0 so that 2008-NaN code is not accidentally run on a Linux kernel
that does not suppport it.  It is anticipated that the version is
adjusted later on to the actual initial linux.org kernel version to
support this feature.  Legacy NaN encoding support is unaffected, older
kernel versions remain supported.

[1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer
    Society, IEEE Std 754-2008, 29 August 2008

[2] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
    MIPS32 Architecture", MIPS Technologies, Inc., Document Number:
    MD00082, Revision 3.50, September 20, 2012

[3] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
    MIPS64 Architecture", MIPS Technologies, Inc., Document Number:
    MD00083, Revision 3.50, September 20, 2012
2013-09-18 21:33:50 +01:00
Will Newton cd90698b54 ARM: Improve armv7 memcpy performance.
Only enter the aligned copy loop with buffers that can be 8-byte
aligned. This improves performance slightly on Cortex-A9 and
Cortex-A15 cores for large copies with buffers that are 4-byte
aligned but not 8-byte aligned.

ports/ChangeLog.arm:

2013-09-16  Will Newton  <will.newton@linaro.org>

	* sysdeps/arm/armv7/multiarch/memcpy_impl.S: Tighten check
	on entry to aligned copy loop to improve performance.
2013-09-16 17:55:28 +01:00
Andreas Schwab ffdd31816a Add O_TMPFILE to <fcntl.h> 2013-09-11 11:52:46 +02:00
Joseph Myers 2deb7bdb74 Define MMAP2_PAGE_SHIFT to -1 for m68k. 2013-09-04 20:50:20 +00:00
Mike Frysinger 18d4371683 hppa: add fanotify_mark
Another example of all the 64bit arches getting the definition via a
common file, but the 32bit ones all adding it by themselves and hppa
was missed.

I'm not entirely sure about the usage of GLIBC_2.19 symbols here.
We'd like to backport this so people can use it, but it means we'd
be releasing a glibc-2.17/glibc-2.18 with a GLIBC_2.19 symbol in it.
But maybe it won't be a big deal since you'd only get that 2.19 ref
if you actually used the symbol ?

There hasn't been a glibc release where hppa worked w/out a bunch of
patches, so in reality there's only two distros that matter -- Gentoo
and Debian.

Reported-by: Jeroen Roovers <jer@gentoo.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-09-02 23:22:24 -04:00
Roland McGrath b0350db974 Use sfi_* macros in armv6t2 strlen. 2013-08-30 11:16:52 -07:00
Roland McGrath 21bfcecf7a Make armv6t2 strlen work in ARM mode too. 2013-08-30 10:43:39 -07:00
Ondřej Bílka f24a6d086b Fix then/than typos. 2013-08-30 18:10:31 +02:00
Ondřej Bílka 382466e04e Fix typos. 2013-08-30 18:08:59 +02:00
Will Newton 6b06ac56cd ARM: Fix clone code when built for Thumb.
The mov lr, pc instruction will lose the Thumb bit from the return address
so use blx lr instead.

ports/ChangeLog.arm:

2013-08-30  Will Newton  <will.newton@linaro.org>

	[BZ #15909]
	* sysdeps/unix/sysv/linux/arm/clone.S (__clone): Use blx
	instead of mov lr, pc.
2013-08-30 10:50:25 +01:00
Will Newton 2601bc1860 sysdeps/arm/armv6t2/strlen.S: strlen implementation for armv6t2.
This implementation of strlen is faster than the armv6 version for
all string lengths greater than 1 on a Cortex-A15.

ports/ChangeLog.arm:

2013-08-09  Will Newton  <will.newton@linaro.org>

	* sysdeps/arm/armv6t2/strlen.S: New file.
2013-08-30 10:04:57 +01:00
Thomas Schwinge c54290cf08 Use ELFOSABI_GNU instead of ELFOSABI_LINUX. 2013-08-29 12:22:17 +02:00
Ondřej Bílka 6f65e66895 Fix typos. 2013-08-29 09:11:45 +02:00
Carlos O'Donell d0721e703d ARM: Pass dl_hwcap to IFUNC resolver.
For REL relocs pass dl_hwcap to the IFUNC resolver
as is required by the IFUNC API (bug 15905).
2013-08-29 00:20:35 -04:00
Maciej W. Rozycki b72ca61b71 MIPS: Correct the handling of reserved FCSR bits
Reserved bits in the Floating-Point Control and Status Register (FCSR)
should not be implicitly cleared by fedisableexcept or feenableexcept,
there is no reason to.  Among these are the 8 condition codes and one of
the two bits reserved for architecture implementers (bits #22 & #21).

As to the latter, there is no reason to treat any of them as reserved
either, they should be user controllable and settable via __fpu_control
override as the user sees fit.  For example in processors implemented by
MIPS Technologies, such as the 5Kf or the 24Kf, these bits are used to
change the treatment of denormalised operands and tiny results: bit #22
is Flush Override (FO) and bit #21 is Flush to Nearest (FN).  They cause
non-IEEE-compliant behaviour, but some programs may have a use for such
modes of operation; the library should not obstruct such use just as it
does not for the architectural Flush to Zero (FS) bit (bit #24).

Therefore the change adjusts the reserved mask accordingly and also
documents the distinction between bits 22:21 and 20:18.
2013-08-22 17:55:17 +01:00
Ondřej Bílka c0c3f78afb Fix typos. 2013-08-21 19:48:48 +02:00
Alexandre Oliva 3f8b479fe0 PR 15483
* sysdeps/powerpc/nofpu/sim-full.c: Add FIXME note about
the need for thread-specific variables preserved across signal
handlers.
* sysdeps/powerpc/nofpu/soft-supp.h: Likewise.
* sysdeps/powerpc/soft-fp/sfp-machine.h: Likewise.
2013-08-17 01:24:00 -03:00
Marcus Shawcroft f8b4877a75 [AArch64] Provide symbol version for _mcount. 2013-07-26 08:29:17 +01:00
Carlos O'Donell cb821cb175 hppa: Regenerate libm-test-ulps. 2013-07-23 23:49:00 -04:00
Chris Metcalf 1fe2988f52 tile BZ #15759: Fix bug in _dl_unmap
We returned without calling __munmap if not in the simulator.
Now we call a separate sim_dlclose() function to make the
control flow work correctly.
2013-07-22 11:56:36 -04:00
Andreas Schwab 106bd84baa m68k: use _dl_static_init to set GLR0(dl_pagesize) 2013-07-21 00:43:54 +02:00
Chris Metcalf 19a601f7b2 tile: add missing semicolon in <bits/ptrace.h>
Change 521c6785e1 added the enum but missed the semicolon.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-07-19 13:06:30 -04:00
Marcus Shawcroft 39f0b2e91a [AArch64] Adding -funwind-tables to backtrace.c 2013-07-12 11:22:32 +01:00
Marcus Shawcroft 8ab07407ba [AArch64] Use _dl_static_init to set GLR0(dl_pagesize) 2013-07-09 15:07:12 +01:00
Chris Metcalf 95a4e1ea3b tile: use _dl_static_init to set GLRO(gl_pagesize)
A recently-added test (dlfcn/tststatic5) pointed out that tile was not
properly initializing the variable pagesize in certain cases.  This
change just copies the existing code from MIPS.
2013-07-07 11:33:25 -04:00
Chris Metcalf b68c223125 tile: update libm-test-ulps from scratch 2013-07-07 11:33:24 -04:00
Chris Metcalf 36002f0786 tile: use soft-fp for fma() and fmaf()
The sfp-machine.h is based on the gcc version, but extended with
required new macros by comparison with other architectures and by
investigating the hardware support for FP on tile.
2013-07-07 11:33:24 -04:00
Marcus Shawcroft bb3ced6f37 [AArch64] Regenerate libm-test-ulps 2013-07-05 09:30:52 +01:00
Andreas Jaeger 521c6785e1 Sync sys/ptrace with Linux 3.10 2013-07-04 09:49:14 +02:00
Joseph Myers a0d93e9b26 Condition sysdeps/arm/include/bits/setjmp.h contents on _ISOMAC. 2013-07-03 21:59:58 +00:00
Joseph Myers 52667c6cad Regenerate powerpc-nofpu ULPs. 2013-07-03 16:32:52 +00:00
Andreas Schwab 6ed4c7891a m68k: update libm test ULPs 2013-07-03 00:50:37 +02:00
Joseph Myers 62e9e9f802 Regenerate MIPS ulps. 2013-07-02 21:53:23 +00:00
Joseph Myers b4ac1f6acb Regenerate ARM ulps. 2013-07-02 20:34:19 +00:00
Joseph Myers 6bed143eb4 Make soft-float ARM use soft-fp fma/fmaf. 2013-07-02 19:51:19 +00:00
Richard Henderson c87156e5e9 alpha: Update libm-test-ulps from scratch 2013-07-02 09:59:50 -07:00
Joseph Myers 77f01ab5d1 Implement fma in soft-fp. 2013-07-02 14:55:32 +00:00
Will Newton 1413c693d3 ARM: Pass dl_hwcap to IFUNC resolver functions. 2013-07-02 13:01:21 +00:00
Joseph Myers c53e2f0a56 Support no-FPU ColdFire in sysdeps/m68k/dl-trampoline.S and refactor code. 2013-06-30 21:36:59 +00:00
Chris Metcalf 8145005c31 tile: switch to using <fenv.h> fallback functions
Now that the fallback functions match the desired semantics for tile
functions, just switch to using them.
2013-06-30 11:50:43 -04:00
Ryan S. Arnold 1ae8bfe07c Add GLRO(dl_hwcap2) for new AT_HWCAP2 auxv_t a_type. 2013-06-28 16:50:48 -05:00
Joseph Myers ef65da39e6 Fix sysdeps/m68k/fpu_control.h preprocessor indentation. 2013-06-28 20:30:43 +00:00