76 lines
2.8 KiB
C
76 lines
2.8 KiB
C
/* Atomic operations. PowerPC32 version.
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Copyright (C) 2003 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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/*
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* The 32-bit exchange_bool is different on powerpc64 because the subf
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* does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
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* (a load word and zero (high 32) form). So powerpc64 has a slightly
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* different version in sysdeps/powerpc/powerpc64/bits/atomic.h.
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*/
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# define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
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({ \
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unsigned int __tmp; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: lwarx %0,0,%1\n" \
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" subf. %0,%2,%0\n" \
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" bne 2f\n" \
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" stwcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp) \
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: "b" (mem), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp != 0; \
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})
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/*
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* Powerpc32 processors don't implement the 64-bit (doubleword) forms of
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* load and reserve (ldarx) and store conditional (stdcx.) instructions.
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* So for powerpc32 we stub out the 64-bit forms.
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*/
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# define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
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(abort (), 0)
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# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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(abort (), 0)
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# define __arch_atomic_exchange_64(mem, value) \
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({ abort (); (*mem) = (value); })
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# define __arch_atomic_exchange_and_add_64(mem, value) \
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({ abort (); (*mem) = (value); })
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# define __arch_atomic_decrement_if_positive_64(mem) \
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({ abort (); (*mem)--; })
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/*
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* Older powerpc32 processors don't support the new "light weight"
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* sync (lwsync). So the only safe option is to use normal sync
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* for all powerpc32 applications.
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*/
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# define atomic_read_barrier() __asm ("sync" ::: "memory")
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/*
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* Include the rest of the atomic ops macros which are common to both
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* powerpc32 and powerpc64.
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*/
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#include_next <bits/atomic.h>
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