136 lines
4.9 KiB
C
136 lines
4.9 KiB
C
/* Atomic operations. PowerPC64 version.
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Copyright (C) 2003 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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/*
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* The 32-bit exchange_bool is different on powerpc64 because the subf
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* does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
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* (a load word and zero (high 32) form) load.
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* In powerpc64 register values are 64-bit by default, including oldval.
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* Net we need to extend sign word the result of lwarx to 64-bit so the
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* 64-bit subtract from gives the expected result and sets the condition
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* correctly.
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*/
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# define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
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({ \
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unsigned int __tmp; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: lwarx %0,0,%1\n" \
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" extsw %0,%0\n" \
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" subf. %0,%2,%0\n" \
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" bne 2f\n" \
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" stwcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp) \
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: "b" (mem), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp != 0; \
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})
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/*
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* Only powerpc64 processors support Load doubleword and reserve index (ldarx)
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* and Store doubleword conditional indexed (stdcx) instructions. So here
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* we define the 64-bit forms.
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*/
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# define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
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({ \
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unsigned long __tmp; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%1\n" \
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" subf. %0,%2,%0\n" \
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" bne 2f\n" \
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" stdcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp) \
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: "b" (mem), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp != 0; \
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})
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#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __tmp; \
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__typeof (mem) __memp = (mem); \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%1\n" \
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" cmpd %0,%2\n" \
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" bne 2f\n" \
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" stdcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp) \
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: "b" (__memp), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp; \
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})
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# define __arch_atomic_exchange_64(mem, value) \
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({ \
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__typeof (*mem) __val; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%2\n" \
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" stdcx. %3,0,%2\n" \
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" bne- 1b" \
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: "=&r" (__val), "=m" (*mem) \
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: "b" (mem), "r" (value), "1" (*mem) \
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: "cr0"); \
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__val; \
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})
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# define __arch_atomic_exchange_and_add_64(mem, value) \
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({ \
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__typeof (*mem) __val, __tmp; \
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__asm __volatile ("1: ldarx %0,0,%3\n" \
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" add %1,%0,%4\n" \
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" stdcx. %1,0,%3\n" \
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" bne- 1b" \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "r" (value), "2" (*mem) \
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: "cr0"); \
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__val; \
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})
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# define __arch_atomic_decrement_if_positive_64(mem) \
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({ int __val, __tmp; \
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__asm __volatile ("1: ldarx %0,0,%3\n" \
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" cmpdi 0,%0,0\n" \
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" addi %1,%0,-1\n" \
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" ble 2f\n" \
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" stdcx. %1,0,%3\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "2" (*mem) \
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: "cr0"); \
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__val; \
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})
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/*
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* All powerpc64 processors support the new "light weight" sync (lwsync).
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*/
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# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
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/*
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* Include the rest of the atomic ops macros which are common to both
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* powerpc32 and powerpc64.
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*/
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#include_next <bits/atomic.h>
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