c3d8dc45c9
Th commit 'Disable TSX on some Haswell processors.' (2702856bf4) changed the
default flags for Haswell models. Previously, new models were handled by the
default switch path, which assumed a Core i3/i5/i7 if AVX is available. After
the patch, Haswell models (0x3f, 0x3c, 0x45, 0x46) do not set the flags
Fast_Rep_String, Fast_Unaligned_Load, Fast_Unaligned_Copy, and
Prefer_PMINUB_for_stringop (only the TSX one).
This patch fixes it by disentangle the TSX flag handling from the memory
optimization ones. The strstr case cited on patch now selects the
__strstr_sse2_unaligned as expected for the Haswell cpu.
Checked on x86_64-linux-gnu.
[BZ #23709]
* sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits
independently of other flags.
531 lines
15 KiB
C
531 lines
15 KiB
C
/* Initialize CPU feature data.
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This file is part of the GNU C Library.
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Copyright (C) 2008-2018 Free Software Foundation, Inc.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <cpuid.h>
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#include <cpu-features.h>
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#include <dl-hwcap.h>
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#include <libc-pointer-arith.h>
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#if HAVE_TUNABLES
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# define TUNABLE_NAMESPACE cpu
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# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */
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# include <elf/dl-tunables.h>
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extern void TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *)
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attribute_hidden;
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# if CET_ENABLED
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extern void TUNABLE_CALLBACK (set_x86_ibt) (tunable_val_t *)
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attribute_hidden;
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extern void TUNABLE_CALLBACK (set_x86_shstk) (tunable_val_t *)
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attribute_hidden;
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# endif
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#endif
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#if CET_ENABLED
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# include <dl-cet.h>
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# include <cet-tunables.h>
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#endif
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static void
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get_extended_indices (struct cpu_features *cpu_features)
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{
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unsigned int eax, ebx, ecx, edx;
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__cpuid (0x80000000, eax, ebx, ecx, edx);
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if (eax >= 0x80000001)
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__cpuid (0x80000001,
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cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].eax,
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cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].ebx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].ecx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].edx);
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}
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static void
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get_common_indices (struct cpu_features *cpu_features,
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unsigned int *family, unsigned int *model,
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unsigned int *extended_model, unsigned int *stepping)
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{
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if (family)
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{
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unsigned int eax;
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__cpuid (1, eax, cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_1].edx);
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cpu_features->cpuid[COMMON_CPUID_INDEX_1].eax = eax;
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*family = (eax >> 8) & 0x0f;
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*model = (eax >> 4) & 0x0f;
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*extended_model = (eax >> 12) & 0xf0;
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*stepping = eax & 0x0f;
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if (*family == 0x0f)
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{
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*family += (eax >> 20) & 0xff;
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*model += *extended_model;
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}
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}
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if (cpu_features->max_cpuid >= 7)
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__cpuid_count (7, 0,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].eax,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].ebx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].ecx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].edx);
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/* Can we call xgetbv? */
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if (CPU_FEATURES_CPU_P (cpu_features, OSXSAVE))
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{
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unsigned int xcrlow;
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unsigned int xcrhigh;
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asm ("xgetbv" : "=a" (xcrlow), "=d" (xcrhigh) : "c" (0));
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/* Is YMM and XMM state usable? */
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if ((xcrlow & (bit_YMM_state | bit_XMM_state)) ==
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(bit_YMM_state | bit_XMM_state))
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{
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/* Determine if AVX is usable. */
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if (CPU_FEATURES_CPU_P (cpu_features, AVX))
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{
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cpu_features->feature[index_arch_AVX_Usable]
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|= bit_arch_AVX_Usable;
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/* The following features depend on AVX being usable. */
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/* Determine if AVX2 is usable. */
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if (CPU_FEATURES_CPU_P (cpu_features, AVX2))
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{
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cpu_features->feature[index_arch_AVX2_Usable]
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|= bit_arch_AVX2_Usable;
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/* Unaligned load with 256-bit AVX registers are faster on
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Intel/AMD processors with AVX2. */
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cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
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|= bit_arch_AVX_Fast_Unaligned_Load;
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}
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/* Determine if FMA is usable. */
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if (CPU_FEATURES_CPU_P (cpu_features, FMA))
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cpu_features->feature[index_arch_FMA_Usable]
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|= bit_arch_FMA_Usable;
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}
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/* Check if OPMASK state, upper 256-bit of ZMM0-ZMM15 and
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ZMM16-ZMM31 state are enabled. */
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if ((xcrlow & (bit_Opmask_state | bit_ZMM0_15_state
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| bit_ZMM16_31_state)) ==
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(bit_Opmask_state | bit_ZMM0_15_state | bit_ZMM16_31_state))
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{
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/* Determine if AVX512F is usable. */
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if (CPU_FEATURES_CPU_P (cpu_features, AVX512F))
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{
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cpu_features->feature[index_arch_AVX512F_Usable]
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|= bit_arch_AVX512F_Usable;
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/* Determine if AVX512DQ is usable. */
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if (CPU_FEATURES_CPU_P (cpu_features, AVX512DQ))
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cpu_features->feature[index_arch_AVX512DQ_Usable]
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|= bit_arch_AVX512DQ_Usable;
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}
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}
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}
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/* For _dl_runtime_resolve, set xsave_state_size to xsave area
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size + integer register save size and align it to 64 bytes. */
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if (cpu_features->max_cpuid >= 0xd)
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{
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unsigned int eax, ebx, ecx, edx;
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__cpuid_count (0xd, 0, eax, ebx, ecx, edx);
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if (ebx != 0)
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{
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unsigned int xsave_state_full_size
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= ALIGN_UP (ebx + STATE_SAVE_OFFSET, 64);
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cpu_features->xsave_state_size
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= xsave_state_full_size;
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cpu_features->xsave_state_full_size
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= xsave_state_full_size;
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__cpuid_count (0xd, 1, eax, ebx, ecx, edx);
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/* Check if XSAVEC is available. */
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if ((eax & (1 << 1)) != 0)
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{
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unsigned int xstate_comp_offsets[32];
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unsigned int xstate_comp_sizes[32];
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unsigned int i;
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xstate_comp_offsets[0] = 0;
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xstate_comp_offsets[1] = 160;
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xstate_comp_offsets[2] = 576;
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xstate_comp_sizes[0] = 160;
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xstate_comp_sizes[1] = 256;
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for (i = 2; i < 32; i++)
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{
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if ((STATE_SAVE_MASK & (1 << i)) != 0)
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{
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__cpuid_count (0xd, i, eax, ebx, ecx, edx);
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xstate_comp_sizes[i] = eax;
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}
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else
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{
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ecx = 0;
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xstate_comp_sizes[i] = 0;
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}
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if (i > 2)
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{
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xstate_comp_offsets[i]
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= (xstate_comp_offsets[i - 1]
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+ xstate_comp_sizes[i -1]);
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if ((ecx & (1 << 1)) != 0)
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xstate_comp_offsets[i]
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= ALIGN_UP (xstate_comp_offsets[i], 64);
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}
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}
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/* Use XSAVEC. */
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unsigned int size
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= xstate_comp_offsets[31] + xstate_comp_sizes[31];
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if (size)
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{
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cpu_features->xsave_state_size
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= ALIGN_UP (size + STATE_SAVE_OFFSET, 64);
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cpu_features->feature[index_arch_XSAVEC_Usable]
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|= bit_arch_XSAVEC_Usable;
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}
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}
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}
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}
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}
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}
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static inline void
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init_cpu_features (struct cpu_features *cpu_features)
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{
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unsigned int ebx, ecx, edx;
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unsigned int family = 0;
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unsigned int model = 0;
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enum cpu_features_kind kind;
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#if !HAS_CPUID
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if (__get_cpuid_max (0, 0) == 0)
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{
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kind = arch_kind_other;
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goto no_cpuid;
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}
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#endif
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__cpuid (0, cpu_features->max_cpuid, ebx, ecx, edx);
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/* This spells out "GenuineIntel". */
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if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
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{
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unsigned int extended_model, stepping;
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kind = arch_kind_intel;
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get_common_indices (cpu_features, &family, &model, &extended_model,
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&stepping);
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get_extended_indices (cpu_features);
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if (family == 0x06)
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{
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model += extended_model;
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switch (model)
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{
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case 0x1c:
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case 0x26:
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/* BSF is slow on Atom. */
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cpu_features->feature[index_arch_Slow_BSF]
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|= bit_arch_Slow_BSF;
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break;
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case 0x57:
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/* Knights Landing. Enable Silvermont optimizations. */
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case 0x5c:
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case 0x5f:
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/* Unaligned load versions are faster than SSSE3
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on Goldmont. */
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case 0x4c:
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/* Airmont is a die shrink of Silvermont. */
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case 0x37:
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case 0x4a:
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case 0x4d:
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case 0x5a:
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case 0x5d:
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/* Unaligned load versions are faster than SSSE3
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on Silvermont. */
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#if index_arch_Fast_Unaligned_Load != index_arch_Prefer_PMINUB_for_stringop
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# error index_arch_Fast_Unaligned_Load != index_arch_Prefer_PMINUB_for_stringop
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#endif
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#if index_arch_Fast_Unaligned_Load != index_arch_Slow_SSE4_2
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# error index_arch_Fast_Unaligned_Load != index_arch_Slow_SSE4_2
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#endif
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#if index_arch_Fast_Unaligned_Load != index_arch_Fast_Unaligned_Copy
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# error index_arch_Fast_Unaligned_Load != index_arch_Fast_Unaligned_Copy
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#endif
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cpu_features->feature[index_arch_Fast_Unaligned_Load]
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|= (bit_arch_Fast_Unaligned_Load
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| bit_arch_Fast_Unaligned_Copy
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| bit_arch_Prefer_PMINUB_for_stringop
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| bit_arch_Slow_SSE4_2);
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break;
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default:
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/* Unknown family 0x06 processors. Assuming this is one
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of Core i3/i5/i7 processors if AVX is available. */
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if (!CPU_FEATURES_CPU_P (cpu_features, AVX))
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break;
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case 0x1a:
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case 0x1e:
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case 0x1f:
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case 0x25:
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case 0x2c:
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case 0x2e:
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case 0x2f:
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/* Rep string instructions, unaligned load, unaligned copy,
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and pminub are fast on Intel Core i3, i5 and i7. */
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#if index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Load
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# error index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Load
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#endif
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#if index_arch_Fast_Rep_String != index_arch_Prefer_PMINUB_for_stringop
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# error index_arch_Fast_Rep_String != index_arch_Prefer_PMINUB_for_stringop
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#endif
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#if index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Copy
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# error index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Copy
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#endif
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cpu_features->feature[index_arch_Fast_Rep_String]
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|= (bit_arch_Fast_Rep_String
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| bit_arch_Fast_Unaligned_Load
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| bit_arch_Fast_Unaligned_Copy
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| bit_arch_Prefer_PMINUB_for_stringop);
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break;
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}
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/* Disable TSX on some Haswell processors to avoid TSX on kernels that
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weren't updated with the latest microcode package (which disables
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broken feature by default). */
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switch (model)
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{
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case 0x3f:
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/* Xeon E7 v3 with stepping >= 4 has working TSX. */
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if (stepping >= 4)
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break;
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case 0x3c:
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case 0x45:
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case 0x46:
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/* Disable Intel TSX on Haswell processors (except Xeon E7 v3
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with stepping >= 4) to avoid TSX on kernels that weren't
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updated with the latest microcode package (which disables
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broken feature by default). */
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cpu_features->cpuid[index_cpu_RTM].reg_RTM &= ~bit_cpu_RTM;
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break;
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}
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}
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/* Since AVX512ER is unique to Xeon Phi, set Prefer_No_VZEROUPPER
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if AVX512ER is available. Don't use AVX512 to avoid lower CPU
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frequency if AVX512ER isn't available. */
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if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
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cpu_features->feature[index_arch_Prefer_No_VZEROUPPER]
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|= bit_arch_Prefer_No_VZEROUPPER;
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else
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cpu_features->feature[index_arch_Prefer_No_AVX512]
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|= bit_arch_Prefer_No_AVX512;
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}
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/* This spells out "AuthenticAMD". */
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else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
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{
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unsigned int extended_model, stepping;
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kind = arch_kind_amd;
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get_common_indices (cpu_features, &family, &model, &extended_model,
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&stepping);
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get_extended_indices (cpu_features);
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ecx = cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx;
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if (HAS_ARCH_FEATURE (AVX_Usable))
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{
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/* Since the FMA4 bit is in COMMON_CPUID_INDEX_80000001 and
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FMA4 requires AVX, determine if FMA4 is usable here. */
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if (CPU_FEATURES_CPU_P (cpu_features, FMA4))
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cpu_features->feature[index_arch_FMA4_Usable]
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|= bit_arch_FMA4_Usable;
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}
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if (family == 0x15)
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{
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#if index_arch_Fast_Unaligned_Load != index_arch_Fast_Copy_Backward
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# error index_arch_Fast_Unaligned_Load != index_arch_Fast_Copy_Backward
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#endif
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/* "Excavator" */
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if (model >= 0x60 && model <= 0x7f)
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{
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cpu_features->feature[index_arch_Fast_Unaligned_Load]
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|= (bit_arch_Fast_Unaligned_Load
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| bit_arch_Fast_Copy_Backward);
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/* Unaligned AVX loads are slower.*/
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cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
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&= ~bit_arch_AVX_Fast_Unaligned_Load;
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}
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}
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}
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else
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{
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kind = arch_kind_other;
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get_common_indices (cpu_features, NULL, NULL, NULL, NULL);
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}
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/* Support i586 if CX8 is available. */
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if (CPU_FEATURES_CPU_P (cpu_features, CX8))
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cpu_features->feature[index_arch_I586] |= bit_arch_I586;
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/* Support i686 if CMOV is available. */
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if (CPU_FEATURES_CPU_P (cpu_features, CMOV))
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cpu_features->feature[index_arch_I686] |= bit_arch_I686;
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|
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#if !HAS_CPUID
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no_cpuid:
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#endif
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cpu_features->family = family;
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cpu_features->model = model;
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cpu_features->kind = kind;
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#if HAVE_TUNABLES
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TUNABLE_GET (hwcaps, tunable_val_t *, TUNABLE_CALLBACK (set_hwcaps));
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cpu_features->non_temporal_threshold
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= TUNABLE_GET (x86_non_temporal_threshold, long int, NULL);
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cpu_features->data_cache_size
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= TUNABLE_GET (x86_data_cache_size, long int, NULL);
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cpu_features->shared_cache_size
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= TUNABLE_GET (x86_shared_cache_size, long int, NULL);
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#endif
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|
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/* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. */
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#if !HAVE_TUNABLES && defined SHARED
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/* The glibc.cpu.hwcap_mask tunable is initialized already, so no need to do
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this. */
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GLRO(dl_hwcap_mask) = HWCAP_IMPORTANT;
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#endif
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#ifdef __x86_64__
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GLRO(dl_hwcap) = HWCAP_X86_64;
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if (cpu_features->kind == arch_kind_intel)
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{
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const char *platform = NULL;
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if (CPU_FEATURES_ARCH_P (cpu_features, AVX512F_Usable)
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&& CPU_FEATURES_CPU_P (cpu_features, AVX512CD))
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{
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if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
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{
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if (CPU_FEATURES_CPU_P (cpu_features, AVX512PF))
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platform = "xeon_phi";
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}
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else
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{
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if (CPU_FEATURES_CPU_P (cpu_features, AVX512BW)
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&& CPU_FEATURES_CPU_P (cpu_features, AVX512DQ)
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&& CPU_FEATURES_CPU_P (cpu_features, AVX512VL))
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GLRO(dl_hwcap) |= HWCAP_X86_AVX512_1;
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}
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}
|
|
|
|
if (platform == NULL
|
|
&& CPU_FEATURES_ARCH_P (cpu_features, AVX2_Usable)
|
|
&& CPU_FEATURES_ARCH_P (cpu_features, FMA_Usable)
|
|
&& CPU_FEATURES_CPU_P (cpu_features, BMI1)
|
|
&& CPU_FEATURES_CPU_P (cpu_features, BMI2)
|
|
&& CPU_FEATURES_CPU_P (cpu_features, LZCNT)
|
|
&& CPU_FEATURES_CPU_P (cpu_features, MOVBE)
|
|
&& CPU_FEATURES_CPU_P (cpu_features, POPCNT))
|
|
platform = "haswell";
|
|
|
|
if (platform != NULL)
|
|
GLRO(dl_platform) = platform;
|
|
}
|
|
#else
|
|
GLRO(dl_hwcap) = 0;
|
|
if (CPU_FEATURES_CPU_P (cpu_features, SSE2))
|
|
GLRO(dl_hwcap) |= HWCAP_X86_SSE2;
|
|
|
|
if (CPU_FEATURES_ARCH_P (cpu_features, I686))
|
|
GLRO(dl_platform) = "i686";
|
|
else if (CPU_FEATURES_ARCH_P (cpu_features, I586))
|
|
GLRO(dl_platform) = "i586";
|
|
#endif
|
|
|
|
#if CET_ENABLED
|
|
# if HAVE_TUNABLES
|
|
TUNABLE_GET (x86_ibt, tunable_val_t *,
|
|
TUNABLE_CALLBACK (set_x86_ibt));
|
|
TUNABLE_GET (x86_shstk, tunable_val_t *,
|
|
TUNABLE_CALLBACK (set_x86_shstk));
|
|
# endif
|
|
|
|
/* Check CET status. */
|
|
unsigned int cet_status = get_cet_status ();
|
|
|
|
if (cet_status)
|
|
{
|
|
GL(dl_x86_feature_1)[0] = cet_status;
|
|
|
|
# ifndef SHARED
|
|
/* Check if IBT and SHSTK are enabled by kernel. */
|
|
if ((cet_status & GNU_PROPERTY_X86_FEATURE_1_IBT)
|
|
|| (cet_status & GNU_PROPERTY_X86_FEATURE_1_SHSTK))
|
|
{
|
|
/* Disable IBT and/or SHSTK if they are enabled by kernel, but
|
|
disabled by environment variable:
|
|
|
|
GLIBC_TUNABLES=glibc.cpu.hwcaps=-IBT,-SHSTK
|
|
*/
|
|
unsigned int cet_feature = 0;
|
|
if (!HAS_CPU_FEATURE (IBT))
|
|
cet_feature |= GNU_PROPERTY_X86_FEATURE_1_IBT;
|
|
if (!HAS_CPU_FEATURE (SHSTK))
|
|
cet_feature |= GNU_PROPERTY_X86_FEATURE_1_SHSTK;
|
|
|
|
if (cet_feature)
|
|
{
|
|
int res = dl_cet_disable_cet (cet_feature);
|
|
|
|
/* Clear the disabled bits in dl_x86_feature_1. */
|
|
if (res == 0)
|
|
GL(dl_x86_feature_1)[0] &= ~cet_feature;
|
|
}
|
|
|
|
/* Lock CET if IBT or SHSTK is enabled in executable. Don't
|
|
lock CET if SHSTK is enabled permissively. */
|
|
if (((GL(dl_x86_feature_1)[1] >> CET_MAX)
|
|
& ((1 << CET_MAX) - 1))
|
|
!= CET_PERMISSIVE)
|
|
dl_cet_lock_cet ();
|
|
}
|
|
# endif
|
|
}
|
|
#endif
|
|
}
|