803 lines
20 KiB
C
803 lines
20 KiB
C
/* Copyright (C) 1992, 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by David Mosberger.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Library General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Library General Public License for more details.
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You should have received a copy of the GNU Library General Public
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License along with the GNU C Library; see the file COPYING.LIB. If not,
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write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* I/O access is restricted to ISA port space (ports 0..65535).
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Modern devices hopefully are sane enough not to put any performance
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critical registers in i/o space.
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On the first call to ioperm() or _sethae(), the entire (E)ISA port
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space is mapped into the virtual address space at address io.base.
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mprotect() calls are then used to enable/disable access to ports. Per
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page, there are PAGE_SIZE>>IO_SHIFT I/O ports (e.g., 256 ports on a
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Low Cost Alpha based system using 8KB pages).
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Keep in mind that this code should be able to run in a 32bit address
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space. It is therefore unreasonable to expect mmap'ing the entire
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sparse address space would work (e.g., the Low Cost Alpha chip has an
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I/O address space that's 512MB large!). */
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#include <errno.h>
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#include <fcntl.h>
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#include <stdio.h>
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#include <ctype.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/mman.h>
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#include <asm/page.h>
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#include <asm/system.h>
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#define PATH_ALPHA_SYSTYPE "/etc/alpha_systype"
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#define PATH_CPUINFO "/proc/cpuinfo"
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#define MAX_PORT 0x10000
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#define vuip volatile unsigned int *
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#define JENSEN_IO_BASE (0xfffffc0300000000UL)
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#define JENSEN_SPARSE_MEM (0xfffffc0200000000UL)
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/* With respect to the I/O architecture, APECS and LCA are identical,
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so the following defines apply to LCA as well. */
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#define APECS_IO_BASE (0xfffffc01c0000000UL)
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#define APECS_SPARSE_MEM (0xfffffc0200000000UL)
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#define APECS_DENSE_MEM (0xfffffc0300000000UL)
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/* The same holds for CIA and PYXIS. */
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#define CIA_IO_BASE (0xfffffc8580000000UL)
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#define CIA_SPARSE_MEM (0xfffffc8000000000UL)
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#define CIA_DENSE_MEM (0xfffffc8600000000UL)
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/* SABLE is EV4, GAMMA is EV5 */
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#define T2_IO_BASE (0xfffffc03a0000000UL)
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#define T2_SPARSE_MEM (0xfffffc0200000000UL)
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#define T2_DENSE_MEM (0xfffffc03c0000000UL)
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#define GAMMA_IO_BASE (0xfffffc83a0000000UL)
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#define GAMMA_SPARSE_MEM (0xfffffc8200000000UL)
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#define GAMMA_DENSE_MEM (0xfffffc83c0000000UL)
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/* these are for the RAWHIDE family */
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#define MCPCIA_IO_BASE (0xfffffcf980000000UL)
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#define MCPCIA_SPARSE_MEM (0xfffffcf800000000UL)
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#define MCPCIA_DENSE_MEM (0xfffffcf900000000UL)
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/* Tsunami has no SPARSE space */
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/* NOTE: these are hardwired to PCI bus 0 addresses!!! */
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/* Also, these are PHYSICAL, as/so there's no KSEG translation */
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#define TSUNAMI_IO_BASE (0x00000801fc000000UL + 0xfffffc0000000000UL)
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#define TSUNAMI_DENSE_MEM (0x0000080000000000UL + 0xfffffc0000000000UL)
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/* Polaris has SPARSE space, but we prefer to use only DENSE */
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/* because of some idiosyncracies in actually using SPARSE */
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#define POLARIS_IO_BASE (0xfffffcf9fc000000UL)
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#define POLARIS_DENSE_MEM (0xfffffcf900000000UL)
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typedef enum {
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IOSYS_UNKNOWN, IOSYS_JENSEN, IOSYS_APECS, IOSYS_CIA, IOSYS_T2,
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IOSYS_TSUNAMI, IOSYS_MCPCIA, IOSYS_GAMMA, IOSYS_POLARIS,
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IOSYS_CPUDEP, IOSYS_PCIDEP
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} iosys_t;
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typedef enum {
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IOSWIZZLE_JENSEN, IOSWIZZLE_SPARSE, IOSWIZZLE_DENSE
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} ioswizzle_t;
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static struct io_system {
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int hae_shift;
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unsigned long int bus_memory_base;
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unsigned long int sparse_bus_mem_base;
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unsigned long int bus_io_base;
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} io_system[] = { /* NOTE! must match iosys_t enumeration */
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/* UNKNOWN */ {0, 0, 0, 0},
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/* JENSEN */ {7, 0, JENSEN_SPARSE_MEM, JENSEN_IO_BASE},
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/* APECS */ {5, APECS_DENSE_MEM, APECS_SPARSE_MEM, APECS_IO_BASE},
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/* CIA */ {5, CIA_DENSE_MEM, CIA_SPARSE_MEM, CIA_IO_BASE},
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/* T2 */ {5, T2_DENSE_MEM, T2_SPARSE_MEM, T2_IO_BASE},
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/* TSUNAMI */ {0, TSUNAMI_DENSE_MEM, 0, TSUNAMI_IO_BASE},
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/* MCPCIA */ {5, MCPCIA_DENSE_MEM, MCPCIA_SPARSE_MEM, MCPCIA_IO_BASE},
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/* GAMMA */ {5, GAMMA_DENSE_MEM, GAMMA_SPARSE_MEM, GAMMA_IO_BASE},
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/* POLARIS */ {0, POLARIS_DENSE_MEM, 0, POLARIS_IO_BASE},
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/* CPUDEP */ {0, 0, 0, 0}, /* for platforms dependent on CPU type */
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/* PCIDEP */ {0, 0, 0, 0}, /* for platforms dependent on core logic */
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};
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static struct platform {
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const char *name;
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iosys_t io_sys;
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} platform[] = {
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{"Alcor", IOSYS_CIA},
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{"Avanti", IOSYS_APECS},
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{"XL", IOSYS_APECS},
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{"Cabriolet", IOSYS_APECS},
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{"EB164", IOSYS_PCIDEP},
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{"EB64+", IOSYS_APECS},
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{"EB66", IOSYS_APECS},
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{"EB66P", IOSYS_APECS},
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{"Jensen", IOSYS_JENSEN},
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{"Mikasa", IOSYS_CPUDEP},
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{"Noritake", IOSYS_CPUDEP},
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{"Noname", IOSYS_APECS},
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{"Sable", IOSYS_CPUDEP},
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{"Miata", IOSYS_CIA},
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{"Tsunami", IOSYS_TSUNAMI},
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{"Rawhide", IOSYS_MCPCIA},
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{"Ruffian", IOSYS_CIA},
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{"Takara", IOSYS_CIA},
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};
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struct ioswtch {
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void (*sethae)(unsigned long int addr);
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void (*outb)(unsigned char b, unsigned long int port);
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void (*outw)(unsigned short b, unsigned long int port);
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void (*outl)(unsigned int b, unsigned long int port);
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unsigned int (*inb)(unsigned long int port);
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unsigned int (*inw)(unsigned long int port);
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unsigned int (*inl)(unsigned long int port);
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};
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static struct {
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struct hae {
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unsigned long int cache;
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unsigned long int * reg;
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} hae;
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unsigned long int base;
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struct ioswtch * swp;
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unsigned long int bus_memory_base;
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unsigned long int sparse_bus_memory_base;
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unsigned long int io_base;
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iosys_t sys;
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ioswizzle_t swiz;
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int hae_shift;
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} io;
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extern void __sethae (unsigned long int); /* we can't use asm/io.h */
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static inline unsigned long int
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port_to_cpu_addr (unsigned long int port, ioswizzle_t ioswiz, int size)
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{
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if (ioswiz == IOSWIZZLE_SPARSE)
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return (port << 5) + ((size - 1) << 3) + io.base;
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else if (ioswiz == IOSWIZZLE_DENSE)
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return port + io.base;
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else
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return (port << 7) + ((size - 1) << 5) + io.base;
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}
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static inline void
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inline_sethae (unsigned long int addr, ioswizzle_t ioswiz)
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{
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if (ioswiz == IOSWIZZLE_SPARSE)
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{
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unsigned long int msb;
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/* no need to set hae if msb is 0: */
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msb = addr & 0xf8000000;
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if (msb && msb != io.hae.cache)
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{
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__sethae (msb);
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io.hae.cache = msb;
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}
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}
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else
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{
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/* hae on the Jensen is bits 31:25 shifted right */
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addr >>= 25;
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if (addr != io.hae.cache)
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{
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__sethae (addr);
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io.hae.cache = addr;
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}
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}
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}
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static inline void
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inline_outb (unsigned char b, unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned int w;
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 1);
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inline_sethae (0, ioswiz);
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asm ("insbl %2,%1,%0" : "=r" (w) : "ri" (port & 0x3), "r" (b));
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*(vuip)addr = w;
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mb ();
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}
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static inline void
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inline_outw (unsigned short int b, unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned int w;
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 2);
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inline_sethae (0, ioswiz);
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asm ("inswl %2,%1,%0" : "=r" (w) : "ri" (port & 0x3), "r" (b));
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*(vuip)addr = w;
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mb ();
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}
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static inline void
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inline_outl (unsigned int b, unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 4);
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inline_sethae (0, ioswiz);
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*(vuip)addr = b;
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mb ();
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}
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static inline unsigned int
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inline_inb (unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int result, addr = port_to_cpu_addr (port, ioswiz, 1);
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inline_sethae (0, ioswiz);
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result = *(vuip) addr;
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result >>= (port & 3) * 8;
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return 0xffUL & result;
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}
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static inline unsigned int
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inline_inw (unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int result, addr = port_to_cpu_addr (port, ioswiz, 2);
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inline_sethae (0, ioswiz);
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result = *(vuip) addr;
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result >>= (port & 3) * 8;
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return 0xffffUL & result;
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}
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static inline unsigned int
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inline_inl (unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 4);
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inline_sethae (0, ioswiz);
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return *(vuip) addr;
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}
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/*
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* Now define the inline functions for CPUs supporting byte/word insns,
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* and whose core logic supports I/O space accesses utilizing them.
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*
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* These routines could be used by MIATA, for example, because it has
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* and EV56 plus PYXIS, but it currently uses SPARSE anyway. This is
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* also true of RX164 which used POLARIS, but we will choose to use
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* these routines in that case instead of SPARSE.
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*
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* These routines are necessary for TSUNAMI/TYPHOON based platforms,
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* which will have (at least) EV6.
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*/
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static inline unsigned long int
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dense_port_to_cpu_addr (unsigned long int port)
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{
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return port + io.base;
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}
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static inline void
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inline_bwx_outb (unsigned char b, unsigned long int port)
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{
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unsigned long int addr = dense_port_to_cpu_addr (port);
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__asm__ __volatile__ ("stb %1,%0" : : "m"(*(unsigned char *)addr), "r"(b));
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mb ();
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}
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static inline void
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inline_bwx_outw (unsigned short int b, unsigned long int port)
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{
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unsigned long int addr = dense_port_to_cpu_addr (port);
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__asm__ __volatile__ ("stw %1,%0" : : "m"(*(unsigned short *)addr), "r"(b));
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mb ();
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}
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static inline void
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inline_bwx_outl (unsigned int b, unsigned long int port)
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{
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unsigned long int addr = dense_port_to_cpu_addr (port);
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*(vuip)addr = b;
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mb ();
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}
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static inline unsigned int
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inline_bwx_inb (unsigned long int port)
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{
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unsigned long int r, addr = dense_port_to_cpu_addr (port);
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__asm__ __volatile__ ("ldbu %0,%1" : "=r"(r) : "m"(*(unsigned char *)addr));
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return 0xffUL & r;
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}
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static inline unsigned int
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inline_bwx_inw (unsigned long int port)
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{
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unsigned long int r, addr = dense_port_to_cpu_addr (port);
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__asm__ __volatile__ ("ldwu %0,%1" : "=r"(r) : "m"(*(unsigned short *)addr));
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return 0xffffUL & r;
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}
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static inline unsigned int
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inline_bwx_inl (unsigned long int port)
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{
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unsigned long int addr = dense_port_to_cpu_addr (port);
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return *(vuip) addr;
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}
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/* macros to define routines with appropriate names and functions */
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/* these do either SPARSE or JENSEN swizzle */
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#define DCL_SETHAE(name, ioswiz) \
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static void \
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name##_sethae (unsigned long int addr) \
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{ \
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inline_sethae (addr, IOSWIZZLE_##ioswiz); \
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}
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#define DCL_OUT(name, func, type, ioswiz) \
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static void \
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name##_##func (unsigned type b, unsigned long int addr) \
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{ \
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inline_##func (b, addr, IOSWIZZLE_##ioswiz); \
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}
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#define DCL_IN(name, func, ioswiz) \
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static unsigned int \
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name##_##func (unsigned long int addr) \
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{ \
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return inline_##func (addr, IOSWIZZLE_##ioswiz); \
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}
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/* these do DENSE, so no swizzle is needed */
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#define DCL_OUT_BWX(name, func, type) \
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static void \
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name##_##func (unsigned type b, unsigned long int addr) \
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{ \
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inline_bwx_##func (b, addr); \
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}
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#define DCL_IN_BWX(name, func) \
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static unsigned int \
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name##_##func (unsigned long int addr) \
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{ \
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return inline_bwx_##func (addr); \
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}
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/* now declare/define the necessary routines */
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DCL_SETHAE(jensen, JENSEN)
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DCL_OUT(jensen, outb, char, JENSEN)
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DCL_OUT(jensen, outw, short int, JENSEN)
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DCL_OUT(jensen, outl, int, JENSEN)
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DCL_IN(jensen, inb, JENSEN)
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DCL_IN(jensen, inw, JENSEN)
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DCL_IN(jensen, inl, JENSEN)
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DCL_SETHAE(sparse, SPARSE)
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DCL_OUT(sparse, outb, char, SPARSE)
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DCL_OUT(sparse, outw, short int, SPARSE)
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DCL_OUT(sparse, outl, int, SPARSE)
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DCL_IN(sparse, inb, SPARSE)
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DCL_IN(sparse, inw, SPARSE)
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DCL_IN(sparse, inl, SPARSE)
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DCL_OUT_BWX(dense, outb, char)
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DCL_OUT_BWX(dense, outw, short int)
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DCL_OUT_BWX(dense, outl, int)
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DCL_IN_BWX(dense, inb)
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DCL_IN_BWX(dense, inw)
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DCL_IN_BWX(dense, inl)
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/* define the "swizzle" switch */
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static struct ioswtch ioswtch[] = {
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{
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jensen_sethae,
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jensen_outb, jensen_outw, jensen_outl,
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jensen_inb, jensen_inw, jensen_inl
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},
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{
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sparse_sethae,
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sparse_outb, sparse_outw, sparse_outl,
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sparse_inb, sparse_inw, sparse_inl
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},
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{
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NULL,
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dense_outb, dense_outw, dense_outl,
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dense_inb, dense_inw, dense_inl
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}
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};
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#undef DEBUG_IOPERM
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/* routine to process the /proc/cpuinfo information into the fields */
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/* that are required for correctly determining the platform parameters */
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char systype[256]; /* system type field */
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char sysvari[256]; /* system variation field */
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char cpumodel[256]; /* cpu model field */
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int got_type, got_vari, got_model;
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static int
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process_cpuinfo(void)
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{
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char dummy[256];
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FILE * fp;
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fp = fopen (PATH_CPUINFO, "r");
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if (!fp)
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return 0;
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got_type = got_vari = got_model = 0;
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systype[0] = sysvari[0] = cpumodel[0] = 0;
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while (1)
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{
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if (fgets (dummy, 256, fp) == NULL) break;
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/* fprintf(stderr, "read: %s", dummy); */
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if (!got_type &&
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sscanf (dummy, "system type : %256[^\n]\n", systype) == 1)
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got_type = 1;
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if (!got_vari &&
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sscanf (dummy, "system variation : %256[^\n]\n", sysvari) == 1)
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got_vari = 1;
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if (!got_model &&
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sscanf (dummy, "cpu model : %256[^\n]\n", cpumodel) == 1)
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got_model = 1;
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}
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fclose (fp);
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#ifdef DEBUG_IOPERM
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fprintf(stderr, "system type: %s\n", systype);
|
|
fprintf(stderr, "system vari: %s\n", sysvari);
|
|
fprintf(stderr, "cpu model: %s\n", cpumodel);
|
|
#endif
|
|
|
|
return got_type+got_vari+got_model;
|
|
}
|
|
/*
|
|
* Initialize I/O system. To determine what I/O system we're dealing
|
|
* with, we first try to read the value of symlink PATH_ALPHA_SYSTYPE,
|
|
* if that fails, we lookup the "system type" field in /proc/cpuinfo.
|
|
* If that fails as well, we give up.
|
|
*
|
|
* If the value received from PATH_ALPHA_SYSTYPE begins with a number,
|
|
* assume this is a previously unsupported system and the values encode,
|
|
* in order, "<io_base>,<hae_shift>,<dense_base>,<sparse_base>".
|
|
*/
|
|
static int
|
|
init_iosys (void)
|
|
{
|
|
int i, n;
|
|
|
|
n = readlink (PATH_ALPHA_SYSTYPE, systype, sizeof (systype) - 1);
|
|
if (n > 0)
|
|
{
|
|
systype[n] = '\0';
|
|
if (isdigit (systype[0]))
|
|
{
|
|
if (sscanf (systype, "%li,%i,%li,%li", &io.io_base, &io.hae_shift,
|
|
&io.bus_memory_base, &io.sparse_bus_memory_base) == 4)
|
|
{
|
|
io.sys = IOSYS_UNKNOWN;
|
|
io.swiz = IOSWIZZLE_SPARSE;
|
|
io.swp = &ioswtch[IOSWIZZLE_SPARSE];
|
|
return 0;
|
|
}
|
|
/* else we're likely going to fail with the system match below */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
n = process_cpuinfo();
|
|
|
|
if (!n)
|
|
{
|
|
/* this can happen if the format of /proc/cpuinfo changes... */
|
|
fprintf (stderr,
|
|
"ioperm.init_iosys(): Unable to determine system type.\n"
|
|
"\t(May need " PATH_ALPHA_SYSTYPE " symlink?)\n");
|
|
__set_errno (ENODEV);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
/* translate systype name into i/o system: */
|
|
for (i = 0; i < sizeof (platform) / sizeof (platform[0]); ++i)
|
|
{
|
|
if (strcmp (platform[i].name, systype) == 0)
|
|
{
|
|
io.sys = platform[i].io_sys;
|
|
/* some platforms can have either EV4 or EV5 CPUs */
|
|
if (io.sys == IOSYS_CPUDEP) /* SABLE or MIKASA or NORITAKE so far */
|
|
{
|
|
if (strcmp (platform[i].name, "Sable") == 0)
|
|
{
|
|
if (strncmp (cpumodel, "EV4", 3) == 0)
|
|
io.sys = IOSYS_T2;
|
|
else if (strncmp (cpumodel, "EV5", 3) == 0)
|
|
io.sys = IOSYS_GAMMA;
|
|
}
|
|
else
|
|
{ /* this covers MIKASA/NORITAKE */
|
|
if (strncmp (cpumodel, "EV4", 3) == 0)
|
|
io.sys = IOSYS_APECS;
|
|
else if (strncmp (cpumodel, "EV5", 3) == 0)
|
|
io.sys = IOSYS_CIA;
|
|
}
|
|
if (io.sys == IOSYS_CPUDEP)
|
|
{
|
|
/* This can happen if the format of /proc/cpuinfo changes.*/
|
|
fprintf (stderr, "ioperm.init_iosys(): Unable to determine"
|
|
" CPU model.\n");
|
|
__set_errno (ENODEV);
|
|
return -1;
|
|
}
|
|
}
|
|
/* some platforms can have different core logic chipsets */
|
|
if (io.sys == IOSYS_PCIDEP) /* EB164 so far */
|
|
{
|
|
if (strcmp (systype, "EB164") == 0)
|
|
{
|
|
if (strncmp (sysvari, "RX164", 5) == 0)
|
|
io.sys = IOSYS_POLARIS;
|
|
else
|
|
io.sys = IOSYS_CIA;
|
|
}
|
|
if (io.sys == IOSYS_PCIDEP)
|
|
{
|
|
/* This can happen if the format of /proc/cpuinfo changes.*/
|
|
fprintf (stderr, "ioperm.init_iosys(): Unable to determine"
|
|
" core logic chipset.\n");
|
|
__set_errno (ENODEV);
|
|
return -1;
|
|
}
|
|
}
|
|
io.hae_shift = io_system[io.sys].hae_shift;
|
|
io.bus_memory_base = io_system[io.sys].bus_memory_base;
|
|
io.sparse_bus_memory_base = io_system[io.sys].sparse_bus_mem_base;
|
|
io.io_base = io_system[io.sys].bus_io_base;
|
|
|
|
if (io.sys == IOSYS_JENSEN)
|
|
io.swiz = IOSWIZZLE_JENSEN;
|
|
else if (io.sys == IOSYS_TSUNAMI || io.sys == IOSYS_POLARIS)
|
|
io.swiz = IOSWIZZLE_DENSE;
|
|
else
|
|
io.swiz = IOSWIZZLE_SPARSE;
|
|
io.swp = &ioswtch[io.swiz];
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* systype is not a know platform name... */
|
|
__set_errno (EINVAL);
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "init_iosys: platform not recognized\n");
|
|
#endif
|
|
return -1;
|
|
}
|
|
|
|
|
|
int
|
|
_ioperm (unsigned long int from, unsigned long int num, int turn_on)
|
|
{
|
|
unsigned long int addr, len;
|
|
int prot, err;
|
|
|
|
if (!io.swp && init_iosys() < 0) {
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "ioperm: init_iosys() failed\n");
|
|
#endif
|
|
return -1;
|
|
}
|
|
|
|
/* this test isn't as silly as it may look like; consider overflows! */
|
|
if (from >= MAX_PORT || from + num > MAX_PORT)
|
|
{
|
|
__set_errno (EINVAL);
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "ioperm: from/num out of range\n");
|
|
#endif
|
|
return -1;
|
|
}
|
|
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "ioperm: turn_on %d io.base %ld\n", turn_on, io.base);
|
|
#endif
|
|
|
|
if (turn_on)
|
|
{
|
|
if (!io.base)
|
|
{
|
|
int fd;
|
|
|
|
io.hae.reg = 0; /* not used in user-level */
|
|
io.hae.cache = 0;
|
|
if (io.swiz != IOSWIZZLE_DENSE)
|
|
__sethae (io.hae.cache); /* synchronize with hw */
|
|
|
|
fd = open ("/dev/mem", O_RDWR);
|
|
if (fd < 0) {
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "ioperm: /dev/mem open failed\n");
|
|
#endif
|
|
return -1;
|
|
}
|
|
|
|
addr = port_to_cpu_addr (0, io.swiz, 1);
|
|
len = port_to_cpu_addr (MAX_PORT, io.swiz, 1) - addr;
|
|
io.base =
|
|
(unsigned long int) __mmap (0, len, PROT_NONE, MAP_SHARED,
|
|
fd, io.io_base);
|
|
close (fd);
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "ioperm: mmap of len 0x%lx returned 0x%lx\n",
|
|
len, io.base);
|
|
#endif
|
|
if ((long) io.base == -1)
|
|
return -1;
|
|
}
|
|
prot = PROT_READ | PROT_WRITE;
|
|
}
|
|
else
|
|
{
|
|
if (!io.base)
|
|
return 0; /* never was turned on... */
|
|
|
|
/* turnoff access to relevant pages: */
|
|
prot = PROT_NONE;
|
|
}
|
|
addr = port_to_cpu_addr (from, io.swiz, 1);
|
|
addr &= PAGE_MASK;
|
|
len = port_to_cpu_addr (from + num, io.swiz, 1) - addr;
|
|
err = mprotect ((void *) addr, len, prot);
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "ioperm: mprotect returned %d\n", err);
|
|
#endif
|
|
return err;
|
|
}
|
|
|
|
|
|
int
|
|
_iopl (unsigned int level)
|
|
{
|
|
if (level > 3)
|
|
{
|
|
__set_errno (EINVAL);
|
|
return -1;
|
|
}
|
|
if (level)
|
|
{
|
|
return _ioperm (0, MAX_PORT, 1);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
void
|
|
_sethae (unsigned long int addr)
|
|
{
|
|
if (!io.swp && init_iosys () < 0)
|
|
return;
|
|
|
|
io.swp->sethae (addr);
|
|
}
|
|
|
|
|
|
void
|
|
_outb (unsigned char b, unsigned long int port)
|
|
{
|
|
if (port >= MAX_PORT)
|
|
return;
|
|
|
|
io.swp->outb (b, port);
|
|
}
|
|
|
|
|
|
void
|
|
_outw (unsigned short b, unsigned long int port)
|
|
{
|
|
if (port >= MAX_PORT)
|
|
return;
|
|
|
|
io.swp->outw (b, port);
|
|
}
|
|
|
|
|
|
void
|
|
_outl (unsigned int b, unsigned long int port)
|
|
{
|
|
if (port >= MAX_PORT)
|
|
return;
|
|
|
|
io.swp->outl (b, port);
|
|
}
|
|
|
|
|
|
unsigned int
|
|
_inb (unsigned long int port)
|
|
{
|
|
return io.swp->inb (port);
|
|
}
|
|
|
|
|
|
unsigned int
|
|
_inw (unsigned long int port)
|
|
{
|
|
return io.swp->inw (port);
|
|
}
|
|
|
|
|
|
unsigned int
|
|
_inl (unsigned long int port)
|
|
{
|
|
return io.swp->inl (port);
|
|
}
|
|
|
|
|
|
unsigned long int
|
|
_bus_base(void)
|
|
{
|
|
if (!io.swp && init_iosys () < 0)
|
|
return -1;
|
|
return io.bus_memory_base;
|
|
}
|
|
|
|
unsigned long int
|
|
_bus_base_sparse(void)
|
|
{
|
|
if (!io.swp && init_iosys () < 0)
|
|
return -1;
|
|
return io.sparse_bus_memory_base;
|
|
}
|
|
|
|
int
|
|
_hae_shift(void)
|
|
{
|
|
if (!io.swp && init_iosys () < 0)
|
|
return -1;
|
|
return io.hae_shift;
|
|
}
|
|
|
|
weak_alias (_sethae, sethae);
|
|
weak_alias (_ioperm, ioperm);
|
|
weak_alias (_iopl, iopl);
|
|
weak_alias (_inb, inb);
|
|
weak_alias (_inw, inw);
|
|
weak_alias (_inl, inl);
|
|
weak_alias (_outb, outb);
|
|
weak_alias (_outw, outw);
|
|
weak_alias (_outl, outl);
|
|
weak_alias (_bus_base, bus_base);
|
|
weak_alias (_bus_base_sparse, bus_base_sparse);
|
|
weak_alias (_hae_shift, hae_shift);
|