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linux-headers-5.4.0-3.6

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This commit is contained in:
Alibek Omarov 2021-08-26 01:47:50 +03:00
parent b732598e29
commit 6609503008
104 changed files with 2792 additions and 1633 deletions
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5
Makefile
View File

@ -2,7 +2,7 @@
VERSION = 5
PATCHLEVEL = 4
SUBLEVEL = 91
EXTRAVERSION = -2.13
EXTRAVERSION = -3.6
NAME = Kleptomaniac Octopus
# *DOCUMENTATION*
@ -506,9 +506,6 @@ KBUILD_CFLAGS := -Wall -Wundef -Werror=strict-prototypes -Wno-trigraphs \
-Wno-format-security \
-std=gnu89
endif
ifeq ($(call cc-lcc-yn),y)
KBUILD_CFLAGS += -fno-ident
endif
KBUILD_CPPFLAGS := -D__KERNEL__
KBUILD_AFLAGS_KERNEL :=
KBUILD_CFLAGS_KERNEL :=

11
arch/e2k/Makefile
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@ -17,7 +17,8 @@ LD = $(shell $(CC) -print-prog-name=ld)
OBJCOPY = $(shell $(CC) -print-prog-name=objcopy)
KBUILD_CFLAGS += -fkernel -gline -masm-inline $(call cc-option,-fforbid-fp) \
$(call cc-option,-fmax-errors=5) $(call cc-option,-fno-loop-apb)
$(call cc-option,-fmax-errors=5) $(call cc-option,-fno-loop-apb) \
-fno-ident
ifeq ($(PROFILE_GENERATE), 1)
KBUILD_CFLAGS += -fprofile-generate-kernel
@ -31,10 +32,10 @@ KBUILD_CFLAGS += $(call cc-option,-finline-functions,) \
$(call cc-option,-finline-functions-called-once,)
# Some uninteresting or broken warnings can be disabled with #pragma's only
KBUILD_CFLAGS += -Wno-array-bounds -Wno-duplicate-type-qualifier \
-Wno-builtin-functions-redefined -Wno-reduced-alignment \
-Wno-unused-value -Wno-overflow -Wno-signed-one-bit-field \
-include $(srctree)/arch/e2k/include/asm/override-lcc-warnings.h
KBUILD_CFLAGS += -Wno-array-bounds -Wno-builtin-functions-redefined \
-Wno-reduced-alignment -Wno-overflow -Wno-signed-one-bit-field \
-Wno-alignment-reduction-ignored \
-include $(srctree)/arch/e2k/include/asm/override-lcc-warnings.h
LDFLAGS_vmlinux :=
CHECKFLAGS += -D__e2k__

5
arch/e2k/include/asm-l/epic.h
View File

@ -67,6 +67,11 @@ static inline bool read_epic_bsp(void)
return reg.bits.bsp_core;
}
static inline u32 epic_vector_prio(u32 vector)
{
return 1 + ((vector >> 8) & 0x3);
}
extern void __init_recv setup_prepic(void);
extern void ack_epic_irq(void);
extern void epic_send_IPI(unsigned int dest_id, int vector);

20
arch/e2k/include/asm-l/epic_regs.h
View File

@ -79,9 +79,9 @@ union cepic_epic_int2 {
dlvm : 3,
__reserved2 : 4,
gst_id : 12,
__reserved3 : 12,
__reserved3 : 8,
gst_dst : 10,
__reserved4 : 10;
__reserved4 : 14;
} __packed bits;
};
@ -323,12 +323,12 @@ typedef struct kvm_epic_page {
u32 id;
u32 cpr;
u32 esr;
u32 esr2;
u32 cir;
union cepic_esr2 esr2;
union cepic_cir cir;
atomic_t esr_new;
u32 svr;
u64 icr;
u32 timer_lvtt;
union cepic_icr icr;
union cepic_timer_lvtt timer_lvtt;
u32 timer_init;
u32 timer_cur;
u32 timer_div;
@ -338,13 +338,13 @@ typedef struct kvm_epic_page {
u32 nm_timer_div;
u32 pnmirr_mask;
/*04c*/ u32 __reserved1[45];
/*100*/ atomic64_t pmirr[16];
/*100*/ atomic64_t pmirr[CEPIC_PMIRR_NR_DREGS];
/*180*/ u32 __reserved2[24];
/*1e0*/ atomic_t pnmirr;
u32 __reserved3[263];
/*600*/ u8 pnmirr_byte[16];
/*610*/ u32 __reserved4[124];
/*800*/ u8 pmirr_byte[1024];
/*800*/ u8 pmirr_byte[CEPIC_PMIRR_NR_BITS];
} epic_page_t;
#elif defined(__BIG_ENDIAN)
@ -417,9 +417,9 @@ union cepic_epic_int {
union cepic_epic_int2 {
u64 raw;
struct {
u64 __reserved4 : 10,
u64 __reserved4 : 14,
gst_dst : 10,
__reserved3 : 12,
__reserved3 : 8,
gst_id : 12,
__reserved2 : 4,
dlvm : 3,

2
arch/e2k/include/asm-l/l_pmc.h
View File

@ -124,7 +124,7 @@ struct l_pmc {
extern struct l_pmc l_pmc[MAX_NUM_PMCS];
#if defined(CONFIG_L_PMC) || defined(CONFIG_S2_PMC)
#if defined(CONFIG_L_PMC_MODULE) || defined(CONFIG_L_PMC) || defined(CONFIG_S2_PMC)
extern int spmc_get_temp_cur0(void);
int pmc_l_gpufreq_set_scale(unsigned char scale);
int pmc_l_gpufreq_get_scale(void);

1
arch/e2k/include/asm-l/l_timer.h
View File

@ -46,6 +46,7 @@ typedef struct lt_regs {
extern unsigned long long lt_phys_base;
extern lt_regs_t *lt_regs;
extern long lt_clock_rate;
extern void setup_lt_timer(void);
extern int __init init_lt_clocksource(void);

1
arch/e2k/include/asm-l/mpspec.h
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@ -378,6 +378,7 @@ extern int mp_find_iolink_io_apicid(int node, int link);
extern int mp_fix_io_apicid(unsigned int src_apicid, unsigned int new_apicid);
void mp_pci_add_resources(struct list_head *resources,
struct iohub_sysdata *sd);
extern int mp_iohubs_num;
#else
static inline int mp_fix_io_apicid(unsigned int src_apicid,
unsigned int new_apicid)

6
arch/e2k/include/asm/aau_regs_access.h
View File

@ -537,14 +537,14 @@ do { \
\
/* prefetch data to restore */ \
if (AS(aasr).stb) \
prefetchw_range(aau->aastis, sizeof(aau->aastis) + \
prefetch_nospec_range(aau->aastis, sizeof(aau->aastis) + \
sizeof(aau->aasti_tags)); \
if (AS(aasr).iab) \
prefetchw_range(aau->aainds, sizeof(aau->aainds) + \
prefetch_nospec_range(aau->aainds, sizeof(aau->aainds) + \
sizeof(aau->aaind_tags) + sizeof(aau->aaincrs) + \
sizeof(aau->aaincr_tags) + sizeof(aau->aads)); \
if (AAU_STOPPED(aasr)) \
prefetchw_range(aau->aaldi, sizeof(aau->aaldi)); \
prefetch_nospec_range(aau->aaldi, sizeof(aau->aaldi)); \
\
/* Make sure prefetches are issued */ \
barrier(); \

19
arch/e2k/include/asm/alternative.h
View File

@ -177,14 +177,19 @@ void apply_alternatives(struct alt_instr *start, struct alt_instr *end);
* oldinstr is padded with jump and nops at compile time if altinstr is
* longer. altinstr is padded with jump and nops at run-time during patching.
*/
#define alternative(oldinstr, altinstr, facility, clobbers...) \
asm volatile (ALTERNATIVE(oldinstr, altinstr, facility) \
::: clobbers)
#define alternative(oldinstr, altinstr, _facility, clobbers...) \
_Pragma("no_asm_inline") \
asm volatile (ALTERNATIVE(oldinstr, altinstr, %[facility]) \
:: [facility] "i" (_facility) : clobbers)
#define alternative_2(oldinstr, altinstr1, facility1, altinstr2, facility2) \
asm volatile (ALTERNATIVE_2(oldinstr, altinstr1, facility1, \
altinstr2, facility2) \
::: clobbers)
#define alternative_2(oldinstr, altinstr1, _facility1, altinstr2, _facility2) \
_Pragma("no_asm_inline") \
asm volatile (ALTERNATIVE_2(oldinstr, altinstr1, %[facility1], \
altinstr2, %[facility2]) \
: \
: [facility1] "i" (_facility1), \
[facility2] "i" (_facility2) \
: clobbers)
/*
* How to use:

17
arch/e2k/include/asm/barrier.h
View File

@ -4,17 +4,18 @@
#include <linux/compiler.h>
#include <asm/e2k_api.h>
#include <asm/alternative.h>
#include <asm/atomic_api.h>
#if CONFIG_CPU_ISET >= 6
/* Cannot use this on V5 because of load-after-store dependencies -
* compiled kernel won't honour them */
# define mb() E2K_WAIT_V6(_st_c | _ld_c | _sas | _sal | _las | _lal)
# define mb() E2K_WAIT(_st_c | _ld_c | _sas | _sal | _las | _lal)
#else
# define mb() E2K_WAIT(_st_c | _ld_c)
#endif
#define wmb() E2K_WAIT_ST_C_SAS()
#define rmb() E2K_WAIT_LD_C_LAL()
#define wmb() E2K_WAIT(_st_c | _sas)
#define rmb() E2K_WAIT(_ld_c | _lal)
/*
* For smp_* variants add _mt modifier
@ -22,12 +23,12 @@
#if CONFIG_CPU_ISET >= 6
/* Cannot use this on V5 because of load-after-store dependencies -
* compiled kernel won't honour them */
# define __smp_mb() E2K_WAIT_V6(_st_c | _ld_c | _sas | _sal | _las | _lal | _mt)
# define __smp_mb() E2K_WAIT(_st_c | _ld_c | _sas | _sal | _las | _lal | _mt)
#else
# define __smp_mb() E2K_WAIT(_st_c | _ld_c)
#endif
#define __smp_wmb() E2K_WAIT_ST_C_SAS_MT()
#define __smp_rmb() E2K_WAIT_LD_C_LAL_MT()
#define __smp_wmb() E2K_WAIT(_st_c | _sas | _mt)
#define __smp_rmb() E2K_WAIT(_ld_c | _lal | _mt)
#define dma_rmb() __smp_rmb()
#define dma_wmb() __smp_wmb()
@ -37,7 +38,7 @@
#if CONFIG_CPU_ISET >= 5
# define __smp_mb__after_atomic() barrier()
# define __smp_mb__before_atomic() E2K_WAIT_ST_C_SAS_LD_C_SAL_MT()
# define __smp_mb__before_atomic() E2K_WAIT(_st_c | _las | _ld_c | _lal | _mt)
#elif CONFIG_CPU_ISET >= 3
/* Atomic operations are serializing since e2s */
# define __smp_mb__after_atomic() \
@ -70,7 +71,7 @@ do { \
compiletime_assert(sizeof(*p) == 1 || sizeof(*p) == 2 || \
sizeof(*p) == 4 || sizeof(*p) == 8, \
"Need native word sized stores/loads for atomicity."); \
E2K_WAIT_ST_C_SAS_LD_C_SAL_MT(); \
E2K_WAIT(_st_c | _sas | _ld_c | _sal | _mt); \
WRITE_ONCE(*(p), (v)); \
} while (0)
#endif /* CONFIG_CPU_ISET >= 6 */

2
arch/e2k/include/asm/checksum.h
View File

@ -112,7 +112,7 @@ static inline __wsum csum_partial(const void *buff, int len, __wsum sum)
!cpu_has(CPU_HWBUG_UNALIGNED_LOADS)) {
sum = csum_add(sum, ip_fast_csum_nofold_maybe_unaligned(buff, len >> 2));
} else {
E2K_PREFETCH_L1((__force void *) buff);
prefetch((__force void *) buff);
sum = __csum_partial(buff, len, sum);
}
return sum;

1
arch/e2k/include/asm/console.h
View File

@ -8,6 +8,7 @@
#include <linux/init.h>
#include <asm/types.h>
#include <stdarg.h>
#include <asm/cpu_regs.h>
#include <asm/machdep.h>
#include <asm-l/console.h>
#include <asm/kvm/guest/console.h>

10
arch/e2k/include/asm/copy-hw-stacks.h
View File

@ -214,7 +214,7 @@ native_collapse_kernel_ps(u64 *dst, const u64 *src, u64 spilled_size)
size = k_psp_hi.PSP_hi_ind - spilled_size;
BUG_ON(!IS_ALIGNED(size, ALIGN_PSTACK_TOP_SIZE) || (s64) size < 0);
prefetchw_range(src, size);
prefetch_nospec_range(src, size);
native_kernel_hw_stack_frames_copy(dst, src, size);
k_psp_hi.PSP_hi_ind -= spilled_size;
@ -327,7 +327,7 @@ static inline int __copy_user_to_current_hw_stack(void *dst, void __user *src,
E2K_FLUSHR;
SET_USR_PFAULT("$.recovery_memcpy_fault");
fast_tagged_memory_copy_from_user(dst, src, size, regs,
fast_tagged_memory_copy_from_user(dst, src, size, NULL, regs,
TAGGED_MEM_STORE_REC_OPC |
MAS_BYPASS_L1_CACHE << LDST_REC_OPC_MAS_SHIFT,
TAGGED_MEM_LOAD_REC_OPC |
@ -395,8 +395,8 @@ static inline int copy_e2k_stack_to_user(void __user *dst, void *src,
}
static __always_inline int
user_hw_stack_frames_copy(void __user *dst, void *src, unsigned long copy_size,
const pt_regs_t *regs, unsigned long hw_stack_ind, bool is_pcsp)
user_hw_stack_frames_copy(void __user *dst, void *src, long copy_size,
const pt_regs_t *regs, long hw_stack_ind, bool is_pcsp)
{
unsigned long ts_flag;
@ -414,7 +414,7 @@ user_hw_stack_frames_copy(void __user *dst, void *src, unsigned long copy_size,
SET_USR_PFAULT("$.recovery_memcpy_fault");
ts_flag = set_ts_flag(TS_KERNEL_SYSCALL);
fast_tagged_memory_copy_to_user(dst, src, copy_size, regs,
fast_tagged_memory_copy_to_user(dst, src, copy_size, NULL, regs,
TAGGED_MEM_STORE_REC_OPC |
MAS_BYPASS_L1_CACHE << LDST_REC_OPC_MAS_SHIFT,
TAGGED_MEM_LOAD_REC_OPC |

99
arch/e2k/include/asm/cpu_regs.h
View File

@ -6,11 +6,54 @@
#include <asm/types.h>
#include <asm/cpu_regs_types.h>
#include <asm/cpu_regs_access.h>
#ifndef __ASSEMBLY__
#include <asm/e2k_api.h>
#include <asm/e2k.h>
/*
* Read Core Mode Register (CORE_MODE) to the structure
* Register fields access: fff = AS_STRACT(CORE_MODE).xxx
* Register entire access: reg_entire = AS_WORD(CORE_MODE)
*/
#define NATIVE_READ_CORE_MODE_REG() \
({ \
e2k_core_mode_t CORE_MODE; \
CORE_MODE.CORE_MODE_reg = NATIVE_READ_CORE_MODE_REG_VALUE(); \
CORE_MODE; \
})
#define READ_CORE_MODE_REG() \
({ \
e2k_core_mode_t CORE_MODE; \
CORE_MODE.CORE_MODE_reg = READ_CORE_MODE_REG_VALUE(); \
CORE_MODE; \
})
#define BOOT_READ_CORE_MODE_REG() \
({ \
e2k_core_mode_t CORE_MODE; \
CORE_MODE.CORE_MODE_reg = BOOT_READ_CORE_MODE_REG_VALUE(); \
CORE_MODE; \
})
/* Fix header dependency hell. cpu_regs_access.h eventually includes
* macros for paravirtualized guest which in turn rely on IS_HV_GM(),
* and IS_HV_GM() relies in READ_CORE_MODE_REG() defined in this file. */
#include <asm/cpu_regs_access.h>
/*
* Write Core Mode Register (CORE_MODE) from the structure
* Register fields filling: AS_STRACT(CORE_MODE).xxx = fff
* Register entire filling: AS_WORD(CORE_MODE) = CORE_MODE_value
*/
#define NATIVE_WRITE_CORE_MODE_REG(CORE_MODE) \
NATIVE_WRITE_CORE_MODE_REG_VALUE(CORE_MODE.CORE_MODE_reg)
#define BOOT_NATIVE_WRITE_CORE_MODE_REG(CORE_MODE) \
BOOT_NATIVE_WRITE_CORE_MODE_REG_VALUE(CORE_MODE.CORE_MODE_reg)
#define WRITE_CORE_MODE_REG(CORE_MODE) \
WRITE_CORE_MODE_REG_VALUE(CORE_MODE.CORE_MODE_reg)
#define BOOT_WRITE_CORE_MODE_REG(CORE_MODE) \
BOOT_WRITE_CORE_MODE_REG_VALUE(CORE_MODE.CORE_MODE_reg)
#define NATIVE_STRIP_PCSHTP_WINDOW() NATIVE_WRITE_PCSHTP_REG_SVALUE(0)
#define STRIP_PCSHTP_WINDOW() WRITE_PCSHTP_REG_SVALUE(0)
@ -2965,11 +3008,11 @@ native_boot_init_BGR_reg(void)
/*
* Read/Write Control Unit HardWare registers (CU_HW0/CU_HW1)
*/
#define READ_CU_HW0_REG() READ_CU_HW0_REG_VALUE()
#define READ_CU_HW1_REG() READ_CU_HW1_REG_VALUE()
#define READ_CU_HW0_REG() ((e2k_cu_hw0_t) { .word = READ_CU_HW0_REG_VALUE() })
#define READ_CU_HW1_REG() READ_CU_HW1_REG_VALUE()
#define WRITE_CU_HW0_REG(reg) WRITE_CU_HW0_REG_VALUE(reg)
#define WRITE_CU_HW1_REG(reg) WRITE_CU_HW1_REG_VALUE(reg)
#define WRITE_CU_HW0_REG(reg) WRITE_CU_HW0_REG_VALUE(reg.word)
#define WRITE_CU_HW1_REG(reg) WRITE_CU_HW1_REG_VALUE(reg)
/*
* Read low/high double-word Recovery point register (RPR)
@ -3194,11 +3237,7 @@ write_DIBSR_reg(e2k_dibsr_t DIBSR)
#define NATIVE_WRITE_DIMCR_REG(DIMCR) \
NATIVE_WRITE_DIMCR_REG_VALUE(DIMCR.DIMCR_reg)
#define WRITE_DIMCR_REG(DIMCR) WRITE_DIMCR_REG_VALUE(DIMCR.DIMCR_reg)
static inline void
write_DIMCR_reg(e2k_dimcr_t DIMCR)
{
WRITE_DIMCR_REG(DIMCR);
}
#define NATIVE_WRITE_DIBAR0_REG(DIBAR0) NATIVE_WRITE_DIBAR0_REG_VALUE(DIBAR0)
#define NATIVE_WRITE_DIBAR1_REG(DIBAR1) NATIVE_WRITE_DIBAR1_REG_VALUE(DIBAR1)
#define NATIVE_WRITE_DIBAR2_REG(DIBAR2) NATIVE_WRITE_DIBAR2_REG_VALUE(DIBAR2)
@ -3314,44 +3353,6 @@ read_CUIR_reg(void)
return READ_CUIR_REG();
}
/*
* Read Core Mode Register (CORE_MODE) to the structure
* Register fields access: fff = AS_STRACT(CORE_MODE).xxx
* Register entire access: reg_entire = AS_WORD(CORE_MODE)
*/
#define NATIVE_READ_CORE_MODE_REG() \
({ \
e2k_core_mode_t CORE_MODE; \
CORE_MODE.CORE_MODE_reg = NATIVE_READ_CORE_MODE_REG_VALUE(); \
CORE_MODE; \
})
#define READ_CORE_MODE_REG() \
({ \
e2k_core_mode_t CORE_MODE; \
CORE_MODE.CORE_MODE_reg = READ_CORE_MODE_REG_VALUE(); \
CORE_MODE; \
})
#define BOOT_READ_CORE_MODE_REG() \
({ \
e2k_core_mode_t CORE_MODE; \
CORE_MODE.CORE_MODE_reg = BOOT_READ_CORE_MODE_REG_VALUE(); \
CORE_MODE; \
})
/*
* Write Core Mode Register (CORE_MODE) from the structure
* Register fields filling: AS_STRACT(CORE_MODE).xxx = fff
* Register entire filling: AS_WORD(CORE_MODE) = CORE_MODE_value
*/
#define NATIVE_WRITE_CORE_MODE_REG(CORE_MODE) \
NATIVE_WRITE_CORE_MODE_REG_VALUE(CORE_MODE.CORE_MODE_reg)
#define BOOT_NATIVE_WRITE_CORE_MODE_REG(CORE_MODE) \
BOOT_NATIVE_WRITE_CORE_MODE_REG_VALUE(CORE_MODE.CORE_MODE_reg)
#define WRITE_CORE_MODE_REG(CORE_MODE) \
WRITE_CORE_MODE_REG_VALUE(CORE_MODE.CORE_MODE_reg)
#define BOOT_WRITE_CORE_MODE_REG(CORE_MODE) \
BOOT_WRITE_CORE_MODE_REG_VALUE(CORE_MODE.CORE_MODE_reg)
/*
* Read word Processor State Register (PSR) to the structure
* Register fields access: fff = AS_STRACT(PSR).xxx

257
arch/e2k/include/asm/cpu_regs_types.h
View File

@ -991,29 +991,26 @@ typedef union instr_hs {
u32 __pad : 14;
u32 c0 : 1; /* CS0 */
u32 c1 : 1; /* CS1 */
u32 __pad2 : 16;
u32 __pad2 : 4;
u32 ale0 : 1;
u32 ale1 : 1;
u32 ale2 : 1;
u32 ale3 : 1;
u32 ale4 : 1;
u32 ale5 : 1;
u32 al0 : 1;
u32 al1 : 1;
u32 al2 : 1;
u32 al3 : 1;
u32 al4 : 1;
u32 al5 : 1;
};
struct {
u32 mdl : 4;
u32 lng : 3;
u32 nop : 3;
u32 lm : 1;
u32 x : 1;
u32 s : 1;
u32 sw : 1;
u32 c : 2;
u32 cd : 2;
u32 pl : 2;
u32 ale : 6;
u32 al : 6;
} fields;
instr_syl_t word; /* as entire syllable */
instr_syl_t word; /* as entire syllable */
} instr_hs_t;
#define E2K_INSTR_HS_LNG_MASK 0x70
#define E2K_GET_INSTR_SIZE(hs) \
((AS_STRUCT(hs).lng + 1) * sizeof(instr_item_t))
#define E2K_GET_INSTR_SIZE(hs) ((hs.lng + 1) * sizeof(instr_item_t))
/*
* Stubs sullable structure
@ -1037,23 +1034,6 @@ typedef union instr_ss {
u32 eap : 1; /* [29] end array prefetch */
u32 ipd : 2; /* [31:30] instruction prefetch depth */
};
struct {
u32 ctcond : 9;
u32 x : 1;
u32 ctop : 2;
u32 aa : 4;
u32 alc : 2;
u32 abp : 2;
u32 xx : 1;
u32 abn : 2;
u32 abg : 2;
u32 xxx : 1;
u32 vfdi : 1;
u32 srp : 1;
u32 bap : 1;
u32 eap : 1;
u32 ipd : 2;
} fields;
instr_syl_t word; /* as entire syllable */
} instr_ss_t;
@ -1061,39 +1041,45 @@ typedef union instr_ss {
* ALU syllables structure
*/
typedef struct instr_alsf2_fields {
u32 dst : 8; /* [ 7: 0] destination */
u32 src2 : 8; /* [15: 8] source register #2 */
u32 opce : 8; /* [23:16] opcode extension */
u32 cop : 7; /* [30:24] code of operation */
u32 spec : 1; /* [31] speculative mode */
} instr_alsf2_fields_t;
typedef union instr_alsf2 {
instr_alsf2_fields_t fields; /* as fields */
instr_syl_t word; /* as entire syllable */
} instr_alsf2_t;
typedef union instr_als {
instr_alsf2_fields_t f2; /* as fields */
instr_syl_t word; /* as entire syllable */
typedef union {
union {
struct {
u32 dst : 8; /* [ 7: 0] destination */
u32 src2 : 8; /* [15: 8] source register #2 */
u32 opce : 8; /* [23:16] opcode extension */
u32 cop : 7; /* [30:24] code of operation */
u32 spec : 1; /* [31] speculative mode */
};
struct {
u32 : 24;
u32 opc : 8;
};
} alf2;
instr_syl_t word; /* as entire syllable */
} instr_als_t;
typedef struct instr_alesf2_fields {
u32 opce : 8; /* [ 7: 0] opcode 2 extension */
u32 opc2 : 8; /* [15: 8] opcode 2 */
} instr_alesf2_fields_t;
typedef union instr_alesf2 {
instr_alesf2_fields_t fields; /* as fields */
instr_semisyl_t word; /* as entire syllable */
} instr_alesf2_t;
typedef union instr_ales {
instr_alesf2_fields_t f2; /* as fields */
instr_semisyl_t word; /* as entire syllable */
struct {
u16 src3 : 8;
u16 opc2 : 8;
} alef1;
struct {
u16 opce : 8;
u16 opc2 : 8;
} alef2;
instr_semisyl_t word; /* as entire syllable */
} instr_ales_t;
typedef union {
struct {
u8 __pad : 5;
u8 rt5 : 1;
u8 rt6 : 1;
u8 rt7 : 1;
};
u8 word;
} instr_src_t;
#define INSTR_SRC2_GREG_VALUE 0xe0
#define INSTR_SRC2_GREG_MASK 0xe0
#define INSTR_SRC2_GREG_NUM_MASK 0x1f
@ -1176,6 +1162,7 @@ typedef union {
} instr_cs1_t;
#define CS1_OPC_SETEI 2
#define CS1_OPC_WAIT 3
#define CS1_OPC_CALL 5
@ -1226,6 +1213,15 @@ struct e2k_wd_fields {
/* Current window descriptor (WD) */
typedef union e2k_wd {
struct {
u64 : 3;
u64 base_d : E2K_WD_SIZE - 3;
u64 : 16 - E2K_WD_SIZE + 3;
u64 size_d : E2K_WD_SIZE - 3;
u64 : 16 - E2K_WD_SIZE + 3;
u64 psize_d : E2K_WD_SIZE - 3;
u64 : 32 - E2K_WD_SIZE;
};
struct {
u64 base : E2K_WD_SIZE; /* [10: 0] window base: */
/* %r0 physical address */
@ -1388,6 +1384,13 @@ typedef struct e2k_br_fields { /* Structure of br reg */
u32 pcur : 5; /* [27:23] */
} e2k_br_fields_t;
typedef union e2k_br {
struct {
u32 rbs : 6;
u32 rsz : 6;
u32 rcur : 6;
u32 psz : 5;
u32 pcur : 5;
};
e2k_br_fields_t fields; /* as fields */
u32 word; /* as entire register */
} e2k_br_t;
@ -1398,6 +1401,11 @@ typedef union e2k_br {
#define BR_pcur fields.pcur
#define BR_reg word
static inline int br_rsz_full_d(e2k_br_t br)
{
return 2 * (br.rsz + 1);
}
/* see 5.25.1. */
typedef union e2k_rpr_lo_struct {
@ -1456,11 +1464,15 @@ typedef union e2k_bgr {
/* CR0 */
typedef struct e2k_cr0_hi_fields { /* Structure of cr0_hi chain reg */
typedef struct { /* Structure of cr0_hi chain reg */
u64 unused : 3; /* [ 2: 0] */
u64 ip : 61; /* [63: 3] */
} e2k_cr0_hi_fields_t;
typedef union e2k_cr0_hi {
typedef union {
struct {
u64 : 3;
u64 ip : 61;
};
e2k_cr0_hi_fields_t fields; /* as fields */
u64 word; /* as entire register */
} e2k_cr0_hi_t;
@ -1468,10 +1480,10 @@ typedef union e2k_cr0_hi {
#define CR0_hi_half word /* [63: 0] - entire high */
#define CR0_hi_IP CR0_hi_half /* [63: 0] - IP */
typedef struct e2k_cr0_lo_fields { /* Structure of cr0_lo chain reg */
typedef struct { /* Structure of cr0_lo chain reg */
u64 pf : 64; /* [63: 0] */
} e2k_cr0_lo_fields_t;
typedef union e2k_cr0_lo {
typedef union {
e2k_cr0_lo_fields_t fields; /* as fields */
u64 word; /* as entire register */
} e2k_cr0_lo_t;
@ -1480,7 +1492,7 @@ typedef union e2k_cr0_lo {
/* CR1 */
typedef union e2k_cr1_hi_fields { /* Structure of cr1_hi chain reg */
typedef union { /* Structure of cr1_hi chain reg */
struct {
u64 br : 28; /* [27: 0] */
u64 unused : 7; /* [34:28] */
@ -1496,7 +1508,21 @@ typedef union e2k_cr1_hi_fields { /* Structure of cr1_hi chain reg */
u64 __x1 : 36; /* [63:28] */
};
} e2k_cr1_hi_fields_t;
typedef union e2k_cr1_hi {
typedef union {
struct {
u64 br : 28;
u64 : 7;
u64 wdbl : 1;
u64 ussz : 28;
};
struct {
u64 rbs : 6;
u64 rsz : 6;
u64 rcur : 6;
u64 psz : 5;
u64 pcur : 5;
u64 : 36;
};
e2k_cr1_hi_fields_t fields; /* as fields */
u64 word; /* as entire register */
} e2k_cr1_hi_t;
@ -1510,7 +1536,7 @@ typedef union e2k_cr1_hi {
#define CR1_hi_pcur fields.pcur /* [27:23] - current of rotate preds */
#define CR1_hi_half word /* [63: 0] - entire high */
typedef union e2k_cr1_lo_fields { /* Structure of cr1_lo chain reg */
typedef union { /* Structure of cr1_lo chain reg */
struct {
u64 unused1 : 16; /* [15:0] */
u64 ein : 8; /* [23:16] */
@ -1535,7 +1561,29 @@ typedef union e2k_cr1_lo_fields { /* Structure of cr1_lo chain reg */
/* enable */
};
} e2k_cr1_lo_fields_t;
typedef union e2k_cr1_lo {
typedef union {
struct {
u64 : 16;
u64 ein : 8;
u64 ss : 1;
u64 wfx : 1;
u64 wpsz : 7;
u64 wbs : 7;
u64 cuir : 17;
u64 psr : 7;
};
struct {
u64 : 40;
u64 cui : 16;
u64 ic : 1; /* iset <= v5 */
u64 pm : 1;
u64 ie : 1;
u64 sge : 1;
u64 lw : 1;
u64 uie : 1;
u64 nmie : 1;
u64 unmie : 1;
};
e2k_cr1_lo_fields_t fields; /* as fields */
u64 word; /* as entire register */
} e2k_cr1_lo_t;
@ -1655,7 +1703,7 @@ typedef union {
/* PSR */
typedef struct e2k_psr_fields { /* Structure of psr reg */
typedef struct {
u32 pm : 1; /* [ 0] */
u32 ie : 1; /* [ 1] */
u32 sge : 1; /* [ 2] */
@ -1666,7 +1714,17 @@ typedef struct e2k_psr_fields { /* Structure of psr reg */
/* enable */
u32 unused : 25; /* [31: 7] */
} e2k_psr_fields_t;
typedef union e2k_psr {
typedef union {
struct {
u32 pm : 1;
u32 ie : 1;
u32 sge : 1;
u32 lw : 1;
u32 uie : 1;
u32 nmie : 1;
u32 unmie : 1;
u32 : 25;
};
e2k_psr_fields_t fields; /* as fields */
u32 word; /* as entire register */
} e2k_psr_t;
@ -1901,6 +1959,35 @@ typedef struct e2k_mem_crstack {
#define SZ_OF_CR sizeof(e2k_mem_crs_t)
typedef union {
struct {
u64 trwm_itag : 3;
u64 trwm_idata : 3;
u64 trwm_cf : 3;
u64 ib_snoop_dsbl : 1;
u64 bist_cf : 1;
u64 bist_tu : 1;
u64 bist_itag : 1;
u64 bist_itlbtag : 1;
u64 bist_itlbdata : 1;
u64 bist_idata_nm : 4;
u64 bist_idata_cnt : 10;
u64 pipe_frz_dsbl : 1; /* Since iset v5 */
u64 rf_clean_dsbl : 1;
/* iset v6 */
u64 virt_dsbl : 1;
u64 upt_sec_ad_shift_dsbl : 1;
u64 pdct_stat_enbl : 1;
u64 pdct_dyn_enbl : 1;
u64 pdct_rbr_enbl : 1;
u64 pdct_ret_enbl : 1;
u64 pdct_retst_enbl : 1;
u64 pdct_cond_enbl : 1;
};
u64 word;
} e2k_cu_hw0_t;
/*
* Trap Info Registers
*/
@ -2260,6 +2347,12 @@ typedef union {
} e2k_dimcr_t;
#define DIMCR_reg word
static inline bool dimcr_enabled(e2k_dimcr_t dimcr, int monitor)
{
return (monitor == 0) ? (AS(dimcr)[0].user || AS(dimcr)[0].system)
: (AS(dimcr)[1].user || AS(dimcr)[1].system);
}
typedef union {
struct {
u32 b0 : 1;
@ -2356,24 +2449,6 @@ typedef struct e2k_svd_gregs_struct {
u8 tag; /* any time too */
} e2k_svd_gregs_t;
/* CU_HW0 register */
#define _CU_HW0_TRWM_ITAG_MASK 0x000000007 /* IB tag */
#define _CU_HW0_TRWM_IDATA_MASK 0x000000038 /* IB data */
#define _CU_HW0_TRWM_CF_MASK 0x0000001c0 /* Chain File */
#define _CU_HW0_IB_SNOOP_DISABLE_MASK 0x000000200 /* Disable IB snooping */
#define _CU_HW0_BIST_CF_MASK 0x000000400 /* Chain File */
#define _CU_HW0_BIST_TU_MASK 0x000000800 /* Trap Unit */
#define _CU_HW0_BIST_ITAG_MASK 0x000001000 /* IB tag */
#define _CU_HW0_BIST_ITLB_TAG_MASK 0x000002000 /* ITLB tag */
#define _CU_HW0_BIST_ITLB_DATA_MASK 0x000004000 /* ITLB data */
#define _CU_HW0_BIST_IDATA_NM_MASK 0x000078000 /* IB data */
#define _CU_HW0_BIST_IDATA_CNT_MASK 0x01ff80000 /* IB tag */
#define _CU_HW0_PIPE_FROST_DISABLE_MASK 0x020000000 /* Instruction pipe */
#define _CU_HW0_RF_CLEAN_DISABLE_MASK 0x040000000 /* Register File */
#define _CU_HW0_VIRT_DISABLE_MASK 0x080000000 /* Disable hardware */
/* virtualization support */
#define _CU_HW0_UPT_SEC_AD_SHIFT_DSBL_MASK 0x100000000 /* Disable address shift in */
/* MMU_CR.upt mode */
struct hw_stacks {
e2k_psp_lo_t psp_lo;

712
arch/e2k/include/asm/e2k_api.h
View File

@ -3,6 +3,7 @@
#include <linux/stringify.h>
#include <asm/mas.h>
#include <uapi/asm/e2k_api.h>
#ifndef __ASSEMBLY__
@ -1330,12 +1331,30 @@ do { \
#define STORE_NV_MAS(_addr, _val, _mas, size_letter, clobber) \
do { \
_Pragma("no_asm_inline") \
asm NOT_VOLATILE ("st" #size_letter" %[addr], %[val], mas=%[mas]" \
: [addr] "=m" (*(_addr)) \
: [val] "r" (_val), \
[mas] "i" (_mas) \
: clobber); \
if ((_mas) == MAS_STORE_RELEASE_V6(MAS_MT_0) || \
(_mas) == MAS_STORE_RELEASE_V6(MAS_MT_1)) { \
_Pragma("no_asm_inline") \
asm NOT_VOLATILE ( \
ALTERNATIVE( \
/* Default version */ \
"{wait st_c=1, ld_c=1\n" \
" st" #size_letter" %[addr], %[val]}", \
/* CPU_NO_HWBUG_SOFT_WAIT version */ \
"{st" #size_letter" %[addr], %[val], mas=%[mas]}", \
%[facility]) \
: [addr] "=m" (*(_addr)) \
: [val] "r" (_val), \
[mas] "i" (_mas), \
[facility] "i" (CPU_NO_HWBUG_SOFT_WAIT) \
: clobber); \
} else { \
_Pragma("no_asm_inline") \
asm NOT_VOLATILE ("st" #size_letter" %[addr], %[val], mas=%[mas]" \
: [addr] "=m" (*(_addr)) \
: [val] "r" (_val), \
[mas] "i" (_mas) \
: clobber); \
} \
} while (0)
/*
@ -1352,12 +1371,12 @@ do { \
# define READ_MAS_BARRIER_AFTER(mas) \
do { \
if ((mas) == MAS_IOADDR) \
E2K_WAIT_LD_C_LAL_SAL(); \
__E2K_WAIT(_ld_c | _lal | _sal); \
} while (0)
# define WRITE_MAS_BARRIER_BEFORE(mas) \
do { \
if ((mas) == MAS_IOADDR) \
E2K_WAIT_ST_C_SAS_LD_C_SAL(); \
__E2K_WAIT(_st_c | _sas | _ld_c | _sal); \
} while (0)
/*
* Not required by documentation, but this is how
@ -1366,7 +1385,7 @@ do { \
# define WRITE_MAS_BARRIER_AFTER(mas) \
do { \
if ((mas) == MAS_IOADDR) \
E2K_WAIT_ST_C_SAS(); \
__E2K_WAIT(_st_c | _sas); \
} while (0)
#elif CONFIG_CPU_ISET == 0
@ -1379,7 +1398,7 @@ do { \
# define WRITE_MAS_BARRIER_BEFORE(mas) \
do { \
if ((mas) == MAS_IOADDR) \
__E2K_WAIT(_st_c | _ld_c); \
__E2K_WAIT(_st_c | _sas | _ld_c | _sal); \
} while (0)
/*
* Not required by documentation, but this is how
@ -1388,7 +1407,7 @@ do { \
# define WRITE_MAS_BARRIER_AFTER(mas) \
do { \
if ((mas) == MAS_IOADDR) \
__E2K_WAIT(_st_c); \
__E2K_WAIT(_st_c | _sas); \
} while (0)
#else
@ -1519,10 +1538,6 @@ do { \
})
/*
* Prefetching with fully speculative load is
* needed when the passed address can be invalid.
*/
#if !defined(CONFIG_BOOT_E2K) && !defined(E2K_P2V)
# define E2K_PREFETCH_L2_SPEC(addr) \
do { \
@ -1533,42 +1548,23 @@ do { \
"i" (MAS_LOAD_SPEC | MAS_BYPASS_L1_CACHE)); \
} while (0)
# define E2K_PREFETCH_L2_SPEC_OFFSET(addr, offset) \
# define E2K_PREFETCH_L2_NOSPEC_OFFSET(addr, offset) \
do { \
int unused; \
asm ("ldb,sm %1, %2, %%empty, mas=%3\n" \
: "=r" (unused) \
: "r" (addr), \
"i" (offset), \
"i" (MAS_LOAD_SPEC | MAS_BYPASS_L1_CACHE)); \
} while (0)
# define E2K_PREFETCH_L2_OFFSET(addr, offset) \
do { \
int unused; \
asm ("ldb,sm %1, %2, %%empty, mas=%3\n" \
asm ("ldb %1, %2, %%empty, mas=%3\n" \
: "=r" (unused) \
: "r" (addr), \
"i" (offset), \
"i" (MAS_BYPASS_L1_CACHE)); \
} while (0)
# define E2K_PREFETCH_L2_256(addr) \
# define E2K_PREFETCH_L2_NOSPEC_256(addr) \
do { \
int unused; \
asm ( "ldb,0,sm %1, 0, %%empty, mas=%2\n" \
"ldb,2,sm %1, 64, %%empty, mas=%2\n" \
"ldb,3,sm %1, 128, %%empty, mas=%2\n" \
"ldb,5,sm %1, 192, %%empty, mas=%2" \
: "=r" (unused) \
: "r" (addr), \
"i" (MAS_BYPASS_L1_CACHE)); \
} while (0)
# define E2K_PREFETCH_L2(addr) \
do { \
int unused; \
asm ("ldb,sm %1, 0, %%empty, mas=%2" \
asm ( "ldb,0 %1, 0, %%empty, mas=%2\n" \
"ldb,2 %1, 64, %%empty, mas=%2\n" \
"ldb,3 %1, 128, %%empty, mas=%2\n" \
"ldb,5 %1, 192, %%empty, mas=%2" \
: "=r" (unused) \
: "r" (addr), \
"i" (MAS_BYPASS_L1_CACHE)); \
@ -1583,6 +1579,14 @@ do { \
"i" (MAS_LOAD_SPEC)); \
} while (0)
# define E2K_PREFETCH_L1_NOSPEC(addr) \
do { \
int unused; \
asm ("ldb %1, 0, %%empty" \
: "=r" (unused) \
: "r" (addr)); \
} while (0)
# define E2K_PREFETCH_L1_SPEC_OFFSET(addr, offset) \
do { \
int unused; \
@ -1592,49 +1596,15 @@ do { \
"i" (offset), \
"i" (MAS_LOAD_SPEC)); \
} while (0)
# define E2K_PREFETCH_L1_OFFSET(addr, offset) \
do { \
int unused; \
asm ("ldb,sm %1, %2, %%empty\n" \
: "=r" (unused) \
: "r" (addr), \
"i" (offset)); \
} while (0)
# define E2K_PREFETCH_L1_256(addr) \
do { \
int unused; \
asm ( "ldb,0,sm %1, 0, %%empty\n" \
"ldb,2,sm %1, 64, %%empty\n" \
"ldb,3,sm %1, 128, %%empty\n" \
"ldb,5,sm %1, 192, %%empty" \
: "=r" (unused) \
: "r" (addr)); \
} while (0)
# define E2K_PREFETCH_L1(addr) \
do { \
int unused; \
asm ("ldb,3 %1, 0, %%empty" \
: "=r" (unused) \
: "r" (addr)); \
} while (0)
#else
# define E2K_PREFETCH_L2_SPEC_OFFSET(addr, offset) \
do { (void) (addr); (void) (offset); } while (0)
# define E2K_PREFETCH_L2_OFFSET(addr, offset) \
# define E2K_PREFETCH_L2_SPEC(addr) do { (void) (addr); } while (0)
# define E2K_PREFETCH_L2_NOSPEC_OFFSET(addr, offset) \
do { (void) (addr); (void) (offset); } while (0)
# define E2K_PREFETCH_L2_NOSPEC_256(addr) do { (void) (addr); } while (0)
# define E2K_PREFETCH_L1_SPEC(addr) do { (void) (addr); } while (0)
# define E2K_PREFETCH_L1_NOSPEC(addr) do { (void) (addr); } while (0)
# define E2K_PREFETCH_L1_SPEC_OFFSET(addr, offset) \
do { (void) (addr); (void) (offset); } while (0)
# define E2K_PREFETCH_L1_OFFSET(addr, offset) \
do { (void) (addr); (void) (offset); } while (0)
# define E2K_PREFETCH_L2_SPEC(addr) do { (void) (addr); } while (0)
# define E2K_PREFETCH_L2_256(addr) do { (void) (addr); } while (0)
# define E2K_PREFETCH_L2(addr) do { (void) (addr); } while (0)
# define E2K_PREFETCH_L1_SPEC(addr) do { (void) (addr); } while (0)
# define E2K_PREFETCH_L1_256(addr) do { (void) (addr); } while (0)
# define E2K_PREFETCH_L1(addr) do { (void) (addr); } while (0)
#endif
/*
@ -1743,20 +1713,22 @@ do { \
#define NATIVE_RECOVERY_LOAD_TO_THE_GREG_VR_ATOMIC_QP(_addr, _opc, \
greg_no, _vr) \
do { \
u64 val; \
u64 __opc = (_opc); \
u64 tmp, __opc = (_opc); \
/* #133760 Use a real quadro register when repeating atomic load */ \
asm ( "{disp %%ctpr1, qpswitchd_sm\n" \
" nop 4\n" \
" ldrd,0 [ %[addr] + %[opc] ], %[val]\n" \
" ldrd,2 [ %[addr] + %[opc_8] ], %%g" #greg_no "\n" \
" ldrd,0 [ %[addr] + %[opc] ], %%db[0]\n" \
" ldrd,2 [ %[addr] + %[opc_8] ], %%db[1]\n" \
" cmpesb,1 %[vr], 0, %%pred19}\n" \
"{movts,0 %%g" #greg_no ", %[val] ? %%pred19\n" \
"{movts,0 %%g" #greg_no ", %%b[0] ? %%pred19\n" \
" movtd,1 %%db[1], %%dg" #greg_no "}\n" \
"{movtd,0 %%db[0], %[tmp]\n" \
" addd,2 %[greg], 0, %%db[0]\n" \
" call %%ctpr1, wbs=%#}\n" \
"{movtd %[val], %%dg" #greg_no "}\n" \
: [val] "=&r" (val) \
: [addr] "r" (_addr), [vr] "ir" ((u32) (_vr)), \
[opc] "r" (__opc), [opc_8] "r" (__opc | 8ull), \
"{movtd,0 %[tmp], %%dg" #greg_no "}\n" \
: [tmp] "=&r" (tmp) \
: [opc] "r" (__opc), [opc_8] "r" (__opc | 8ull), \
[addr] "r" (_addr), [vr] "ir" ((u32) (_vr)), \
[greg] "i" ((u64) (greg_no)) \
: "call", "memory", "pred19", "g" #greg_no); \
} while (false)
@ -1764,36 +1736,37 @@ do { \
#define NATIVE_RECOVERY_LOAD_TO_THE_GREG_VR_ATOMIC_QP_OR_Q(_addr, _opc, \
greg_no_lo, greg_no_hi, _vr, _qp_load) \
do { \
u64 val; \
u64 __opc = (_opc); \
u64 tmp, __opc = (_opc); \
/* #133760 Use a real quadro register when repeating atomic load */ \
if (_qp_load) { \
asm ( "{disp %%ctpr1, qpswitchd_sm\n" \
" nop 4\n" \
" ldrd,0 [ %[addr] + %[opc] ], %[val]\n" \
" ldrd,2 [ %[addr] + %[opc_8] ], %%g" #greg_no_lo "\n" \
" ldrd,0 [ %[addr] + %[opc] ], %%db[0]\n" \
" ldrd,2 [ %[addr] + %[opc_8] ], %%db[1]\n" \
" cmpesb,1 %[vr], 0, %%pred19}\n" \
"{movts,0 %%g" #greg_no_lo ", %[val] ? %%pred19\n" \
"{movts,0 %%g" #greg_no_lo ", %%b[0] ? %%pred19\n" \
" movtd,1 %%db[1], %%dg" #greg_no_lo "}\n" \
"{movtd,0 %%db[0], %[tmp]\n" \
" addd,2 %[greg], 0, %%db[0]\n" \
" call %%ctpr1, wbs=%#}\n" \
"{movtd %[val], %%dg" #greg_no_lo "}\n" \
: [val] "=&r" (val) \
"{movtd %[tmp], %%dg" #greg_no_lo "}\n" \
: [tmp] "=&r" (tmp) \
: [addr] "r" (_addr), [vr] "ir" ((u32) (_vr)), \
[opc] "r" (__opc), [opc_8] "r" (__opc | 8ull), \
[greg] "i" ((u64) (greg_no_lo)) \
: "call", "memory", "pred19", "g" #greg_no_lo); \
} else { \
asm ( "{nop 4\n" \
" ldrd,0 [ %[addr] + %[opc] ], %[val]\n" \
" ldrd,0 [ %[addr] + %[opc] ], %%g" #greg_no_lo "\n" \
" ldrd,2 [ %[addr] + %[opc_8] ], %%g" #greg_no_hi "\n" \
" cmpesb,1 %[vr], 0, %%pred19}\n" \
"{nop 1\n" \
" movts,0 %%g" #greg_no_lo ", %[val] ? %%pred19}\n" \
"{movtd,0 %[val], %%dg" #greg_no_lo "}\n" \
: [val] "=&r" (val) \
" movts,1 %%g" #greg_no_lo ", %[tmp]\n" \
" cmpesb,4 %[vr], 0, %%pred19}\n" \
"{movts,0 %[tmp], %%g" #greg_no_lo " ? %%pred19}\n" \
: [tmp] "=&r" (tmp) \
: [addr] "r" (_addr), [vr] "ir" ((u32) (_vr)), \
[opc] "r" (__opc), [opc_8] "r" (__opc | 8ull), \
[greg] "i" ((u64) (greg_no_lo)) \
: "call", "memory", "pred19", "g" #greg_no_lo); \
: "memory", "pred19", "g" #greg_no_lo, "g" #greg_no_hi); \
} \
} while (false)
@ -2290,7 +2263,10 @@ do { \
#define NATIVE_MOVE_TAGGED_DWORD_WITH_OPC_VR_ATOMIC(_from, _to, _to_hi, \
_vr, _opc) \
do { \
u64 prev, val, val_8; \
u64 prev; \
/* #133760 Use a real quadro register when repeating atomic load */ \
register u64 val asm("%b[0]"); \
register u64 val_8 asm("%b[1]"); \
u64 __opc = (_opc); \
asm ( "{cmpesb %[vr], 0, %%pred19}\n" \
"{ldrd,0 [ %[from] + %[opc] ], %[val]\n" \
@ -4629,158 +4605,104 @@ do { \
#if !defined CONFIG_E2K_MACHINE || \
defined CONFIG_E2K_ES2_DSP || defined CONFIG_E2K_ES2_RU || \
(defined CONFIG_E2K_E2S && defined CONFIG_NUMA)
# define WORKAROUND_WAIT_HWBUG(num) (((num) & (_st_c | _all_c | _sas)) ? \
((num) | _ma_c) : (num))
# define E2K_WAIT_ST_C_SAS() E2K_WAIT(_st_c)
# define E2K_WAIT_ST_C_SAS_MT() E2K_WAIT(_st_c)
# define E2K_WAIT_LD_C_LAL() E2K_WAIT(_ld_c)
# define E2K_WAIT_LD_C_LAL_MT() E2K_WAIT(_ld_c)
# define E2K_WAIT_LD_C_LAL_SAL() E2K_WAIT(_ld_c)
# define E2K_WAIT_ST_C_SAS_LD_C_SAL() E2K_WAIT(_st_c | _ld_c)
# define E2K_WAIT_ST_C_SAS_LD_C_SAL_MT() E2K_WAIT(_st_c | _ld_c)
#else
# define WORKAROUND_WAIT_HWBUG(num) num
/* BUG 79245 - use .word to encode relaxed barriers */
# define E2K_WAIT_ST_C_SAS() \
({ \
int unused; \
_Pragma("no_asm_inline") \
asm NOT_VOLATILE (".word 0x00008001\n" \
".word 0x30000084\n" \
: "=r" (unused) :: "memory"); \
})
# define E2K_WAIT_LD_C_LAL() \
({ \
int unused; \
_Pragma("no_asm_inline") \
asm NOT_VOLATILE (".word 0x00008001\n" \
".word 0x30000408\n" \
: "=r" (unused) :: "memory"); \
})
# define E2K_WAIT_ST_C_SAS_MT() \
({ \
int unused; \
_Pragma("no_asm_inline") \
asm NOT_VOLATILE (".word 0x00008001\n" \
".word 0x30000884\n" \
: "=r" (unused) :: "memory"); \
})
# define E2K_WAIT_LD_C_LAL_SAL() \
({ \
int unused; \
_Pragma("no_asm_inline") \
asm NOT_VOLATILE (".word 0x00008001\n" \
".word 0x30000508\n" \
: "=r" (unused) :: "memory"); \
})
# define E2K_WAIT_LD_C_LAL_MT() \
({ \
int unused; \
_Pragma("no_asm_inline") \
asm NOT_VOLATILE (".word 0x00008001\n" \
".word 0x30000c08\n" \
: "=r" (unused) :: "memory"); \
})
# define E2K_WAIT_ST_C_SAS_LD_C_SAL() \
({ \
int unused; \
_Pragma("no_asm_inline") \
asm NOT_VOLATILE (".word 0x00008001\n" \
".word 0x3000018c\n" \
: "=r" (unused) :: "memory"); \
})
# define E2K_WAIT_ST_C_SAS_LD_C_SAL_MT() \
({ \
int unused; \
_Pragma("no_asm_inline") \
asm NOT_VOLATILE (".word 0x00008001\n" \
".word 0x3000098c\n" \
: "=r" (unused) :: "memory"); \
})
#endif
#define E2K_WAIT_V6(_num) \
({ \
int unused, num = WORKAROUND_WAIT_HWBUG(_num); \
/* "trap=1" requires special handling, see C1_wait_trap() */ \
asm NOT_VOLATILE("{wait mem_mod=%[mem_mod], int=%[intr], mt=%[mt], " \
" lal=%[lal], las=%[las], sal=%[sal], sas=%[sas], " \
" ma_c=%[ma_c], fl_c=%[fl_c], ld_c = %[ld_c], " \
" st_c=%[st_c], all_e=%[all_e], all_c=%[all_c]}"\
: "=r" (unused) \
: [all_c] "i" (((num) & 0x1)), \
[all_e] "i" (((num) & 0x2) >> 1), \
[st_c] "i" (((num) & 0x4) >> 2), \
[ld_c] "i" (((num) & 0x8) >> 3), \
[fl_c] "i" (((num) & 0x10) >> 4), \
[ma_c] "i" (((num) & 0x20) >> 5), \
[sas] "i" (((num) & 0x80) >> 7), \
[sal] "i" (((num) & 0x100) >> 8), \
[las] "i" (((num) & 0x200) >> 9), \
[lal] "i" (((num) & 0x400) >> 10), \
[mt] "i" (((num) & 0x800) >> 11), \
[intr] "i" (((num) & 0x1000) >> 12), \
[mem_mod] "i" (((num) & 0x2000) >> 13) \
: "memory" ); \
if ((num & (_all_c | _ma_c | _lal | _las)) || \
(num & _ld_c) && !(num & _sal) || \
(num & _st_c) && !(num & _sas)) \
NATIVE_HWBUG_AFTER_LD_ACQ(); \
})
#define E2K_WAIT_V5(_num) \
({ \
int unused, num = WORKAROUND_WAIT_HWBUG(_num); \
/* "trap=1" requires special handling, see C1_wait_trap() */ \
asm NOT_VOLATILE ("{wait sal=%[sal], sas=%[sas], ma_c=%[ma_c], " \
" fl_c=%[fl_c], ld_c=%[ld_c], st_c=%[st_c], " \
" all_e=%[all_e], all_c=%[all_c]}" \