277 lines
5.9 KiB
C
277 lines
5.9 KiB
C
#ifndef __ASM_APIC_REGS_H
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#define __ASM_APIC_REGS_H
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#ifndef __ASSEMBLY__
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/*
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* the local APIC register structure, memory mapped. Not terribly well
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* tested, but we might eventually use this one in the future - the
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* problem why we cannot use it right now is the P5 APIC, it has an
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* errata which cannot take 8-bit reads and writes, only 32-bit ones ...
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*/
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#define u32 unsigned int
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struct local_apic {
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/*000*/ struct { u32 __reserved[4]; } __reserved_01;
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/*010*/ struct { u32 __reserved_1 : 8,
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boot_strap : 1,
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__reserved_2 : 2,
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apic_enable : 1,
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__reserved_3 : 20;
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u32 __reserved[3];
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} bsp;
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/*020*/ struct { /* APIC ID Register */
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u32 __reserved_1 : 24,
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phys_apic_id : 4,
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__reserved_2 : 4;
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u32 __reserved[3];
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} id;
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/*030*/ const
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struct { /* APIC Version Register */
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u32 version : 8,
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__reserved_1 : 8,
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max_lvt : 8,
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__reserved_2 : 8;
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u32 __reserved[3];
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} version;
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/*040*/ struct { u32 __reserved[4]; } __reserved_03;
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/*050*/ struct { u32 __reserved[4]; } __reserved_04;
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/*060*/ struct { u32 __reserved[4]; } __reserved_05;
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/*070*/ struct { u32 __reserved[4]; } __reserved_06;
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/*080*/ struct { /* Task Priority Register */
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u32 priority : 8,
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__reserved_1 : 24;
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u32 __reserved_2[3];
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} tpr;
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/*090*/ const
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struct { /* Arbitration Priority Register */
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u32 priority : 8,
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__reserved_1 : 24;
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u32 __reserved_2[3];
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} apr;
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/*0A0*/ const
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struct { /* Processor Priority Register */
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u32 priority : 8,
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__reserved_1 : 24;
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u32 __reserved_2[3];
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} ppr;
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/*0B0*/ struct { /* End Of Interrupt Register */
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u32 eoi;
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u32 __reserved[3];
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} eoi;
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/*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
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/*0D0*/ struct { /* Logical Destination Register */
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u32 __reserved_1 : 24,
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logical_dest : 8;
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u32 __reserved_2[3];
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} ldr;
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/*0E0*/ struct { /* Destination Format Register */
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u32 __reserved_1 : 28,
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model : 4;
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u32 __reserved_2[3];
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} dfr;
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/*0F0*/ struct { /* Spurious Interrupt Vector Register */
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u32 spurious_vector : 8,
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apic_enabled : 1,
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focus_cpu : 1,
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__reserved_2 : 22;
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u32 __reserved_3[3];
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} svr;
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/*100*/ struct { /* In Service Register */
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/*170*/ u32 bitfield;
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u32 __reserved[3];
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} isr [8];
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/*180*/ struct { /* Trigger Mode Register */
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/*1F0*/ u32 bitfield;
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u32 __reserved[3];
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} tmr [8];
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/*200*/ struct { /* Interrupt Request Register */
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/*270*/ u32 bitfield;
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u32 __reserved[3];
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} irr [8];
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/*280*/ union { /* Error Status Register */
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struct {
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u32 send_cs_error : 1,
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receive_cs_error : 1,
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send_accept_error : 1,
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receive_accept_error : 1,
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__reserved_1 : 1,
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send_illegal_vector : 1,
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receive_illegal_vector : 1,
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illegal_register_address : 1,
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__reserved_2 : 24;
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u32 __reserved_3[3];
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} error_bits;
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struct {
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u32 errors;
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u32 __reserved_3[3];
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} all_errors;
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} esr;
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/*290*/ struct { u32 __reserved[4]; } __reserved_08;
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/*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
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/*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
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/*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
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/*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
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/*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
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/*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
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/*300*/ struct { /* Interrupt Command Register 1 */
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u32 vector : 8,
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delivery_mode : 3,
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destination_mode : 1,
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delivery_status : 1,
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__reserved_1 : 1,
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level : 1,
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trigger : 1,
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__reserved_2 : 2,
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shorthand : 2,
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__reserved_3 : 12;
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u32 __reserved_4[3];
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} icr1;
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/*310*/ struct { /* Interrupt Command Register 2 */
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union {
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u32 __reserved_1 : 24,
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phys_dest : 4,
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__reserved_2 : 4;
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u32 __reserved_3 : 24,
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logical_dest : 8;
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} dest;
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u32 __reserved_4[3];
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} icr2;
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/*320*/ struct { /* LVT - Timer */
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u32 vector : 8,
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__reserved_1 : 4,
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delivery_status : 1,
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__reserved_2 : 3,
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mask : 1,
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timer_mode : 1,
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__reserved_3 : 14;
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u32 __reserved_4[3];
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} lvt_timer;
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/*330*/ struct { u32 __reserved[4]; } __reserved_15;
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/*340*/ struct { /* LVT - Performance Counter */
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u32 vector : 8,
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delivery_mode : 3,
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__reserved_1 : 1,
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delivery_status : 1,
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__reserved_2 : 3,
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mask : 1,
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__reserved_3 : 15;
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u32 __reserved_4[3];
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} lvt_pc;
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/*350*/ struct { /* LVT - LINT0 */
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u32 vector : 8,
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delivery_mode : 3,
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__reserved_1 : 1,
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delivery_status : 1,
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polarity : 1,
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remote_irr : 1,
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trigger : 1,
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mask : 1,
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__reserved_2 : 15;
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u32 __reserved_3[3];
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} lvt_lint0;
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/*360*/ struct { /* LVT - LINT1 */
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u32 vector : 8,
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delivery_mode : 3,
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__reserved_1 : 1,
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delivery_status : 1,
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polarity : 1,
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remote_irr : 1,
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trigger : 1,
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mask : 1,
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__reserved_2 : 15;
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u32 __reserved_3[3];
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} lvt_lint1;
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/*370*/ struct { /* LVT - Error */
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u32 vector : 8,
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__reserved_1 : 4,
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delivery_status : 1,
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__reserved_2 : 3,
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mask : 1,
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__reserved_3 : 15;
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u32 __reserved_4[3];
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} lvt_error;
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/*380*/ struct { /* Timer Initial Count Register */
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u32 initial_count;
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u32 __reserved_2[3];
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} timer_icr;
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/*390*/ const
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struct { /* Timer Current Count Register */
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u32 curr_count;
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u32 __reserved_2[3];
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} timer_ccr;
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/*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
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/*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
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/*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
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/*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
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/*3E0*/ struct { /* Timer Divide Configuration Register */
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u32 divisor : 4,
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__reserved_1 : 28;
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u32 __reserved_2[3];
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} timer_dcr;
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/*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
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#if 0
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/*3F0*/ struct { u32 __reserved[764]; } __reserved_20;
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/*FE0*/ struct { /* Vector from PIC or APIC in nmi */
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u32 nm_vector : 8,
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__reserved : 24;
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u32 __reserved[3];
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} nm_vect;
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/*FF0*/ struct { /* Vector */
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u32 vector : 8,
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__reserved_1 : 24;
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u32 __reserved[3];
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} vect;
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#endif
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} __attribute__ ((packed));
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#undef u32
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#endif /* !(__ASSEMBLY__) */
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#endif /* __ASM_APIC_REGS_H */
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