60 lines
1.9 KiB
C
60 lines
1.9 KiB
C
#ifndef _ASM_E12C_H_
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#define _ASM_E12C_H_
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/*
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* Machine (based on E12C processor) topology:
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* E12C is NUMA system on distributed memory and can have several nodes.
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* Each node can have some memory (faster to access) and max 12 CPUs (cores)
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* Node number is the same as chip-processor number
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* Some nodes (CPUs) can be without memory
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* LAPIC cluster number is the same as node number
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*/
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#ifndef __ASSEMBLY__
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struct pt_regs;
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extern void boot_e12c_setup_arch(void);
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extern void e12c_setup_machine(void);
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extern void setup_APIC_vector_handler(int vector,
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void (*handler)(struct pt_regs *), bool system, char *name);
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#endif
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#define E12C_NR_NODE_CPUS 12
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#define E12C_MAX_NR_NODE_CPUS 16
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#define E12C_NODE_IOLINKS 1
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#define E12C_PCICFG_AREA_PHYS_BASE ES2_PCICFG_AREA_PHYS_BASE
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#define E12C_PCICFG_AREA_SIZE ES2_PCICFG_AREA_SIZE
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#define E12C_NSR_AREA_PHYS_BASE ES2_NSR_AREA_PHYS_BASE
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#define E12C_NBSR_AREA_OFFSET ES2_NBSR_AREA_OFFSET
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#define E12C_NBSR_AREA_SIZE ES2_NBSR_AREA_SIZE
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#define E12C_COPSR_AREA_PHYS_BASE ES2_COPSR_AREA_PHYS_BASE
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#define E12C_COPSR_AREA_SIZE ES2_COPSR_AREA_SIZE
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#define E12C_MLT_SIZE ES2_MLT_SIZE
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#define E12C_TLB_LINES_BITS_NUM ES2_TLB_LINES_BITS_NUM
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#define E12C_TLB_ADDR_LINE_NUM E2S_TLB_ADDR_LINE_NUM
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#define E12C_TLB_ADDR_LINE_NUM2 E2S_TLB_ADDR_LINE_NUM2
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#define E12C_TLB_ADDR_LINE_NUM_SHIFT2 E2S_TLB_ADDR_LINE_NUM_SHIFT2
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#define E12C_TLB_ADDR_SET_NUM E2S_TLB_ADDR_SET_NUM
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#define E12C_TLB_ADDR_SET_NUM_SHIFT E2S_TLB_ADDR_SET_NUM_SHIFT
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#define E12C_SIC_MC_SIZE E16C_SIC_MC_SIZE
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#define E12C_SIC_MC_COUNT 2
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#define E12C_CLOCK_TICK_RATE ES2_CLOCK_TICK_RATE
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#define E12C_L1_CACHE_SHIFT ES2_L1_CACHE_SHIFT
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#define E12C_L1_CACHE_BYTES ES2_L1_CACHE_BYTES
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#define E12C_L2_CACHE_SHIFT ES2_L2_CACHE_SHIFT
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#define E12C_L2_CACHE_BYTES ES2_L2_CACHE_BYTES
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#define E12C_L3_CACHE_SHIFT E8C_L3_CACHE_SHIFT
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#define E12C_L3_CACHE_BYTES E8C_L3_CACHE_BYTES
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#endif /* _ASM_E12C_H_ */
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