60 lines
1.8 KiB
C
60 lines
1.8 KiB
C
#ifndef _ASM_E2S_H_
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#define _ASM_E2S_H_
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/*
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* Machine (based on E4C processor) topology:
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* E4C is NUMA system on distributed memory and can have several nodes.
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* Each node can have some memory (faster to access) and max 4 CPUs (cores)
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* Node number is the same as chip-processor number
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* Some nodes (CPUs) can be without memory
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* LAPIC cluster number is the same as node number
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*/
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#ifndef __ASSEMBLY__
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struct pt_regs;
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extern void boot_e2s_setup_arch(void);
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extern void e2s_setup_machine(void);
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extern void setup_APIC_vector_handler(int vector,
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void (*handler)(struct pt_regs *), bool system, char *name);
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extern void sic_error_interrupt(struct pt_regs *regs);
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#endif
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#define E2S_NR_NODE_CPUS 4
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#define E2S_MAX_NR_NODE_CPUS E2S_NR_NODE_CPUS
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#define E2S_NODE_IOLINKS 1
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#define E2S_PCICFG_AREA_PHYS_BASE ES2_PCICFG_AREA_PHYS_BASE
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#define E2S_PCICFG_AREA_SIZE ES2_PCICFG_AREA_SIZE
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#define E2S_NSR_AREA_PHYS_BASE ES2_NSR_AREA_PHYS_BASE
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#define E2S_NBSR_AREA_OFFSET ES2_NBSR_AREA_OFFSET
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#define E2S_NBSR_AREA_SIZE ES2_NBSR_AREA_SIZE
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#define E2S_COPSR_AREA_PHYS_BASE ES2_COPSR_AREA_PHYS_BASE
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#define E2S_COPSR_AREA_SIZE ES2_COPSR_AREA_SIZE
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#define E2S_MLT_SIZE ES2_MLT_SIZE
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#define E2S_TLB_LINES_BITS_NUM ES2_TLB_LINES_BITS_NUM
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#define E2S_TLB_ADDR_LINE_NUM ES2_TLB_ADDR_LINE_NUM
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#define E2S_TLB_ADDR_LINE_NUM2 0x000000001fe00000
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#define E2S_TLB_ADDR_LINE_NUM_SHIFT2 21
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#define E2S_TLB_ADDR_SET_NUM ES2_TLB_ADDR_SET_NUM
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#define E2S_TLB_ADDR_SET_NUM_SHIFT ES2_TLB_ADDR_SET_NUM_SHIFT
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#define E2S_SIC_MC_SIZE 0xa4
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#define E2S_SIC_MC_COUNT 3
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#define E2S_SIC_MC1_ECC 0x440
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#define E2S_CLOCK_TICK_RATE ES2_CLOCK_TICK_RATE
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#define E2S_L1_CACHE_SHIFT ES2_L1_CACHE_SHIFT
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#define E2S_L1_CACHE_BYTES ES2_L1_CACHE_BYTES
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#define E2S_L2_CACHE_SHIFT ES2_L2_CACHE_SHIFT
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#define E2S_L2_CACHE_BYTES ES2_L2_CACHE_BYTES
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#endif /* _ASM_E2S_H_ */
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