438 lines
14 KiB
C
438 lines
14 KiB
C
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#ifndef _E2K_HB_REGS_H_
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#define _E2K_HB_REGS_H_
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#ifdef __KERNEL__
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#include <linux/types.h>
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#ifndef __ASSEMBLY__
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#include <linux/pci.h>
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#include <asm/e2k.h>
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#include <asm/e2k_sic.h>
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#endif /* __ASSEMBLY__ */
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#undef DEBUG_ERALY_HB_MODE
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#undef DebugEHB
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#define DEBUG_ERALY_HB_MODE 0 /* early Host Bridge access */
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#undef DEBUG_BOOT_HB_MODE
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#undef DebugBEHB
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#define DEBUG_BOOT_HB_MODE 0 /* boot Host Bridge access */
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#ifndef CONFIG_BOOT_E2K
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#define DebugEHB(fmt, args...) \
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({ if (DEBUG_ERALY_HB_MODE) \
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printk(fmt, ##args); })
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#define DebugBEHB(fmt, args...) \
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({ if (DEBUG_BOOT_HB_MODE) \
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do_boot_printk(fmt, ##args); })
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#else /* CONFIG_BOOT_E2K */
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#define DebugEHB(fmt, args...) \
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({ if (DEBUG_ERALY_HB_MODE) \
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rom_printk(fmt, ##args); })
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#define DebugBEHB(fmt, args...) \
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({ if (DEBUG_BOOT_HB_MODE) \
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rom_printk(fmt, ##args); })
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#endif /* ! CONFIG_BOOT_E2K */
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#undef DEBUG_HB_MODE
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#undef DebugHB
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#define DEBUG_HB_MODE 0 /* Host Bridge access */
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#define DebugHB(fmt, args...) \
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({ if (DEBUG_HB_MODE) \
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printk(fmt, ##args); })
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/*
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* Host Bridge is PCI device on root bus #0 and has common PCI configure
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* registers and some additional special registers
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*/
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/* Host bridge is device 0x1f on root bus #0 */
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#define HB_PCI_BUS_NUM 0x00
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#define HB_PCI_SLOT 0x1f
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#define HB_PCI_FUNC 0x00
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/* Embeded Graphic is device 0x1e on root bus #0 */
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#define EG_PCI_BUS_NUM 0x00
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#define EG_PCI_SLOT 0x1e
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#define EG_PCI_FUNC 0x00
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/* Base address of legacy NBSR registers */
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#define HB_PCI_LEGACY_BAR PCI_BASE_ADDRESS_0 /* 0x10 64 bits */
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#define HB_PCI_LEGACY_MEMORY_BAR 0x000000fffff00000 /* [39:20] */
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#define HB_PCI_LEGACY_ADDR_MASK 0x00000000000ffff0 /* [19: 4] 1M */
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/* Base address of Power Management Controller registers */
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#define HB_PCI_PMC_BAR PCI_BASE_ADDRESS_2 /* 0x18 64 bits */
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#define HB_PCI_PMC_MEMORY_BAR 0x000000ffffff0000 /* [39:16] */
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#define HB_PCI_PMC_ADDR_MASK 0x000000000000fff0 /* [15: 4] */
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/* 64K */
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/* Additional special registers */
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/* Host Bridge configuration register */
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#define HB_PCI_CFG 0x40 /* 32 bits */
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#define HB_CFG_MaskIntSic 0x00000080 /* SIC interrupts */
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/* to embedeed IOAPIC */
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#define HB_CFG_MaskIntWlcc 0x00000040 /* WLCC interrupts */
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/* to embedeed IOAPIC */
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#define HB_CFG_MaskIntIommu 0x00000020 /* IOMMU interrupts */
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/* to embedeed IOAPIC */
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#define HB_CFG_ShareHostInterrupts 0x00000010 /* HB interrupts */
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/* are shared as IRQ2 */
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/* else IRQ2 & IRQ3 */
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#define HB_CFG_ShareGraphicsInterrupts 0x00000008 /* EG interrupts */
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/* are shared as IRQ0 */
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/* else IRQ0 & IRQ1 */
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#define HB_CFG_InternalIoApicEnable 0x00000004 /* embeded interrupts */
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/* to embedeed IOAPIC */
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/* else to LAPIC LVT */
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#define HB_CFG_IntegratedVgaEnable 0x00000002 /* Legacy VGA access */
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/* to EG */
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/* else to IOHUB */
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#define HB_CFG_IntegratedGraphicsEnable 0x00000001 /* EG is on */
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/* Top Of low Memory register */
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#define HB_PCI_TOM 0x44 /* 32 bits */
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#define HB_PCI_TOM_LOW_MASK 0x00000000fff00000 /* [31:20] */
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/* Top Of high Memory register */
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#define HB_PCI_TOM2 0x48 /* 64 bits */
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#define HB_PCI_TOM2_HI_MASK 0x000000fffff00000 /* [39:20] */
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#define HB_PCI_HI_ADDR_BASE 0x0000000100000000 /* 4Gb */
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/* Base Address of high memory from which remapped low memore */
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#define HB_PCI_REMAPBASE 0x50 /* 64 bits */
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#define HB_PCI_REMAPBASE_MASK 0x000000fffff00000 /* [39:20] */
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/* Base Address of embeded IO APIC */
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#define HB_PCI_IOAPICBASE 0x58 /* 64 bits */
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#define HB_PCI_IOAPICBASE_MASK 0x000000ffffffff00 /* [39: 8] */
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/* PMC MSI configuration register */
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#define HB_PCI_PMC_MSGCTL 0x62 /* 16 bits */
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/* PMC MSI address register */
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#define HB_PCI_PMC_MSGADDR 0x64 /* 32 bits */
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#define HB_PCI_MESSADGEADDRESS 0xfffffffc /* [31: 2] */
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/*
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* Embeded Graphic controller registers
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*/
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/* Base address of Video RAM */
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#define EG_PCI_VRAM_BAR PCI_BASE_ADDRESS_0 /* 0x10 64 bits */
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#define EG_PCI_VRAM_MEMORY_BAR 0x000000fff8000000 /* [39:30] */
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#define EG_PCI_VRAM_ADDRMASK1024 0x0000000020000000 /* [29] */
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#define EG_PCI_VRAM_ADDRMASK512 0x0000000010000000 /* [28] */
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#define EG_PCI_VRAM_ADDRMASK256 0x0000000008000000 /* [27] */
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#define EG_PCI_VRAM_ADDR_MASK 0x0000000007fffff0 /* [26: 4] 128M */
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/* Base address of MGA-2 registers */
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#define EG_PCI_MGA2_BAR PCI_BASE_ADDRESS_2 /* 0x18 32 bits */
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#define EG_PCI_MGA2_MEMORY_BAR 0xfffc0000 /* [31:18] */
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#define EG_PCI_MGA2_ADDR_MASK 0x0003ffff /* [17: 4] 256K */
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/* Base address of GC2500 registers */
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#define EG_PCI_GC2500_BAR PCI_BASE_ADDRESS_3 /* 0x1c 32 bits */
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#define EG_PCI_GC2500_MEMORY_BAR 0xfffc0000 /* [31:18] */
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#define EG_PCI_GC2500_ADDR_MASK 0x0003ffff /* [17: 4] 256K */
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/* Embeded Graphic controller CFG register */
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#define EG_PCI_CFG 0x40 /* 32 bits */
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#define EG_CFG_VRAM_SIZE_MASK 0x00000003 /* [ 1: 0] */
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#define EG_CFG_VRAM_SIZE_128 0x0 /* 128 Mb */
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#define EG_CFG_VRAM_SIZE_256 0x1 /* 256 Mb */
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#define EG_CFG_VRAM_SIZE_512 0x2 /* 512 Mb */
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#define EG_CFG_VRAM_SIZE_1024 0x3 /* 1 Gb */
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/* Embeded Graphic MSI configuration register */
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#define EG_PCI_MSGCTL 0x46 /* 16 bits */
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/* Embeded Graphic MSI address register */
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#define EG_PCI_MSGADDR 0x48 /* 32 bits */
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#define EG_PCI_MESSADGEADDRESS 0xfffffffc /* [31: 2] */
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#ifndef __ASSEMBLY__
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/*
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* Host bridge & embeded graphic see as PCI devices on bus #0
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*/
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#define hb_eg_early_readb(addr) \
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boot_readb((void *)(addr))
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#define hb_eg_early_readw(addr) \
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boot_readw((void *)(addr))
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#define hb_eg_early_readl(addr) \
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boot_readl((void *)(addr))
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#define hb_eg_early_writeb(value, addr) \
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boot_writeb((value), (void *)(addr))
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#define hb_eg_early_writew(value, addr) \
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boot_writew((value), (void *)(addr))
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#define hb_eg_early_writel(value, addr) \
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boot_writel((value), (void *)(addr))
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#define hb_eg_early_pci_conf_base() sic_domain_pci_conf_base(0)
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#define boot_hb_eg_readl(addr) boot_readl((void *)(addr))
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#define boot_hb_eg_pci_conf_base() boot_sic_domain_pci_conf_base(0)
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static inline unsigned char
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early_readb_hb_eg_reg(unsigned int bus, unsigned int slot, unsigned int func,
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unsigned int reg_offset)
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{
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unsigned long reg_addr = hb_eg_early_pci_conf_base();
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unsigned char reg_value;
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reg_addr += CONFIG_CMD(bus, PCI_DEVFN(slot, func), reg_offset);
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reg_value = hb_eg_early_readb(reg_addr);
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DebugEHB("early_readb_hb_eg_reg() reg 0x%x read 0x%02hhx from 0x%lx\n",
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reg_offset, reg_value, reg_addr);
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return reg_value;
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}
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static inline unsigned short
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early_readw_hb_eg_reg(unsigned int bus, unsigned int slot, unsigned int func,
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unsigned int reg_offset)
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{
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unsigned long reg_addr = hb_eg_early_pci_conf_base();
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unsigned short reg_value;
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reg_addr += CONFIG_CMD(bus, PCI_DEVFN(slot, func), reg_offset);
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reg_value = hb_eg_early_readw(reg_addr);
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DebugEHB("early_readw_hb_eg_reg() reg 0x%x read 0x%04hx from 0x%lx\n",
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reg_offset, reg_value, reg_addr);
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return reg_value;
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}
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static inline unsigned int
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early_readl_hb_eg_reg(unsigned int bus, unsigned int slot, unsigned int func,
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unsigned int reg_offset)
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{
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unsigned long reg_addr = hb_eg_early_pci_conf_base();
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unsigned int reg_value;
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reg_addr += CONFIG_CMD(bus, PCI_DEVFN(slot, func), reg_offset);
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reg_value = hb_eg_early_readl(reg_addr);
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DebugEHB("early_readl_hb_eg_reg() reg 0x%x read 0x%08x from 0x%lx\n",
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reg_offset, reg_value, reg_addr);
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return reg_value;
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}
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static inline unsigned long
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early_readll_hb_eg_reg(unsigned int bus, unsigned int slot, unsigned int func,
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unsigned int reg_offset)
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{
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unsigned long reg_addr = hb_eg_early_pci_conf_base();
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unsigned long reg_value_lo;
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unsigned long reg_value_hi;
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unsigned long reg_value;
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reg_addr += CONFIG_CMD(bus, PCI_DEVFN(slot, func), reg_offset);
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reg_value_lo = hb_eg_early_readl(reg_addr);
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reg_value_hi = hb_eg_early_readl(reg_addr + sizeof(unsigned int));
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reg_value = reg_value_lo | (reg_value_hi << sizeof(unsigned int) * 8);
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DebugEHB("early_readw_hb_eg_reg() reg 0x%x read 0x%016lx from 0x%lx\n",
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reg_offset, reg_value, reg_addr);
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return reg_value;
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}
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static inline unsigned long
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boot_readll_hb_eg_reg(unsigned int bus, unsigned int slot, unsigned int func,
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unsigned int reg_offset)
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{
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unsigned long reg_addr = boot_hb_eg_pci_conf_base();
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unsigned long reg_value_lo;
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unsigned long reg_value_hi;
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unsigned long reg_value;
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reg_addr += CONFIG_CMD(bus, PCI_DEVFN(slot, func), reg_offset);
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reg_value_lo = boot_hb_eg_readl(reg_addr);
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reg_value_hi = boot_hb_eg_readl(reg_addr + sizeof(unsigned int));
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reg_value = reg_value_lo | (reg_value_hi << sizeof(unsigned int) * 8);
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DebugBEHB("boot_readw_hb_eg_reg() reg 0x%x read 0x%016lx from 0x%lx\n",
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reg_offset, reg_value, reg_addr);
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return reg_value;
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}
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static inline void
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early_writeb_hb_eg_reg(unsigned int bus, unsigned int slot, unsigned int func,
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unsigned char reg_value, unsigned int reg_offset)
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{
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unsigned long reg_addr = hb_eg_early_pci_conf_base();
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reg_addr += CONFIG_CMD(bus, PCI_DEVFN(slot, func), reg_offset);
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hb_eg_early_writeb(reg_value, reg_addr);
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DebugEHB("early_writeb_hb_eg_reg() reg 0x%x write 0x%02hhx to 0x%lx\n",
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reg_offset, reg_value, reg_addr);
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}
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static inline void
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early_writew_hb_eg_reg(unsigned int bus, unsigned int slot, unsigned int func,
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unsigned short reg_value, unsigned int reg_offset)
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{
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unsigned long reg_addr = hb_eg_early_pci_conf_base();
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reg_addr += CONFIG_CMD(bus, PCI_DEVFN(slot, func), reg_offset);
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hb_eg_early_writew(reg_value, reg_addr);
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DebugEHB("early_writew_hb_eg_reg() reg 0x%x write 0x%04hx to 0x%lx\n",
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reg_offset, reg_value, reg_addr);
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}
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static inline void
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early_writel_hb_eg_reg(unsigned int bus, unsigned int slot, unsigned int func,
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unsigned int reg_value, unsigned int reg_offset)
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{
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unsigned long reg_addr = hb_eg_early_pci_conf_base();
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reg_addr += CONFIG_CMD(bus, PCI_DEVFN(slot, func), reg_offset);
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hb_eg_early_writel(reg_value, reg_addr);
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DebugEHB("early_writel_hb_eg_reg() reg 0x%x write 0x%08x to 0x%lx\n",
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reg_offset, reg_value, reg_addr);
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}
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static inline void
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early_writell_hb_eg_reg(unsigned int bus, unsigned int slot, unsigned int func,
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unsigned long reg_value, unsigned int reg_offset)
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{
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unsigned long reg_addr = hb_eg_early_pci_conf_base();
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unsigned int reg_value_lo;
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unsigned int reg_value_hi;
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reg_addr += CONFIG_CMD(bus, PCI_DEVFN(slot, func), reg_offset);
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reg_value_lo = reg_value & 0x00000000ffffffff;
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reg_value_hi = reg_value >> (sizeof(unsigned int) * 8);
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hb_eg_early_writel(reg_value_lo, reg_addr);
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hb_eg_early_writel(reg_value_hi, reg_addr + sizeof(unsigned int));
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DebugEHB("early_writell_hb_eg_reg() reg 0x%x write 0x%016lx to 0x%lx\n",
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reg_offset, reg_value, reg_addr);
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}
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static inline unsigned char
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early_readb_hb_reg(unsigned int reg_offset)
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{
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return early_readb_hb_eg_reg(HB_PCI_BUS_NUM, HB_PCI_SLOT, HB_PCI_FUNC,
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reg_offset);
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}
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static inline unsigned short
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early_readw_hb_reg(unsigned int reg_offset)
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{
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return early_readw_hb_eg_reg(HB_PCI_BUS_NUM, HB_PCI_SLOT, HB_PCI_FUNC,
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reg_offset);
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}
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static inline unsigned int
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early_readl_hb_reg(unsigned int reg_offset)
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{
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return early_readl_hb_eg_reg(HB_PCI_BUS_NUM, HB_PCI_SLOT, HB_PCI_FUNC,
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reg_offset);
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}
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static inline unsigned long
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early_readll_hb_reg(unsigned int reg_offset)
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{
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return early_readll_hb_eg_reg(HB_PCI_BUS_NUM, HB_PCI_SLOT, HB_PCI_FUNC,
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reg_offset);
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}
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static inline unsigned long
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boot_readll_hb_reg(unsigned int reg_offset)
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{
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return boot_readll_hb_eg_reg(HB_PCI_BUS_NUM, HB_PCI_SLOT, HB_PCI_FUNC,
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reg_offset);
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}
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static inline void
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early_writeb_hb_reg(unsigned char reg_value, unsigned int reg_offset)
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{
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early_writeb_hb_eg_reg(HB_PCI_BUS_NUM, HB_PCI_SLOT, HB_PCI_FUNC,
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reg_value, reg_offset);
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}
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static inline void
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early_writew_hb_reg(unsigned short reg_value, unsigned int reg_offset)
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{
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early_writew_hb_eg_reg(HB_PCI_BUS_NUM, HB_PCI_SLOT, HB_PCI_FUNC,
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reg_value, reg_offset);
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}
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static inline void
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early_writel_hb_reg(unsigned int reg_value, unsigned int reg_offset)
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{
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early_writel_hb_eg_reg(HB_PCI_BUS_NUM, HB_PCI_SLOT, HB_PCI_FUNC,
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reg_value, reg_offset);
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}
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static inline void
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early_writell_hb_reg(unsigned long reg_value, unsigned int reg_offset)
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{
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early_writell_hb_eg_reg(HB_PCI_BUS_NUM, HB_PCI_SLOT, HB_PCI_FUNC,
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reg_value, reg_offset);
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}
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static inline unsigned char
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early_readb_eg_reg(unsigned int reg_offset)
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{
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return early_readb_hb_eg_reg(EG_PCI_BUS_NUM, EG_PCI_SLOT, EG_PCI_FUNC,
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reg_offset);
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}
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static inline unsigned short
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early_readw_eg_reg(unsigned int reg_offset)
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{
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return early_readw_hb_eg_reg(EG_PCI_BUS_NUM, EG_PCI_SLOT, EG_PCI_FUNC,
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reg_offset);
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}
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static inline unsigned int
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early_readl_eg_reg(unsigned int reg_offset)
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{
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return early_readl_hb_eg_reg(EG_PCI_BUS_NUM, EG_PCI_SLOT, EG_PCI_FUNC,
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reg_offset);
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}
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static inline unsigned long
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early_readll_eg_reg(unsigned int reg_offset)
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{
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return early_readll_hb_eg_reg(EG_PCI_BUS_NUM, EG_PCI_SLOT, EG_PCI_FUNC,
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reg_offset);
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}
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static inline void
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early_writeb_eg_reg(unsigned char reg_value, unsigned int reg_offset)
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{
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early_writeb_hb_eg_reg(EG_PCI_BUS_NUM, EG_PCI_SLOT, EG_PCI_FUNC,
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reg_value, reg_offset);
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}
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static inline void
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early_writew_eg_reg(unsigned short reg_value, unsigned int reg_offset)
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{
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early_writew_hb_eg_reg(EG_PCI_BUS_NUM, EG_PCI_SLOT, EG_PCI_FUNC,
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reg_value, reg_offset);
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}
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static inline void
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early_writel_eg_reg(unsigned int reg_value, unsigned int reg_offset)
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{
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early_writel_hb_eg_reg(EG_PCI_BUS_NUM, EG_PCI_SLOT, EG_PCI_FUNC,
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reg_value, reg_offset);
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}
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static inline void
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early_writell_eg_reg(unsigned long reg_value, unsigned int reg_offset)
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{
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early_writell_hb_eg_reg(EG_PCI_BUS_NUM, EG_PCI_SLOT, EG_PCI_FUNC,
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reg_value, reg_offset);
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}
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static inline unsigned long
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early_get_legacy_nbsr_base(void)
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{
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return early_readll_hb_reg(HB_PCI_LEGACY_BAR) &
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HB_PCI_LEGACY_MEMORY_BAR;
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}
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static inline unsigned long
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boot_get_legacy_nbsr_base(void)
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{
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return boot_readll_hb_reg(HB_PCI_LEGACY_BAR) &
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HB_PCI_LEGACY_MEMORY_BAR;
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}
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#endif /* ! __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _E2K_HB_REGS_H_ */
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