616 lines
15 KiB
C
616 lines
15 KiB
C
#ifndef _E2K_IO_H_
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#define _E2K_IO_H_
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/compiler.h>
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#include <asm/e2k_api.h>
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#include <asm/types.h>
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#include <asm/head.h>
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#include <asm/page.h>
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#include <asm/machdep.h>
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#include <asm/p2v/io.h>
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extern int __init native_arch_pci_init(void);
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#define E2K_X86_IO_AREA_BASE E2K_KERNEL_IO_BIOS_AREAS_BASE
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/* Size of pages for the IO area */
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#define E2K_X86_IO_PAGE_SIZE (cpu_has(CPU_HWBUG_LARGE_PAGES) ? \
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E2K_SMALL_PAGE_SIZE : E2K_LARGE_PAGE_SIZE)
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#define X86_IO_AREA_PHYS_BASE (machine.x86_io_area_base)
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#define X86_IO_AREA_PHYS_SIZE (machine.x86_io_area_size)
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/*
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* We add all the necessary barriers manually
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*/
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#define __io_br()
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#define __io_ar(v) do { (void) (v); } while (0)
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#define __io_bw()
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#define __io_aw()
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/*
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* _relaxed() accessors.
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*/
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static inline u8 native_readb_relaxed(const volatile void __iomem *addr)
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{
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u8 res = *(const volatile u8 __force *) addr;
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if (cpu_has(CPU_HWBUG_PIO_READS))
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__E2K_WAIT(_ld_c);
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return res;
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}
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static inline u16 native_readw_relaxed(const volatile void __iomem *addr)
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{
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u16 res = *(const volatile u16 __force *) addr;
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if (cpu_has(CPU_HWBUG_PIO_READS))
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__E2K_WAIT(_ld_c);
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return res;
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}
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static inline u32 native_readl_relaxed(const volatile void __iomem *addr)
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{
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u32 res = *(const volatile u32 __force *) addr;
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if (cpu_has(CPU_HWBUG_PIO_READS))
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__E2K_WAIT(_ld_c);
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return res;
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}
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static inline u64 native_readq_relaxed(const volatile void __iomem *addr)
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{
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u64 res = *(const volatile u64 __force *) addr;
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if (cpu_has(CPU_HWBUG_PIO_READS))
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__E2K_WAIT(_ld_c);
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return res;
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}
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static inline void native_writeb_relaxed(u8 value, volatile void __iomem *addr)
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{
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*(volatile u8 __force *) addr = value;
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}
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static inline void native_writew_relaxed(u16 value, volatile void __iomem *addr)
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{
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*(volatile u16 __force *) addr = value;
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}
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static inline void native_writel_relaxed(u32 value, volatile void __iomem *addr)
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{
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*(volatile u32 __force *) addr = value;
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}
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static inline void native_writeq_relaxed(u64 value, volatile void __iomem *addr)
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{
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*(volatile u64 __force *) addr = value;
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}
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/*
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* Strongly ordered accessors.
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*/
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static inline u8 native_readb(const volatile void __iomem *addr)
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{
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u8 res;
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if (cpu_has(CPU_FEAT_ISET_V6)) {
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LOAD_NV_MAS((volatile u8 __force *) addr, res,
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MAS_LOAD_ACQUIRE_V6(MAS_MT_0), b, "memory");
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} else {
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res = native_readb_relaxed(addr);
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}
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return res;
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}
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static inline u16 native_readw(const volatile void __iomem *addr)
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{
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u16 res;
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if (cpu_has(CPU_FEAT_ISET_V6)) {
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LOAD_NV_MAS((volatile u16 __force *) addr, res,
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MAS_LOAD_ACQUIRE_V6(MAS_MT_0), h, "memory");
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} else {
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res = native_readw_relaxed(addr);
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}
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return res;
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}
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static inline u32 native_readl(const volatile void __iomem *addr)
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{
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u32 res;
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if (cpu_has(CPU_FEAT_ISET_V6)) {
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LOAD_NV_MAS((volatile u32 __force *) addr, res,
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MAS_LOAD_ACQUIRE_V6(MAS_MT_0), w, "memory");
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} else {
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res = native_readl_relaxed(addr);
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}
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return res;
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}
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static inline u64 native_readq(const volatile void __iomem *addr)
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{
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u64 res;
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if (cpu_has(CPU_FEAT_ISET_V6)) {
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LOAD_NV_MAS((volatile u64 __force *) addr, res,
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MAS_LOAD_ACQUIRE_V6(MAS_MT_0), d, "memory");
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} else {
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res = native_readq_relaxed(addr);
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}
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return res;
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}
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static inline void native_writeb(u8 value, volatile void __iomem *addr)
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{
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if (cpu_has(CPU_FEAT_ISET_V6)) {
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STORE_NV_MAS((volatile u8 __force *) addr, value,
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MAS_STORE_RELEASE_V6(MAS_MT_0), b, "memory");
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/* wmb() after MMIO writes is not required by documentation, but
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* this is how x86 works and how most of the drivers are tested. */
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wmb();
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} else {
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native_writeb_relaxed(value, addr);
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}
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}
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static inline void native_writew(u16 value, volatile void __iomem *addr)
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{
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if (cpu_has(CPU_FEAT_ISET_V6)) {
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STORE_NV_MAS((volatile u16 __force *) addr, value,
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MAS_STORE_RELEASE_V6(MAS_MT_0), h, "memory");
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wmb();
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} else {
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native_writew_relaxed(value, addr);
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}
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}
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static inline void native_writel(u32 value, volatile void __iomem *addr)
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{
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if (cpu_has(CPU_FEAT_ISET_V6)) {
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STORE_NV_MAS((volatile u32 __force *) addr, value,
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MAS_STORE_RELEASE_V6(MAS_MT_0), w, "memory");
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wmb();
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} else {
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native_writel_relaxed(value, addr);
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}
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}
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static inline void native_writeq(u64 value, volatile void __iomem *addr)
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{
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if (cpu_has(CPU_FEAT_ISET_V6)) {
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STORE_NV_MAS((volatile u64 __force *) addr, value,
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MAS_STORE_RELEASE_V6(MAS_MT_0), d, "memory");
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wmb();
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} else {
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native_writeq_relaxed(value, addr);
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}
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}
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/*
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* Port accessors, also strongly ordered
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*/
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#if CONFIG_CPU_ISET >= 6
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# define __io_par() __E2K_WAIT(_ld_c | _sal | _lal)
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# define __io_pbw() __E2K_WAIT(_st_c | _sas | _ld_c | _sal)
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/* Not required by documentation, but this is how
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* x86 works and how most of the drivers are tested. */
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# define __io_paw() __E2K_WAIT(_st_c | _sas)
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#else
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# define __io_par() \
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do { \
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if (cpu_has(CPU_HWBUG_PIO_READS)) \
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__E2K_WAIT(_ld_c); \
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} while (0)
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# define __io_pbw()
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# define __io_paw()
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#endif
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static inline u8 native_inb(unsigned int port)
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{
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u8 byte = NATIVE_READ_MAS_B(X86_IO_AREA_PHYS_BASE + port, MAS_IOADDR);
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__io_par();
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return byte;
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}
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static inline u16 native_inw(unsigned int port)
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{
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u16 hword = NATIVE_READ_MAS_H(X86_IO_AREA_PHYS_BASE + port, MAS_IOADDR);
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__io_par();
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return hword;
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}
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static inline u32 native_inl(unsigned int port)
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{
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u32 word = NATIVE_READ_MAS_W(X86_IO_AREA_PHYS_BASE + port, MAS_IOADDR);
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__io_par();
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return word;
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}
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static inline void native_outb(u8 byte, unsigned int port)
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{
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__io_pbw();
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NATIVE_WRITE_MAS_B(X86_IO_AREA_PHYS_BASE + port, byte, MAS_IOADDR);
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__io_paw();
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}
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static inline void native_outw(u16 halfword, unsigned int port)
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{
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__io_pbw();
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NATIVE_WRITE_MAS_H(X86_IO_AREA_PHYS_BASE + port, halfword, MAS_IOADDR);
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__io_paw();
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}
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static inline void native_outl(u32 word, unsigned int port)
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{
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__io_pbw();
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NATIVE_WRITE_MAS_W(X86_IO_AREA_PHYS_BASE + port, word, MAS_IOADDR);
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__io_paw();
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}
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/*
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* Variants of inX/outX that repeatedly access the same port
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*/
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static inline void native_insb(unsigned short port, void *dst, unsigned long count)
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{
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u8 *b_p = dst;
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while (count--)
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*b_p++ = native_inb(port);
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}
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static inline void native_insw(unsigned short port, void *dst, unsigned long count)
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{
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u16 *hw_p = dst;
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while (count--)
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*hw_p++ = native_inw(port);
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}
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static inline void native_insl(unsigned short port, void *dst, unsigned long count)
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{
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u32 *l_p = dst;
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while (count--)
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*l_p++ = native_inl(port);
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}
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static inline void native_outsb(unsigned short port, const void *src, unsigned long count)
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{
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const u8 *b_p = src;
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while (count--)
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native_outb(*b_p++, port);
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}
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static inline void native_outsw(unsigned short port, const void *src, unsigned long count)
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{
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const u16 *hw_p = src;
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while (count--)
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native_outw(*hw_p++, port);
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}
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static inline void native_outsl(unsigned short port, const void *src, unsigned long count)
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{
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const u32 *l_p = src;
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while (count--)
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native_outl(*l_p++, port);
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}
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/*
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* And some e2k-specific accessors
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*/
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static inline void native_debug_cons_outb(u8 byte, u16 port)
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{
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native_outb(byte, port);
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}
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static inline u8 native_debug_cons_inb(u16 port)
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{
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return native_inb(port);
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}
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static inline u32 native_debug_cons_inl(u16 port)
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{
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return native_inl(port);
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}
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extern void native_conf_inb(unsigned int domain, unsigned int bus,
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unsigned long port, u8 *byte);
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extern void native_conf_inw(unsigned int domain, unsigned int bus,
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unsigned long port, u16 *hword);
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extern void native_conf_inl(unsigned int domain, unsigned int bus,
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unsigned long port, u32 *word);
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extern void native_conf_outb(unsigned int domain, unsigned int bus,
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unsigned long port, u8 byte);
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extern void native_conf_outw(unsigned int domain, unsigned int bus,
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unsigned long port, u16 hword);
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extern void native_conf_outl(unsigned int domain, unsigned int bus,
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unsigned long port, u32 word);
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#if defined CONFIG_KVM_GUEST_KERNEL
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/* it is pure guest kernel (not paravirtualized based on pv_ops) */
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# include <asm/kvm/guest/io.h>
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# define __raw_readb kvm_readb_relaxed
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# define __raw_readw kvm_readw_relaxed
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# define __raw_readl kvm_readl_relaxed
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# define __raw_readq kvm_readq_relaxed
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# define __raw_writeb kvm_writeb_relaxed
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# define __raw_writew kvm_writew_relaxed
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# define __raw_writel kvm_writel_relaxed
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# define __raw_writeq kvm_writeq_relaxed
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# define readb kvm_hv_readb
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# define readw kvm_hv_readw
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# define readl kvm_hv_readl
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# define readq kvm_hv_readq
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# define writeb kvm_hv_writeb
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# define writew kvm_hv_writew
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# define writel kvm_hv_writel
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# define writeq kvm_hv_writeq
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# define inb kvm_hv_inb
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# define inw kvm_hv_inw
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# define inl kvm_hv_inl
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# define outb kvm_hv_outb
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# define outw kvm_hv_outw
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# define outl kvm_hv_outl
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# define insb kvm_hv_insb
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# define insw kvm_hv_insw
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# define insl kvm_hv_insl
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# define outsb kvm_hv_outsb
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# define outsw kvm_hv_outsw
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# define outsl kvm_hv_outsl
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#elif defined CONFIG_PARAVIRT_GUEST
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/* it is paravirtualized host and guest kernel */
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# include <asm/paravirt/io.h>
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# define __raw_readb pv_readb
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# define __raw_readw pv_readw
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# define __raw_readl pv_readl
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# define __raw_readq pv_readq
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# define __raw_writeb pv_writeb
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# define __raw_writew pv_writew
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# define __raw_writel pv_writel
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# define __raw_writeq pv_writeq
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# define inb pv_inb
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# define inw pv_inw
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# define inl pv_inl
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# define outb pv_outb
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# define outw pv_outw
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# define outl pv_outl
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# define insb pv_insb
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# define insw pv_insw
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# define insl pv_insl
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# define outsb pv_outsb
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# define outsw pv_outsw
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# define outsl pv_outsl
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#else
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/* Native kernel - either host or without any virtualization at all */
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# define __raw_readb native_readb_relaxed
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# define __raw_readw native_readw_relaxed
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# define __raw_readl native_readl_relaxed
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# define __raw_readq native_readq_relaxed
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# define __raw_writeb native_writeb_relaxed
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# define __raw_writew native_writew_relaxed
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# define __raw_writel native_writel_relaxed
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# define __raw_writeq native_writeq_relaxed
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# define readb native_readb
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# define readw native_readw
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# define readl native_readl
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# define readq native_readq
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# define writeb native_writeb
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# define writew native_writew
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# define writel native_writel
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# define writeq native_writeq
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# define inb native_inb
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# define inw native_inw
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# define inl native_inl
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# define outb native_outb
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# define outw native_outw
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# define outl native_outl
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# define insb native_insb
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# define insw native_insw
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# define insl native_insl
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# define outsb native_outsb
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# define outsw native_outsw
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# define outsl native_outsl
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static inline void boot_writeb(u8 b, void __iomem *addr)
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{
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boot_native_writeb(b, addr);
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}
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static inline void boot_writew(u16 w, void __iomem *addr)
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{
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boot_native_writew(w, addr);
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}
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static inline void boot_writel(u32 l, void __iomem *addr)
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{
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boot_native_writel(l, addr);
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}
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static inline void boot_writeq(u64 q, void __iomem *addr)
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{
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boot_native_writeq(q, addr);
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}
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static inline u8 boot_readb(void __iomem *addr)
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{
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return boot_native_readb(addr);
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}
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static inline u16 boot_readw(void __iomem *addr)
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{
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return boot_native_readw(addr);
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}
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static inline u32 boot_readl(void __iomem *addr)
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{
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return boot_native_readl(addr);
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}
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static inline u64 boot_readq(void __iomem *addr)
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{
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return boot_native_readq(addr);
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}
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static inline void
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conf_inb(unsigned int domain, unsigned int bus, unsigned long port, u8 *byte)
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{
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native_conf_inb(domain, bus, port, byte);
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}
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static inline void
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conf_inw(unsigned int domain, unsigned int bus, unsigned long port, u16 *hword)
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{
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native_conf_inw(domain, bus, port, hword);
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}
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static inline void
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conf_inl(unsigned int domain, unsigned int bus, unsigned long port, u32 *word)
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{
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native_conf_inl(domain, bus, port, word);
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}
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static inline void
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conf_outb(unsigned int domain, unsigned int bus, unsigned long port, u8 byte)
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{
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native_conf_outb(domain, bus, port, byte);
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}
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static inline void
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conf_outw(unsigned int domain, unsigned int bus, unsigned long port, u16 hword)
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{
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native_conf_outw(domain, bus, port, hword);
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}
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static inline void
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conf_outl(unsigned int domain, unsigned int bus, unsigned long port, u32 word)
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{
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native_conf_outl(domain, bus, port, word);
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}
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static inline void debug_cons_outb(u8 byte, u16 port)
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{
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native_debug_cons_outb(byte, port);
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}
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static inline void debug_cons_outb_p(u8 byte, u16 port)
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{
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native_debug_cons_outb(byte, port);
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}
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static inline u8 debug_cons_inb(u16 port)
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{
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return native_debug_cons_inb(port);
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}
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static inline u32 debug_cons_inl(u16 port)
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{
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return native_debug_cons_inl(port);
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}
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static inline void boot_debug_cons_outb(u8 byte, u16 port)
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{
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boot_native_outb(byte, port);
|
|
}
|
|
static inline u8 boot_debug_cons_inb(u16 port)
|
|
{
|
|
return boot_native_inb(port);
|
|
}
|
|
static inline u32 boot_debug_cons_inl(u16 port)
|
|
{
|
|
return boot_native_inl(port);
|
|
}
|
|
|
|
static inline int __init arch_pci_init(void)
|
|
{
|
|
return native_arch_pci_init();
|
|
}
|
|
|
|
#endif
|
|
|
|
/*
|
|
* Map in an area of physical address space, for accessing
|
|
* I/O devices etc.
|
|
*/
|
|
#define ioremap_cache ioremap_cache
|
|
#define ioremap_wc ioremap_wc
|
|
#define ioremap_wt ioremap_wc
|
|
#define ioremap_nocache ioremap_nocache
|
|
#define ioremap_uc ioremap_nocache
|
|
#define ioremap ioremap_nocache
|
|
extern void __iomem *ioremap_cache(resource_size_t address, unsigned long size);
|
|
extern void __iomem *ioremap_wc(resource_size_t address, unsigned long size);
|
|
extern void __iomem *ioremap_nocache(resource_size_t address, unsigned long size);
|
|
|
|
#define iounmap iounmap
|
|
extern void iounmap(volatile void __iomem *addr);
|
|
|
|
#define ARCH_HAS_IOREMAP_WC
|
|
#define ARCH_HAS_IOREMAP_WT
|
|
|
|
|
|
extern void __memset_io(void *s, long c, size_t count);
|
|
|
|
#define memset_io(dst, c, n) _memset_io(dst, c, n, __alignof(*(dst)))
|
|
static inline void _memset_io(volatile void __iomem *dst, int c, size_t n,
|
|
const unsigned long dst_align)
|
|
{
|
|
long cc;
|
|
|
|
cc = c & 0xff;
|
|
cc = cc | (cc << 8);
|
|
cc = cc | (cc << 16);
|
|
cc = cc | (cc << 32);
|
|
|
|
if (__builtin_constant_p(n) && dst_align >= 8 && n < 136) {
|
|
/* Inline small aligned memset's */
|
|
volatile u64 __iomem *l_dst = dst;
|
|
|
|
if (n >= 8)
|
|
l_dst[0] = cc;
|
|
if (n >= 16)
|
|
l_dst[1] = cc;
|
|
if (n >= 24)
|
|
l_dst[2] = cc;
|
|
if (n >= 32)
|
|
l_dst[3] = cc;
|
|
if (n >= 40)
|
|
l_dst[4] = cc;
|
|
if (n >= 48)
|
|
l_dst[5] = cc;
|
|
if (n >= 56)
|
|
l_dst[6] = cc;
|
|
if (n >= 64)
|
|
l_dst[7] = cc;
|
|
if (n >= 72)
|
|
l_dst[8] = cc;
|
|
if (n >= 80)
|
|
l_dst[9] = cc;
|
|
if (n >= 88)
|
|
l_dst[10] = cc;
|
|
if (n >= 96)
|
|
l_dst[11] = cc;
|
|
if (n >= 104)
|
|
l_dst[12] = cc;
|
|
if (n >= 112)
|
|
l_dst[13] = cc;
|
|
if (n >= 120)
|
|
l_dst[14] = cc;
|
|
if (n >= 128)
|
|
l_dst[15] = cc;
|
|
|
|
/* Set the tail */
|
|
if (n & 4)
|
|
*(u32 __iomem *) (dst + (n & ~0x7UL)) = cc;
|
|
if (n & 2)
|
|
*(u16 __iomem *) (dst + (n & ~0x3UL)) = cc;
|
|
if (n & 1)
|
|
*(u8 __iomem *) (dst + (n & ~0x1UL)) = cc;
|
|
} else {
|
|
__memset_io((void * __force) dst, cc, n);
|
|
}
|
|
}
|
|
|
|
extern void __memcpy_fromio(void *dst, const void *src, size_t n);
|
|
extern void __memcpy_toio(void *dst, const void *src, size_t n);
|
|
#define memcpy_fromio(a, b, c) __memcpy_fromio((a), (void * __force) (b), (c))
|
|
#define memcpy_toio(a, b, c) __memcpy_toio((void * __force) (a), (b), (c))
|
|
|
|
|
|
#include <asm-generic/io.h>
|
|
#undef PCI_IOBASE
|
|
|
|
|
|
extern unsigned long get_domain_pci_conf_base(unsigned int domain);
|
|
extern unsigned long get_domain_pci_conf_size(unsigned int domain);
|
|
|
|
/*
|
|
* ISA I/O bus memory addresses are 1:1 with the physical address.
|
|
*/
|
|
#define isa_virt_to_bus virt_to_phys
|
|
|
|
#endif /* _E2K_IO_H_ */
|