476 lines
15 KiB
C
476 lines
15 KiB
C
#ifndef _E2K_IRQFLAGS_H_
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#define _E2K_IRQFLAGS_H_
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#ifndef __ASSEMBLY__
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#ifndef _LINUX_TRACE_IRQFLAGS_H
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# error "Do not include <asm/irqflags.h> directly; use <linux/irqflags.h> instead."
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#endif
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#include <asm/system.h>
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/*
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* There are two registers to control interrupts (enable/disable)
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*
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* The main register is privileged register PSR,
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*
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* the seconde is nonprivileged UPSR.
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*
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* PSR bits should enable interrupts and enable user interrupts to use UPSR
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* as control interrupts register.
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*
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* Principal difference between two registers is scope. UPSR is global
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* register: its scope is all execution, if some function enables/disables
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* interrupts in UPSR and returns to caller then caller will have enabled/
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* disabled interrupts as well. PSR is local register: its scope is current
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* function, and all invoked functions inherit its PSR state, but if invoked
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* function changes PSR and returns, then current function (caller) will see
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* own unchanged PSR state.
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*
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* (PSR is saved by call operation and is restored by return operation from
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* chine registers).
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*
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* So in PSR case, in particular, if interrupts are enabled/disabled
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* by some function call, then it is an error - interrupts enable/disable
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* state will be unchanged. But it is not error in UPSR case.
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*
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* Interrupts control using PSR requires structured kernel organization and
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* it can be permited only inheritance of interrupts enable/disable state
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* (from caller to invoked function) and it cannot be permited return of
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* interrupts enable/disable state (to caller)
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*
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* There is doubt that we should use interrupts control under UPSR
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*
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*
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* PSR and UPSR bits are used to enable and disable interrupts.
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*
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* PSR bits are used while:
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* - A user process executes;
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* - Trap or interrupt occures on user or kernel process, hardware
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* disables interrupts mask in PSR and PSR becomes main register to control
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* interrupts. Trap handler switches control from PSR register to UPSR
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* in the appropriate point and all following trap handling is done under
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* UPSR control;
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* - Trap handler returns control from UPSR to PSR in the appropriate
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* point of trap handling end. Return from trap handler (DONE) restores
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* PSR from CR register and recovers interrupts control type in the trap point;
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* - System call is same as trap (see above);
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* - System call end is same as trap handler end (see above);
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* - Switch from kernel process to user (exec() and signal handler)
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* is same as trap handler end. Before return to user function kernel sets
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* control under PSR and (only for signal handler) after return from user
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* recovers control under UPSR.
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*
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* Kernel cannot use standard macros, functions to enable / disable
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* interrupts same as local_irq_xxx() spin_lock_irq_xxx() ... while
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* interrupts are controled by PSR.
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*
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* UPSR bits are used by kernel while:
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* Kernel jumpstart (system call #12) set UPSR register in the
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* initial state (where interrupts are disabled) and switches
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* control from PSR register to UPSR; From this point kernel runs
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* (except cases listed above for PSR) under UPSR interrupt bits
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*/
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#define NATIVE_SWITCH_IRQ_TO_UPSR() \
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NATIVE_WRITE_PSR_IRQ_BARRIER(AW(E2K_KERNEL_PSR_ENABLED))
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#define NATIVE_RETURN_IRQ_TO_PSR() \
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NATIVE_WRITE_PSR_IRQ_BARRIER(AW(E2K_KERNEL_PSR_DISABLED))
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#define NATIVE_SET_USER_INITIAL_UPSR(upsr) \
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({ \
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NATIVE_RETURN_IRQ_TO_PSR(); \
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NATIVE_WRITE_UPSR_REG(upsr); \
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})
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#define BOOT_NATIVE_SWITCH_IRQ_TO_UPSR() \
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BOOT_NATIVE_WRITE_PSR_REG_VALUE(AW(E2K_KERNEL_PSR_ENABLED))
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#define SWITCH_IRQ_TO_UPSR(set_cr1_lo) \
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do { \
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if (set_cr1_lo) { \
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e2k_cr1_lo_t cr1_lo = READ_CR1_LO_REG(); \
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AS(cr1_lo).ie = 1; \
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AS(cr1_lo).nmie = 1; \
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AS(cr1_lo).uie = 1; \
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AS(cr1_lo).unmie = 1; \
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WRITE_CR1_LO_REG(cr1_lo); \
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} \
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\
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WRITE_PSR_IRQ_BARRIER(AW(E2K_KERNEL_PSR_ENABLED)); \
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} while (0)
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#define BOOT_SWITCH_IRQ_TO_UPSR() \
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BOOT_WRITE_PSR_REG_VALUE(AW(E2K_KERNEL_PSR_ENABLED))
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#define UPSR_STI() \
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({ \
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condition_collect_disable_interrupt_ticks( \
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READ_UPSR_REG_VALUE() & ~UPSR_IE); \
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WRITE_UPSR_IRQ_BARRIER(AW(E2K_KERNEL_UPSR_ENABLED)); \
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})
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#define UPSR_CLI() \
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({ \
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WRITE_UPSR_IRQ_BARRIER(AW(E2K_KERNEL_UPSR_DISABLED)); \
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condition_mark_disable_interrupt_ticks(1); \
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})
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#define UPSR_SAVE_AND_CLI() \
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({ \
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unsigned long __flags = READ_UPSR_REG_VALUE(); \
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WRITE_UPSR_IRQ_BARRIER(AW(E2K_KERNEL_UPSR_DISABLED)); \
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condition_mark_disable_interrupt_ticks(1); \
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__flags; \
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})
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#define UPSR_SAVE() READ_UPSR_REG_VALUE()
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/*
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* nmi_* versions work only with non-maskbale ones interrupts.
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*/
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#define upsr_nmi_irqs_disabled() \
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((READ_UPSR_REG_VALUE() & UPSR_NMIE) == 0)
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#define upsr_nmi_irqs_disabled_flags(flags) \
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((flags & UPSR_NMIE) == 0)
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#define NATIVE_UPSR_NMI_SAVE_AND_CLI(flags) \
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({ \
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flags = NATIVE_NV_READ_UPSR_REG_VALUE(); \
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NATIVE_WRITE_UPSR_IRQ_BARRIER(flags & ~UPSR_NMIE); \
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condition_mark_disable_interrupt_ticks(1); \
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})
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#define NATIVE_UPSR_NMI_STI(flags) \
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({ \
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NATIVE_WRITE_UPSR_IRQ_BARRIER((flags) | UPSR_NMIE); \
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condition_mark_disable_interrupt_ticks(0); \
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})
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#define NATIVE_UPSR_ALL_SAVE_AND_CLI(flags) \
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({ \
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flags = NATIVE_NV_READ_UPSR_REG_VALUE(); \
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NATIVE_WRITE_UPSR_IRQ_BARRIER( \
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AW(E2K_KERNEL_UPSR_DISABLED_ALL)); \
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condition_mark_disable_interrupt_ticks(1); \
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})
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/*
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* all_* versions work on all interrupts including
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* both maskable and non-maskbale ones.
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*/
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#define UPSR_ALL_STI() \
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({ \
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condition_collect_disable_interrupt_ticks( \
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READ_UPSR_REG_VALUE() & ~UPSR_IE & ~UPSR_NMIE); \
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WRITE_UPSR_IRQ_BARRIER(AW(E2K_KERNEL_UPSR_ENABLED)); \
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})
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#define UPSR_ALL_CLI() \
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({ \
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WRITE_UPSR_IRQ_BARRIER(AW(E2K_KERNEL_UPSR_DISABLED_ALL)); \
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condition_mark_disable_interrupt_ticks(1); \
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})
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#define UPSR_ALL_SAVE_AND_CLI(flags) \
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({ \
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flags = READ_UPSR_REG_VALUE(); \
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WRITE_UPSR_IRQ_BARRIER(AW(E2K_KERNEL_UPSR_DISABLED_ALL)); \
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condition_mark_disable_interrupt_ticks(1); \
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})
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#define BOOT_UPSR_ALL_STI() \
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({ \
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unsigned long last_upsr = BOOT_READ_UPSR_REG_VALUE(); \
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unsigned long cur_upsr; \
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cur_upsr = last_upsr | (UPSR_IE | UPSR_NMIE); \
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BOOT_WRITE_UPSR_REG_VALUE(cur_upsr); \
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})
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#define BOOT_UPSR_ALL_CLI() \
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({ \
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unsigned long last_upsr = BOOT_READ_UPSR_REG_VALUE(); \
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unsigned long cur_upsr; \
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cur_upsr = last_upsr & ~(UPSR_IE | UPSR_NMIE); \
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BOOT_WRITE_UPSR_REG_VALUE(cur_upsr); \
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})
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#define BOOT_UPSR_ALL_SAVE_AND_CLI(flags) \
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({ \
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flags = BOOT_READ_UPSR_REG_VALUE(); \
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BOOT_WRITE_UPSR_REG_VALUE(flags & ~(UPSR_IE | UPSR_NMIE)); \
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})
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#define BOOT_UPSR_SAVE(src_upsr) \
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(src_upsr = BOOT_READ_UPSR_REG_VALUE())
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#define BOOT_UPSR_RESTORE(src_upsr) \
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BOOT_WRITE_UPSR_REG_VALUE(src_upsr)
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#define psr_irqs_disabled_flags(flags) (((flags) & PSR_IE) == 0)
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#define upsr_irqs_disabled_flags(flags) (((flags) & UPSR_IE) == 0)
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#define irqs_under_upsr_flags(psr_flags) (((psr_flags) & PSR_UIE) != 0)
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#define psr_and_upsr_irqs_disabled_flags(psr_flags, upsr_flags) \
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({ \
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bool ret; \
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if (psr_irqs_disabled_flags(psr_flags)) { \
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ret = true; \
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} else if (irqs_under_upsr_flags(psr_flags)) { \
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ret = upsr_irqs_disabled_flags(upsr_flags); \
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} else { \
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ret = false; \
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} \
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ret; \
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})
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#define upsr_all_irqs_disabled_flags(flags) \
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((flags & (UPSR_IE | UPSR_NMIE)) == 0)
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#define upsr_all_irqs_disabled() \
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upsr_all_irqs_disabled_flags(READ_UPSR_REG_VALUE())
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#define psr_all_irqs_disabled_flags(flags) \
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((flags & (PSR_IE | PSR_NMIE)) == 0)
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#define psr_all_irqs_enabled_flags(flags) \
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((flags & (PSR_IE | PSR_NMIE)) == (PSR_IE | PSR_NMIE))
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#define psr_all_irqs_disabled() \
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psr_all_irqs_disabled_flags(READ_PSR_REG_VALUE())
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#define all_irqs_under_upsr_flags(psr_flags) \
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(((psr_flags) & (PSR_UIE | PSR_UNMIE)) != 0)
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#define psr_and_upsr_all_irqs_disabled_flags(psr_flags, upsr_flags) \
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({ \
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bool ret; \
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if (psr_all_irqs_disabled_flags(psr_flags)) { \
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ret = true; \
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} else if (all_irqs_under_upsr_flags(psr_flags)) { \
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ret = upsr_all_irqs_disabled_flags(upsr_flags); \
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} else { \
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ret = false; \
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} \
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ret; \
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})
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#define psr_irqs_disabled() \
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psr_irqs_disabled_flags(READ_PSR_REG_VALUE())
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#define upsr_irqs_disabled() \
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upsr_irqs_disabled_flags(READ_UPSR_REG_VALUE())
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#define psr_and_upsr_irqs_disabled() \
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({ \
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unsigned long psr = READ_PSR_REG_VALUE(); \
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unsigned long upsr = READ_UPSR_REG_VALUE(); \
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\
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psr_and_upsr_irqs_disabled_flags(psr, upsr); \
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})
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#define psr_and_upsr_all_irqs_disabled() \
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({ \
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unsigned long psr = READ_PSR_REG_VALUE(); \
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unsigned long upsr = READ_UPSR_REG_VALUE(); \
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\
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psr_and_upsr_all_irqs_disabled_flags(psr, upsr); \
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})
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#define __raw_all_irqs_disabled() psr_and_upsr_all_irqs_disabled()
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#define native_psr_irqs_disabled() \
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psr_irqs_disabled_flags(NATIVE_NV_READ_PSR_REG_VALUE())
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#define psr_and_upsr_nm_irqs_disabled() \
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({ \
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int ret; \
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unsigned long psr = READ_PSR_REG_VALUE(); \
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if ((psr & PSR_NMIE) == 0) { \
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ret = 1; \
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} else if (psr & PSR_UNMIE) { \
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ret = !(READ_UPSR_REG_VALUE() & UPSR_NMIE); \
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} else { \
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ret = 0; \
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} \
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ret; \
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})
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#ifndef CONFIG_DEBUG_IRQ
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#define __raw_irqs_disabled() upsr_irqs_disabled()
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#else
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#define __raw_irqs_disabled() psr_and_upsr_irqs_disabled()
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#endif /* ! CONFIG_DEBUG_IRQ */
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#define __raw_irqs_disabled_flags(flags) ((flags & UPSR_IE) == 0)
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#ifdef CONFIG_MCST_RT
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#define SAVE_CURR_TIME_SWITCH_TO \
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{ \
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cpu_times[raw_smp_processor_id()].curr_time_switch_to = \
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READ_CLKR_REG_VALUE(); \
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}
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#define CALCULATE_TIME_SWITCH_TO \
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{ \
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int cpu = raw_smp_processor_id(); \
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cpu_times[cpu].curr_time_switch_to = READ_CLKR_REG_VALUE() - \
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cpu_times[cpu].curr_time_switch_to; \
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if (cpu_times[cpu].curr_time_switch_to < \
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cpu_times[cpu].min_time_switch_to){ \
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cpu_times[cpu].min_time_switch_to = \
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cpu_times[cpu].curr_time_switch_to; \
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} \
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if (cpu_times[cpu].curr_time_switch_to > \
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cpu_times[cpu].max_time_switch_to){ \
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cpu_times[cpu].max_time_switch_to = \
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cpu_times[cpu].curr_time_switch_to; \
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} \
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}
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#else /* !CONFIG_MCST_RT */
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#define SAVE_CURR_TIME_SWITCH_TO
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#define CALCULATE_TIME_SWITCH_TO
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#endif /* CONFIG_MCST_RT */
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#ifdef CONFIG_CLI_CHECK_TIME
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typedef struct cli_info {
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long cli;
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long max_cli;
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long max_cli_cl;
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long max_cli_ip;
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long gcli;
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long max_gcli;
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long max_gcli_cl;
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long max_gcli_ip;
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} cli_info_t;
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typedef struct tt0_info {
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long max_tt0_prolog;
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long max_tt0_cl;
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} tt0_info_t;
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extern cli_info_t cli_info[];
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extern tt0_info_t tt0_info[];
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extern int cli_info_needed;
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extern void tt0_prolog_ticks(long ticks);
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#define Cli_cl cli_info[raw_smp_processor_id()].cli
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#define Max_cli cli_info[raw_smp_processor_id()].max_cli
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#define Max_cli_cl cli_info[raw_smp_processor_id()].max_cli_cl
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#define Max_cli_ip cli_info[raw_smp_processor_id()].max_cli_ip
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#define Cli_irq cli_info[raw_smp_processor_id()].irq
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#define Gcli_cl cli_info[raw_smp_processor_id()].gcli
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#define Max_gcli cli_info[raw_smp_processor_id()].max_gcli
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#define Max_gcli_cl cli_info[raw_smp_processor_id()].max_gcli_cl
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#define Max_gcli_ip cli_info[raw_smp_processor_id()].max_gcli_ip
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#define Max_tt0_prolog tt0_info[raw_smp_processor_id()].max_tt0_prolog
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#define Max_tt0_cl tt0_info[raw_smp_processor_id()].max_tt0_cl
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#define e2k_cli() \
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{ \
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bool __save_time = cli_info_needed && !__raw_irqs_disabled(); \
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UPSR_CLI(); \
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if (__save_time) \
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Cli_cl = READ_CLKR_REG_VALUE(); \
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}
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#define e2k_sti() \
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{ \
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if (Cli_cl && __raw_irqs_disabled() && \
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(Max_cli < READ_CLKR_REG_VALUE() - Cli_cl)) { \
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Max_cli = READ_CLKR_REG_VALUE() - Cli_cl; \
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Max_cli_cl = Cli_cl; \
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Max_cli_ip = READ_IP_REG_VALUE(); \
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} \
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UPSR_STI(); \
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}
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// check_cli() works under cli() but we want to check time of cli()
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#define check_cli() \
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{ \
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if (cli_info_needed) { \
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Cli_cl = READ_CLKR_REG_VALUE(); \
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} \
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}
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#define sti_return() \
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{ \
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if (cli_info_needed && __raw_irqs_disabled() && \
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(Max_cli < READ_CLKR_REG_VALUE() - Cli_cl)) { \
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Max_cli = READ_CLKR_REG_VALUE() - Cli_cl; \
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Max_cli_cl = Cli_cl; \
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Max_cli_ip = READ_IP_REG_VALUE(); \
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} \
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}
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#else /* above CONFIG_CLI_CHECK_TIME */
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#define e2k_cli() UPSR_CLI()
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#define e2k_sti() UPSR_STI()
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#define check_cli()
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#define sti_return()
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#endif /* CONFIG_CLI_CHECK_TIME */
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/* Normal irq operations: disable maskable interrupts only,
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* but enable both maskable and non-maskable interrupts. */
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#define arch_local_irq_enable() e2k_sti()
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#define arch_local_irq_disable() e2k_cli()
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#define arch_local_irq_save() UPSR_SAVE_AND_CLI()
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#define arch_local_irq_restore(x) UPSR_RESTORE(x)
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#define arch_local_save_flags() UPSR_SAVE()
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#define arch_irqs_disabled_flags(x) __raw_irqs_disabled_flags(x)
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#define arch_irqs_disabled() __raw_irqs_disabled()
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/* nmi_irq_*() - the same as above, but checks only non-maskable interrupts. */
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#define raw_nmi_irqs_disabled_flags(x) upsr_nmi_irqs_disabled_flags(x)
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#define raw_nmi_irqs_disabled() upsr_nmi_irqs_disabled()
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/* all_irq_*() - the same as above, but enables, disables and checks
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* both non-maskable and maskable interrupts. */
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#define raw_all_irq_enable() UPSR_ALL_STI()
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#define raw_all_irq_disable() UPSR_ALL_CLI()
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#define boot_raw_all_irq_enable() BOOT_UPSR_ALL_STI()
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#define boot_raw_all_irq_disable() BOOT_UPSR_ALL_CLI()
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#define raw_all_irq_save(x) UPSR_ALL_SAVE_AND_CLI(x)
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#define raw_all_irq_restore(x) UPSR_RESTORE(x)
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#define boot_raw_all_irq_save(x) BOOT_UPSR_ALL_SAVE_AND_CLI(x)
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#define boot_raw_all_irq_restore(x) BOOT_UPSR_RESTORE(x)
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#define raw_all_irqs_disabled_flags(x) upsr_all_irqs_disabled_flags(x)
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#define raw_all_irqs_disabled() upsr_all_irqs_disabled()
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#define all_irq_enable() \
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do { trace_hardirqs_on(); raw_all_irq_enable(); } while (0)
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#define all_irq_disable() \
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do { raw_all_irq_disable(); trace_hardirqs_off(); } while (0)
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#define all_irq_save(flags) \
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do { \
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typecheck(unsigned long, flags); \
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raw_all_irq_save(flags); \
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trace_hardirqs_off(); \
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} while (0)
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#define all_irq_restore(flags) \
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do { \
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typecheck(unsigned long, flags); \
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if (raw_all_irqs_disabled_flags(flags)) { \
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raw_all_irq_restore(flags); \
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trace_hardirqs_off(); \
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} else { \
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trace_hardirqs_on(); \
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raw_all_irq_restore(flags); \
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} \
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} while (0)
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/*
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* Used in the idle loop
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*/
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static inline void arch_safe_halt(void)
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{
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _E2K_IRQFLAGS_H_ */
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