300 lines
9.0 KiB
C
300 lines
9.0 KiB
C
#ifndef _E2K_KVM_CPU_HV_REGS_ACCESS_H_
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#define _E2K_KVM_CPU_HV_REGS_ACCESS_H_
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <linux/kvm_host.h>
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#include <asm/e2k_api.h>
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#include <asm/cpu_regs_types.h>
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#include <asm/kvm/cpu_hv_regs_types.h>
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#include <asm/machdep.h>
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/*
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* Virtualization control registers
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*/
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#define READ_VIRT_CTRL_CU_REG() \
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((virt_ctrl_cu_t) { .word = NATIVE_GET_DSREG_CLOSED(virt_ctrl_cu) })
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/* Bug #127239: on some CPUs "rwd %virt_ctrl_cu" instruction must also
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* contain a NOP. This is already accomplished by using delay "5" here. */
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#define WRITE_VIRT_CTRL_CU_REG(v) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(virt_ctrl_cu, ((virt_ctrl_cu_t) (v)).word, 5)
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/* Shadow CPU registers */
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/*
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* Read/write low/high double-word OS Compilation Unit Descriptor (SH_OSCUD)
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*/
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#define READ_SH_OSCUD_LO_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_oscud.lo)
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#define READ_SH_OSCUD_HI_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_oscud.hi)
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#define WRITE_SH_OSCUD_LO_REG_VALUE(OSCUD_lo_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_oscud.lo, OSCUD_lo_value, 5)
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#define WRITE_SH_OSCUD_HI_REG_VALUE(OSCUD_hi_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_oscud.hi, OSCUD_hi_value, 5)
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#define WRITE_SH_OSCUD_LO_REG(OSCUD_lo) \
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({ \
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WRITE_SH_OSCUD_LO_REG_VALUE(OSCUD_lo.OSCUD_lo_half); \
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})
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#define WRITE_SH_OSCUD_HI_REG(OSCUD_hi) \
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({ \
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WRITE_SH_OSCUD_HI_REG_VALUE(OSCUD_hi.OSCUD_hi_half); \
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})
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#define WRITE_SH_OSCUD_REG_VALUE(OSCUD_hi_value, OSCUD_lo_value) \
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({ \
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WRITE_SH_OSCUD_LO_REG_VALUE(OSCUD_hi_value); \
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WRITE_SH_OSCUD_HI_REG_VALUE(OSCUD_lo_value); \
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})
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#define WRITE_SH_OSCUD_REG(OSCUD_hi, OSCUD_lo) \
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({ \
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WRITE_SH_OSCUD_REG_VALUE(OSCUD_hi.OSCUD_hi_half, \
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OSCUD_lo.OSCUD_lo_half); \
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})
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/*
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* Read/write low/hgh double-word OS Globals Register (SH_OSGD)
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*/
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#define READ_SH_OSGD_LO_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_osgd.lo)
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#define READ_SH_OSGD_HI_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_osgd.hi)
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#define WRITE_SH_OSGD_LO_REG_VALUE(OSGD_lo_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_osgd.lo, OSGD_lo_value, 5)
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#define WRITE_SH_OSGD_HI_REG_VALUE(OSGD_hi_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_osgd.hi, OSGD_hi_value, 5)
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#define WRITE_SH_OSGD_LO_REG(OSGD_lo) \
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({ \
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WRITE_SH_OSGD_LO_REG_VALUE(OSGD_lo.OSGD_lo_half); \
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})
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#define WRITE_SH_OSGD_HI_REG(OSGD_hi) \
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({ \
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WRITE_SH_OSGD_HI_REG_VALUE(OSGD_hi.OSGD_hi_half); \
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})
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#define WRITE_SH_OSGD_REG_VALUE(OSGD_hi_value, OSGD_lo_value) \
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({ \
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WRITE_SH_OSGD_HI_REG_VALUE(OSGD_hi_value); \
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WRITE_SH_OSGD_LO_REG_VALUE(OSGD_lo_value); \
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})
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#define WRITE_SH_OSGD_REG(OSGD_hi, OSGD_lo) \
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({ \
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WRITE_SH_OSGD_REG_VALUE(OSGD_hi.OSGD_hi_half, \
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OSGD_lo.OSGD_lo_half); \
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})
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/*
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* Read/write low/high quad-word Procedure Stack Pointer Register
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* (SH_PSP, backup BU_PSP)
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*/
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#define READ_SH_PSP_LO_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_psp.lo)
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#define READ_SH_PSP_HI_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_psp.hi)
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#define READ_BU_PSP_LO_REG_VALUE() NATIVE_GET_DSREG_CLOSED(bu_psp.lo)
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#define READ_BU_PSP_HI_REG_VALUE() NATIVE_GET_DSREG_CLOSED(bu_psp.hi)
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#define WRITE_SH_PSP_LO_REG_VALUE(PSP_lo_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_psp.lo, PSP_lo_value, 5)
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#define WRITE_SH_PSP_HI_REG_VALUE(PSP_hi_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_psp.hi, PSP_hi_value, 5)
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#define WRITE_BU_PSP_LO_REG_VALUE(PSP_lo_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(bu_psp.lo, PSP_lo_value, 5)
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#define WRITE_BU_PSP_HI_REG_VALUE(PSP_hi_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(bu_psp.hi, PSP_hi_value, 5)
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/*
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* Read/write word Procedure Stack Harware Top Pointer (SH_PSHTP)
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*/
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#define READ_SH_PSHTP_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_pshtp)
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#define WRITE_SH_PSHTP_REG_VALUE(PSHTP_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_pshtp, PSHTP_value, 5)
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/*
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* Read/write low/high quad-word Procedure Chain Stack Pointer Register
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* (SH_PCSP, backup registers BU_PCSP)
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*/
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#define READ_SH_PCSP_LO_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_pcsp.lo)
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#define READ_SH_PCSP_HI_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_pcsp.hi)
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#define READ_BU_PCSP_LO_REG_VALUE() NATIVE_GET_DSREG_CLOSED(bu_pcsp.lo)
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#define READ_BU_PCSP_HI_REG_VALUE() NATIVE_GET_DSREG_CLOSED(bu_pcsp.hi)
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#define WRITE_SH_PCSP_LO_REG_VALUE(PCSP_lo_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_pcsp.lo, PCSP_lo_value, 5)
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#define WRITE_SH_PCSP_HI_REG_VALUE(PCSP_hi_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_pcsp.hi, PCSP_hi_value, 5)
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#define WRITE_BU_PCSP_LO_REG_VALUE(PCSP_lo_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(bu_pcsp.lo, PCSP_lo_value, 5)
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#define WRITE_BU_PCSP_HI_REG_VALUE(PCSP_hi_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(bu_pcsp.hi, PCSP_hi_value, 5)
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/*
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* Read/write word Procedure Chain Stack Harware Top Pointer (SH_PCSHTP)
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* and shadow pointer (SH_PCSHTP)
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*/
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#define READ_SH_PCSHTP_REG_VALUE() \
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NATIVE_GET_SREG_CLOSED(sh_pcshtp)
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#define READ_SH_PCSHTP_REG_SVALUE() \
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PCSHTP_SIGN_EXTEND(NATIVE_GET_SREG_CLOSED(sh_pcshtp))
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#define WRITE_SH_PCSHTP_REG_SVALUE(PCSHTP_svalue) \
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NATIVE_SET_SREG_CLOSED_NOEXC(sh_pcshtp, PCSHTP_svalue, 5)
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/*
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* Read/write current window descriptor register (SH_WD)
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*/
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#define READ_SH_WD_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_wd)
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#define WRITE_SH_WD_REG_VALUE(WD_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_wd, WD_value, 5)
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/*
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* Read/write OS register which point to current process thread info
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* structure (SH_OSR0)
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*/
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#define READ_SH_OSR0_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_osr0)
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#define WRITE_SH_OSR0_REG_VALUE(osr0_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_osr0, osr0_value, 5)
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/*
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* Read/Write system clock registers (SH_SCLKM3)
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*/
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#define READ_SH_SCLKM3_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_sclkm3)
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#define WRITE_SH_SCLKM3_REG_VALUE(reg_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_sclkm3, reg_value, 4)
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/*
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* Read/write double-word Compilation Unit Table Register (SH_OSCUTD)
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*/
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#define READ_SH_OSCUTD_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sh_oscutd)
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#define WRITE_SH_OSCUTD_REG_VALUE(CUTD_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_oscutd, CUTD_value, 7)
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#define WRITE_SH_OSCUTD_REG(value) WRITE_SH_OSCUTD_REG_VALUE(AW(value))
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/*
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* Read/write word Compilation Unit Index Register (SH_OSCUIR)
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*/
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#define READ_SH_OSCUIR_REG_VALUE() NATIVE_GET_SREG_CLOSED(sh_oscuir)
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#define WRITE_SH_OSCUIR_REG_VALUE(CUIR_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sh_oscuir, CUIR_value, 7)
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#define WRITE_SH_OSCUIR_REG(value) WRITE_SH_OSCUIR_REG_VALUE(AW(value))
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/*
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* Read/Write Processor Core Mode Register (SH_CORE_MODE)
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*/
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#define READ_SH_CORE_MODE_REG_VALUE() NATIVE_GET_SREG_CLOSED(sh_core_mode)
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#define WRITE_SH_CORE_MODE_REG_VALUE(modes) \
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NATIVE_SET_SREG_CLOSED_NOEXC(sh_core_mode, modes, 5)
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#ifdef CONFIG_VIRTUALIZATION
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static inline e2k_core_mode_t read_SH_CORE_MODE_reg(void)
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{
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e2k_core_mode_t core_mode;
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core_mode.CORE_MODE_reg = machine.host.read_SH_CORE_MODE();
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return core_mode;
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}
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static inline void write_SH_CORE_MODE_reg(e2k_core_mode_t core_mode)
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{
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machine.host.write_SH_CORE_MODE(core_mode.CORE_MODE_reg);
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}
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#endif /* CONFIG_VIRTUALIZATION */
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#define READ_G_PREEMPT_TMR_REG() \
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((e2k_g_preempt_tmr_t) NATIVE_GET_SREG_CLOSED(g_preempt_tmr))
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#define WRITE_G_PREEMPT_TMR_REG(x) \
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NATIVE_SET_SREG_CLOSED_NOEXC(g_preempt_tmr, AW(x), 5)
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#define READ_INTC_PTR_CU() NATIVE_GET_DSREG_CLOSED(intc_ptr_cu)
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#define READ_INTC_INFO_CU() NATIVE_GET_DSREG_CLOSED(intc_info_cu)
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#define WRITE_INTC_INFO_CU(x) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(intc_info_cu, x, 5)
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static inline void save_intc_info_cu(intc_info_cu_t *info, int *num)
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{
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u64 info_ptr, i = 0;
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/*
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* The read of INTC_PTR will clear the hardware pointer,
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* but the subsequent reads fo INTC_INFO will increase
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* it again until it reaches the same value it had before.
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*/
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info_ptr = READ_INTC_PTR_CU();
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if (!info_ptr) {
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*num = -1;
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AW(info->header.lo) = 0;
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AW(info->header.hi) = 0;
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return;
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}
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/*
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* CU header should be cleared --- fg@mcst.ru
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*/
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AW(info->header.lo) = READ_INTC_INFO_CU();
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AW(info->header.hi) = READ_INTC_INFO_CU();
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READ_INTC_PTR_CU();
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WRITE_INTC_INFO_CU(0ULL);
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WRITE_INTC_INFO_CU(0ULL);
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info_ptr -= 2;
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/*
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* Read intercepted events list
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*/
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for (; info_ptr > 0; info_ptr -= 2) {
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AW(info->entry[i].lo) = READ_INTC_INFO_CU();
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info->entry[i].hi = READ_INTC_INFO_CU();
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info->entry[i].no_restore = false;
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++i;
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};
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*num = i;
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}
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static inline void restore_intc_info_cu(const intc_info_cu_t *info, int num)
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{
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int i;
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/*
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* 1) Clear the hardware pointer
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*/
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READ_INTC_PTR_CU();
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if (num == -1)
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return;
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/*
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* 2) Write the registers
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*
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* CU header should be cleared --- fg@mcst.ru
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*/
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WRITE_INTC_INFO_CU(0ULL);
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WRITE_INTC_INFO_CU(0ULL);
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for (i = 0; i < num; i++) {
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if (!info->entry[i].no_restore) {
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WRITE_INTC_INFO_CU(AW(info->entry[i].lo));
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WRITE_INTC_INFO_CU(info->entry[i].hi);
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}
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}
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}
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static inline void
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kvm_reset_intc_info_cu_is_updated(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.intc_ctxt.cu_updated = false;
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}
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static inline void
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kvm_set_intc_info_cu_is_updated(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.intc_ctxt.cu_updated = true;
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}
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static inline bool
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kvm_get_intc_info_cu_is_updated(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.intc_ctxt.cu_updated;
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _E2K_KVM_CPU_HV_REGS_ACCESS_H_ */
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