367 lines
12 KiB
C
367 lines
12 KiB
C
#ifndef _E2K_KVM_CPU_HV_REGS_TYPES_H_
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#define _E2K_KVM_CPU_HV_REGS_TYPES_H_
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#ifdef __KERNEL__
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#include <asm/types.h>
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#ifndef __ASSEMBLY__
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typedef union virt_ctrl_cu {
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struct {
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u64 evn_c : 16; /* [15: 0] */
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u64 exc_c : 8; /* [23:16] */
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u64 glnch : 2; /* [25:24] */
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u64 __pad1 : 38; /* [63:26] */
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};
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struct {
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/* env_c: */
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u64 rr_idr : 1; /* [ 0] */
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u64 rr_clkr : 1; /* [ 1] */
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u64 rr_sclkr : 1; /* [ 2] */
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u64 rr_dbg : 1; /* [ 3] */
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u64 rw_core_mode : 1; /* [ 4] */
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u64 rw_clkr : 1; /* [ 5] */
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u64 rw_sclkr : 1; /* [ 6] */
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u64 rw_sclkm3 : 1; /* [ 7] */
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u64 rw_dbg : 1; /* [ 8] */
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u64 hcem : 1; /* [ 9] */
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u64 virt : 1; /* [10] */
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u64 stop : 1; /* [11] */
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u64 evn_c_res : 4; /* [15:12] */
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/* exc_c: */
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u64 exc_instr_debug : 1; /* [16] */
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u64 exc_data_debug : 1; /* [17] */
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u64 exc_instr_page : 1; /* [18] */
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u64 exc_data_page : 1; /* [19] */
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u64 exc_mova : 1; /* [20] */
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u64 exc_interrupt : 1; /* [21] */
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u64 exc_nm_interrupt : 1; /* [22] */
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u64 exc_c_res : 1; /* [23] */
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/* glnch: */
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u64 g_th : 1; /* [24] */
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u64 tir_fz : 1; /* [25] */
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u64 tir_rst : 1; /* [26] */
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u64 __resb : 37; /* [63:27] */
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};
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u64 word; /* as entire register */
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} virt_ctrl_cu_t;
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#define VIRT_CTRL_CU_evn_c evn_c /* events mask to intercept */
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#define VIRT_CTRL_CU_rr_idr rr_idr
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#define VIRT_CTRL_CU_rr_clkr rr_clkr
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#define VIRT_CTRL_CU_rr_sclkr rr_sclkr
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#define VIRT_CTRL_CU_rr_dbg rr_dbg
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#define VIRT_CTRL_CU_rw_core_mode rw_core_mode
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#define VIRT_CTRL_CU_rw_clkr rw_clkr
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#define VIRT_CTRL_CU_rw_sclkr rw_sclkr
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#define VIRT_CTRL_CU_rw_sclkm3 rw_sclkm3
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#define VIRT_CTRL_CU_rw_dbg rw_dbg
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#define VIRT_CTRL_CU_hcem hcem
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#define VIRT_CTRL_CU_virt virt
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#define VIRT_CTRL_CU_stop stop
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#define VIRT_CTRL_CU_exc_c exc_c /* exceptions mask */
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/* to intercept */
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#define VIRT_CTRL_CU_exc_instr_debug exc_instr_debug
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#define VIRT_CTRL_CU_exc_data_debug exc_data_debug
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#define VIRT_CTRL_CU_exc_instr_page exc_instr_page
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#define VIRT_CTRL_CU_exc_data_page exc_data_page
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#define VIRT_CTRL_CU_exc_mova exc_mova
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#define VIRT_CTRL_CU_exc_interrupt exc_interrupt
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#define VIRT_CTRL_CU_exc_nm_interrupt exc_nm_interrupt
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#define VIRT_CTRL_CU_glnch glnch /* modes of guest launch */
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/* instruction execution */
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#define VIRT_CTRL_CU_glnch_g_th g_th
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#define VIRT_CTRL_CU_glnch_tir_fz tir_fz
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#define VIRT_CTRL_CU_tir_rst tir_rst /* mode of TIR registers */
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/* restore */
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#define VIRT_CTRL_CU_reg word /* [63: 0] - entire register */
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#endif /* ! __ASSEMBLY__ */
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#define INTC_CU_COND_EVENT_NO 0
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#define INTC_CU_COND_EVENT_MAX 16
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#define INTC_CU_COND_EXC_NO (INTC_CU_COND_EVENT_NO + \
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INTC_CU_COND_EVENT_MAX)
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#define INTC_CU_COND_EXC_MAX 8
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#define INTC_CU_UNCOND_EVENT_NO (INTC_CU_COND_EXC_NO + \
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INTC_CU_COND_EXC_MAX)
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#define INTC_CU_UNCOND_EVENT_MAX 8
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#define INTC_CU_EVENTS_NUM_MAX (INTC_CU_COND_EVENT_MAX + \
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INTC_CU_COND_EXC_MAX + \
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INTC_CU_UNCOND_EVENT_MAX)
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typedef union {
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struct {
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u64 evn_c : INTC_CU_COND_EVENT_MAX;
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u64 exc_c : INTC_CU_COND_EXC_MAX;
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u64 evn_u : INTC_CU_UNCOND_EVENT_MAX;
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u64 hi_half : 32;
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};
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struct {
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/* evn_c fields */
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u64 rr_idr : 1;
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u64 rr_clkr : 1;
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u64 rr_sclkr : 1;
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u64 rr_dbg : 1;
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u64 rw_core_mode : 1;
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u64 rw_clkr : 1;
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u64 rw_sclkr : 1;
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u64 rw_sclkm3 : 1;
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u64 rw_dbg : 1;
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u64 hcem : 1;
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u64 virt : 1;
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u64 stop : 1;
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u64 hret_last_wish : 1;
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u64 __reserved_evn_c : 3;
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/* exc_c fields */
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u64 exc_instr_debug : 1;
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u64 exc_data_debug : 1;
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u64 exc_instr_page : 1;
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u64 exc_data_page : 1;
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u64 exc_mova : 1;
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u64 exc_interrupt : 1;
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u64 exc_nm_interrupt : 1;
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u64 __reserved_exc_c : 1;
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/* evn_u fields */
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u64 hv_int : 1;
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u64 hv_nm_int : 1;
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u64 g_tmr : 1;
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u64 rr : 1;
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u64 rw : 1;
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u64 exc_mem_error : 1;
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u64 wait_trap : 1;
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u64 dbg : 1;
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/* high half of hdr_lo */
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u64 tir_fz : 1;
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u64 __reserved : 31;
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};
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u64 word;
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} intc_info_cu_hdr_lo_t;
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/* evn_c fields bit # */
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#define INTC_CU_RR_IDR_NO 0
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#define INTC_CU_RR_CLKR_NO 1
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#define INTC_CU_RR_SCLKR_NO 2
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#define INTC_CU_RR_DBG_NO 3
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#define INTC_CU_RW_CORE_MODE_NO 4
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#define INTC_CU_RW_CLKR_NO 5
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#define INTC_CU_RW_SCLKR_NO 6
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#define INTC_CU_RW_SCLKM3_NO 7
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#define INTC_CU_RW_DBG_NO 8
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#define INTC_CU_HCEM_NO 9
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#define INTC_CU_VIRT_NO 10
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#define INTC_CU_STOP_NO 11
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#define INTC_CU_HRET_LAST_WISH_NO 12
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/* INTC_INFO_CU.evn_c fields mask */
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#define intc_cu_evn_c_rr_idr_mask (1UL << INTC_CU_RR_IDR_NO)
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#define intc_cu_evn_c_rr_clkr_mask (1UL << INTC_CU_RR_CLKR_NO)
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#define intc_cu_evn_c_rr_sclkr_mask (1UL << INTC_CU_RR_SCLKR_NO)
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#define intc_cu_evn_c_rr_dbg_mask (1UL << INTC_CU_RR_DBG_NO)
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#define intc_cu_evn_c_rw_core_mode_mask (1UL << INTC_CU_RW_CORE_MODE_NO)
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#define intc_cu_evn_c_rw_clkr_mask (1UL << INTC_CU_RW_CLKR_NO)
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#define intc_cu_evn_c_rw_sclkr_mask (1UL << INTC_CU_RW_SCLKR_NO)
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#define intc_cu_evn_c_rw_sclkm3_mask (1UL << INTC_CU_RW_SCLKM3_NO)
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#define intc_cu_evn_c_rw_dbg_mask (1UL << INTC_CU_RW_DBG_NO)
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#define intc_cu_evn_c_hcem_mask (1UL << INTC_CU_HCEM_NO)
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#define intc_cu_evn_c_virt_mask (1UL << INTC_CU_VIRT_NO)
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#define intc_cu_evn_c_stop_mask (1UL << INTC_CU_STOP_NO)
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#define intc_cu_evn_c_hret_last_wish_mask (1UL << INTC_CU_HRET_LAST_WISH_NO)
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/* common mask of all 'read registers' interceptions */
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#define intc_cu_evn_c_rr_mask (intc_cu_evn_c_rr_idr_mask | \
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intc_cu_evn_c_rr_clkr_mask | \
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intc_cu_evn_c_rr_sclkr_mask | \
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intc_cu_evn_c_rr_dbg_mask)
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/* common mask of all 'write registers' interceptions */
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#define intc_cu_evn_c_rw_mask (intc_cu_evn_c_rw_core_mode_mask | \
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intc_cu_evn_c_rw_clkr_mask | \
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intc_cu_evn_c_rw_sclkr_mask | \
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intc_cu_evn_c_rw_sclkm3_mask | \
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intc_cu_evn_c_rw_dbg_mask)
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/* INTC_INFO_CU.hdr.evn_c fields mask */
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#define intc_cu_hdr_lo_rr_idr_mask \
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(intc_cu_evn_c_rr_idr_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_rr_clkr_mask \
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(intc_cu_evn_c_rr_clkr_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_rr_sclkr_mask \
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(intc_cu_evn_c_rr_sclkr_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_rr_dbg_mask \
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(intc_cu_evn_c_rr_dbg_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_rw_core_mode_mask \
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(intc_cu_evn_c_rw_core_mode_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_rw_clkr_mask \
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(intc_cu_evn_c_rw_clkr_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_rw_sclkr_mask \
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(intc_cu_evn_c_rw_sclkr_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_rw_sclkm3_mask \
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(intc_cu_evn_c_rw_sclkm3_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_rw_dbg_mask \
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(intc_cu_evn_c_rw_dbg_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_hcem_mask \
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(intc_cu_evn_c_hcem_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_virt_mask \
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(intc_cu_evn_c_virt_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_stop_mask \
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(intc_cu_evn_c_stop_mask << INTC_CU_COND_EVENT_NO)
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#define intc_cu_hdr_lo_hret_last_wish_mask \
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(intc_cu_evn_c_hret_last_wish_mask << INTC_CU_COND_EVENT_NO)
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/* common mask of all 'read registers' interceptions */
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#define intc_cu_hrd_lo_rr_mask (intc_cu_hdr_lo_rr_idr_mask | \
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intc_cu_hdr_lo_rr_clkr_mask | \
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intc_cu_hdr_lo_rr_sclkr_mask | \
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intc_cu_hdr_lo_rr_dbg_mask)
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/* common mask of all 'write registers' interceptions */
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#define intc_cu_hrd_lo_rw_mask (intc_cu_hdr_lo_rw_core_mode_mask | \
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intc_cu_hdr_lo_rw_clkr_mask | \
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intc_cu_hdr_lo_rw_sclkr_mask | \
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intc_cu_hdr_lo_rw_sclkm3_mask | \
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intc_cu_hdr_lo_rw_dbg_mask)
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/* exc_c fields bit # */
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#define INTC_CU_EXC_INSTR_DEBUG_NO 0
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#define INTC_CU_EXC_DATA_DEBUG_NO 1
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#define INTC_CU_EXC_INSTR_PAGE_NO 2
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#define INTC_CU_EXC_DATA_PAGE_NO 3
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#define INTC_CU_EXC_MOVA_NO 4
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#define INTC_CU_EXC_INTERRUPT_NO 5
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#define INTC_CU_EXC_NM_INTERRUPT_NO 6
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/* exc_c fields mask */
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#define intc_cu_exc_c_exc_instr_debug_mask \
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(1UL << INTC_CU_EXC_INSTR_DEBUG_NO)
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#define intc_cu_exc_c_exc_data_debug_mask \
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(1UL << INTC_CU_EXC_DATA_DEBUG_NO)
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#define intc_cu_exc_c_exc_instr_page_mask \
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(1UL << INTC_CU_EXC_INSTR_PAGE_NO)
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#define intc_cu_exc_c_exc_data_page_mask \
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(1UL << INTC_CU_EXC_DATA_PAGE_NO)
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#define intc_cu_exc_c_exc_mova_mask \
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(1UL << INTC_CU_EXC_MOVA_NO)
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#define intc_cu_exc_c_exc_interrupt_mask \
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(1UL << INTC_CU_EXC_INTERRUPT_NO)
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#define intc_cu_exc_c_exc_nm_interrupt_mask \
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(1UL << INTC_CU_EXC_NM_INTERRUPT_NO)
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/* INTC_INFO_CU.exc_c fields mask */
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#define intc_cu_hdr_lo_exc_instr_debug_mask \
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(intc_cu_exc_c_exc_instr_debug_mask << INTC_CU_COND_EXC_NO)
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#define intc_cu_hdr_lo_exc_data_debug_mask \
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(intc_cu_exc_c_exc_data_debug_mask << INTC_CU_COND_EXC_NO)
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#define intc_cu_hdr_lo_exc_instr_page_mask \
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(intc_cu_exc_c_exc_instr_page_mask << INTC_CU_COND_EXC_NO)
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#define intc_cu_hdr_lo_exc_data_page_mask \
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(intc_cu_exc_c_exc_data_page_mask << INTC_CU_COND_EXC_NO)
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#define intc_cu_hdr_lo_exc_mova_mask \
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(intc_cu_exc_c_exc_mova_mask << INTC_CU_COND_EXC_NO)
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#define intc_cu_hdr_lo_exc_interrupt_mask \
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(intc_cu_exc_c_exc_interrupt_mask << INTC_CU_COND_EXC_NO)
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#define intc_cu_hdr_lo_exc_nm_interrupt_mask \
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(intc_cu_exc_c_exc_nm_interrupt_mask << INTC_CU_COND_EXC_NO)
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/* evn_u fields bit # */
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#define INTC_CU_HV_INT_NO 0
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#define INTC_CU_HV_NM_INT_NO 1
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#define INTC_CU_G_TMR_NO 2
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#define INTC_CU_RR_NO 3
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#define INTC_CU_RW_NO 4
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#define INTC_CU_EXC_MEM_ERROR_NO 5
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#define INTC_CU_WAIT_TRAP_NO 6
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#define INTC_CU_DBG_NO 7
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/* evn_u fields mask */
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#define intc_cu_evn_u_hv_int_mask (1UL << INTC_CU_HV_INT_NO)
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#define intc_cu_evn_u_hv_nm_int_mask (1UL << INTC_CU_HV_NM_INT_NO)
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#define intc_cu_evn_u_g_tmr_mask (1UL << INTC_CU_G_TMR_NO)
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#define intc_cu_evn_u_rr_mask (1UL << INTC_CU_RR_NO)
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#define intc_cu_evn_u_rw_mask (1UL << INTC_CU_RW_NO)
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#define intc_cu_evn_u_exc_mem_error_mask \
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(1UL << INTC_CU_EXC_MEM_ERROR_NO)
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#define intc_cu_evn_u_wait_trap_mask (1UL << INTC_CU_WAIT_TRAP_NO)
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#define intc_cu_evn_u_dbg_mask (1UL << INTC_CU_DBG_NO)
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/* INT_INFO_CU.evn_u fields mask */
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#define intc_cu_hdr_lo_hv_int_mask \
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(intc_cu_evn_u_hv_int_mask << INTC_CU_UNCOND_EVENT_NO)
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#define intc_cu_hdr_lo_hv_nm_int_mask \
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(intc_cu_evn_u_hv_nm_int_mask << INTC_CU_UNCOND_EVENT_NO)
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#define intc_cu_hdr_lo_g_tmr_mask \
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(intc_cu_evn_u_g_tmr_mask << INTC_CU_UNCOND_EVENT_NO)
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#define intc_cu_hdr_lo_rr_mask \
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(intc_cu_evn_u_rr_mask << INTC_CU_UNCOND_EVENT_NO)
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#define intc_cu_hdr_lo_rw_mask \
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(intc_cu_evn_u_rw_mask << INTC_CU_UNCOND_EVENT_NO)
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#define intc_cu_hdr_lo_exc_mem_error_mask \
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(intc_cu_evn_u_exc_mem_error_mask << INTC_CU_UNCOND_EVENT_NO)
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#define intc_cu_hdr_lo_wait_trap_mask \
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(intc_cu_evn_u_wait_trap_mask << INTC_CU_UNCOND_EVENT_NO)
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#define intc_cu_hdr_lo_dbg_mask \
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(intc_cu_evn_u_dbg_mask << INTC_CU_UNCOND_EVENT_NO)
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#if (1UL << INTC_CU_EVENTS_NUM_MAX) < intc_cu_hdr_lo_dbg_mask
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#error "INTC_CU_EVENTS_NUM_MAX value is out of real events number"
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#endif
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#define INTC_CU_TIR_FZ_NO 32
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#define intc_cu_hdr_lo_tir_fz_mask (1UL << INTC_CU_TIR_FZ_NO)
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typedef union {
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u64 word;
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} intc_info_cu_hdr_hi_t;
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typedef struct e2k_intc_info_cu_hdr {
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intc_info_cu_hdr_lo_t lo;
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intc_info_cu_hdr_hi_t hi;
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} intc_info_cu_hdr_t;
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typedef union {
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struct {
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u64 event_code : 8;
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u64 ch_code : 4;
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u64 reg_num : 8;
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u64 dst : 8;
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u64 vm_dst : 3;
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u64 __reserved : 33;
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};
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u64 word;
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} intc_info_cu_entry_lo_t;
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#define intc_cu_info_lo_get_event_code(x) ((x) & 0xff)
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/* Possible values for `INTC_INFO_CU[2 * j].event_code' */
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typedef enum info_cu_event_code {
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ICE_FORCED = 0,
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ICE_READ_CU = 1,
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ICE_WRITE_CU = 2,
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ICE_MASKED_HCALL = 3,
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ICE_GLAUNCH = 4,
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ICE_HRET = 5,
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} info_cu_event_code_t;
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typedef u64 intc_info_cu_entry_hi_t;
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typedef struct e2k_intc_info_cu_entry {
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intc_info_cu_entry_lo_t lo;
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intc_info_cu_entry_hi_t hi;
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bool no_restore;
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} intc_info_cu_entry_t;
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#define INTC_INFO_CU_MAX 6
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#define INTC_INFO_CU_HDR_MAX 2
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#define INTC_INFO_CU_ENTRY_MAX (INTC_INFO_CU_MAX - INTC_INFO_CU_HDR_MAX)
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#define INTC_INFO_CU_PAIRS_MAX (INTC_INFO_CU_ENTRY_MAX / 2)
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typedef struct {
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intc_info_cu_hdr_t header;
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intc_info_cu_entry_t entry[INTC_INFO_CU_PAIRS_MAX];
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} intc_info_cu_t;
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typedef union {
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struct {
|
|
u64 tmr : 32;
|
|
u64 v : 1;
|
|
u64 __reserved : 31;
|
|
};
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|
u64 word;
|
|
} g_preempt_tmr_t;
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#endif /* __KERNEL__ */
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#endif /* _E2K_KVM_CPU_HV_REGS_TYPES_H_ */
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