194 lines
5.9 KiB
C
194 lines
5.9 KiB
C
/*
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* asm-e2k/mmu_regs.h: E2K MMU structures & registers.
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*
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* Copyright 2001 Salavat S. Guiliazov (atic@mcst.ru)
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*/
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#ifndef _E2K_KVM_MMU_HV_REGS_TYPES_H_
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#define _E2K_KVM_MMU_HV_REGS_TYPES_H_
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#include <linux/types.h>
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#include <asm/mmu_regs_types.h>
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/*
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* Structures of MMU registers for hardware virtualized extensions
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*/
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/* MMU address to access to MMU internal registers */
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#define _MMU_VIRT_CTRL_NO 0x40 /* MMU virtualization control */
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#define _MMU_GID_NO 0x41 /* guest machine ID */
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#define _MMU_GP_PPTB_NO 0x43 /* physical base of guest PTs */
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#define _MMU_INTC_INFO_NO 0x44 /* MMU intercept info */
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#define _MMU_INTC_PTR_NO 0x45 /* MMU intercept info pointer */
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#define _MMU_SH_OS_VPTB_NO 0x46 /* virtual base of guest shadow PTs */
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#define _MMU_SH_OS_PPTB_NO 0x47 /* physical base of guest shadow PTs */
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#define _MMU_CR_G_W_IMASK_NO 0x48 /* mask of MMU_CR bits access to */
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/* control intercepts */
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#define _MMU_SH_PID_NO 0x49 /* shadow register of process ID */
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#define _MMU_SH_MMU_CR_NO 0x4a /* shadow register of control reg. */
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#define MMU_ADDR_VIRT_CTRL MMU_REG_NO_TO_MMU_ADDR(_MMU_VIRT_CTRL_NO)
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#define MMU_ADDR_GID MMU_REG_NO_TO_MMU_ADDR(_MMU_GID_NO)
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#define MMU_ADDR_GP_PPTB MMU_REG_NO_TO_MMU_ADDR(_MMU_GP_PPTB_NO)
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#define MMU_ADDR_INTC_INFO MMU_REG_NO_TO_MMU_ADDR(_MMU_INTC_INFO_NO)
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#define MMU_ADDR_INTC_PTR MMU_REG_NO_TO_MMU_ADDR(_MMU_INTC_PTR_NO)
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#define MMU_ADDR_SH_OS_VPTB MMU_REG_NO_TO_MMU_ADDR(_MMU_SH_OS_VPTB_NO)
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#define MMU_ADDR_SH_OS_PPTB MMU_REG_NO_TO_MMU_ADDR(_MMU_SH_OS_PPTB_NO)
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#define MMU_ADDR_CR_G_W_IMASK MMU_REG_NO_TO_MMU_ADDR(_MMU_CR_G_W_IMASK_NO)
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#define MMU_ADDR_SH_PID MMU_REG_NO_TO_MMU_ADDR(_MMU_SH_PID_NO)
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#define MMU_ADDR_SH_MMU_CR MMU_REG_NO_TO_MMU_ADDR(_MMU_SH_MMU_CR_NO)
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/* MMU internel register contents */
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/*
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* MMU Guest Process (machine #) ID MMU_GID
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*/
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#define MMU_GID_SIZE MMU_PID_SIZE
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/*
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* Kernel virtual memory context
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*/
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#define E2K_KERNEL_GID 0x000 /* defined by hardware */
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#define MMU_GID(gid) MMU_PID(gid)
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#define MMU_KERNEL_GID MMU_GID(E2K_KERNEL_GID)
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/*
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* MMU Virtual Control register
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*/
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typedef union virt_ctrl_mu {
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struct {
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u64 evn_c : 36; /* [35: 0] */
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u64 __resf : 28; /* [63:38] */
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};
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struct {
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/* env_c: */
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u64 rr_mmu_cr : 1; /* [ 0] */
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u64 rr_pptb : 1; /* [ 1] */
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u64 rr_vptb : 1; /* [ 2] */
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u64 rr_apic_base : 1; /* [ 3] */
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u64 rr_mtrr_pat : 1; /* [ 4] */
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u64 rr_ph_pci_b : 1; /* [ 5] */
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u64 rr_dbg : 1; /* [ 6] */
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u64 rr_dbg1 : 1; /* [ 7] */
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u64 rw_mmu_cr : 1; /* [ 8] */
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u64 rw_pptb : 1; /* [ 9] */
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u64 rw_vptb : 1; /* [10] */
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u64 rw_apic_base : 1; /* [11] */
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u64 rw_mtrr_pat : 1; /* [12] */
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u64 rw_ph_pci_b : 1; /* [13] */
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u64 rw_dbg : 1; /* [14] */
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u64 rw_dbg1 : 1; /* [15] */
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u64 pma : 1; /* [16] */
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u64 fl_dc : 1; /* [17] */
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u64 fl_dcl : 1; /* [18] */
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u64 fl_ic : 1; /* [19] */
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u64 fl_icl_u : 1; /* [20] */
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u64 fl_icl_p : 1; /* [21] */
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u64 fl_tlb : 1; /* [22] */
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u64 fl_tlbpg : 1; /* [23] */
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u64 fl_tlb2pg : 1; /* [24] */
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u64 prb_entry : 1; /* [25] */
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u64 evn_c_res : 10; /* [35:26] */
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/* other fields */
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u64 gp_pt_en : 1; /* [36] */
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u64 sh_pt_en : 1; /* [37] */
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u64 __resb : 26; /* [63:38] */
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};
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u64 word; /* as entire register */
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} virt_ctrl_mu_t;
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#define VIRT_CTRL_MU_evn_c evn_c /* events mask to intercept */
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#define VIRT_CTRL_MU_rr_mmu_cr rr_mmu_cr
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#define VIRT_CTRL_MU_rr_u_pptb rr_pptb
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#define VIRT_CTRL_MU_rr_u_vptb rr_vptb
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#define VIRT_CTRL_MU_rr_apic_base rr_apic_base
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#define VIRT_CTRL_MU_rr_mtrr_pat rr_mtrr_pat
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#define VIRT_CTRL_MU_rr_ph_pci_b rr_ph_pci_b
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#define VIRT_CTRL_MU_rr_dbg rr_dbg
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#define VIRT_CTRL_MU_rr_dbg1 rr_dbg1
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#define VIRT_CTRL_MU_rw_mmu_cr rw_mmu_cr
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#define VIRT_CTRL_MU_rw_u_pptb rw_pptb
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#define VIRT_CTRL_MU_rw_u_vptb rw_vptb
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#define VIRT_CTRL_MU_rw_apic_base rw_apic_base
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#define VIRT_CTRL_MU_rw_mtrr_pat rw_mtrr_pat
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#define VIRT_CTRL_MU_rw_ph_pci_b rw_ph_pci_b
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#define VIRT_CTRL_MU_rw_dbg rw_dbg
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#define VIRT_CTRL_MU_rw_dbg1 rw_dbg1
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#define VIRT_CTRL_MU_pma pma
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#define VIRT_CTRL_MU_fl_dc fl_dc
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#define VIRT_CTRL_MU_fl_dcl fl_dcl
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#define VIRT_CTRL_MU_fl_ic fl_ic
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#define VIRT_CTRL_MU_fl_icl_u fl_icl_u
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#define VIRT_CTRL_MU_fl_icl_p fl_icl_p
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#define VIRT_CTRL_MU_fl_tlb fl_tlb
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#define VIRT_CTRL_MU_fl_tlbpg fl_tlbpg
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#define VIRT_CTRL_MU_fl_tlb2pg fl_tlb2pg
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#define VIRT_CTRL_MU_prb_entry prb_entry
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/* GPA -> PA translation enable */
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#define VIRT_CTRL_MU_gp_pt_en gp_pt_en
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/* shadow Page Tables enable */
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#define VIRT_CTRL_MU_sh_pt_en sh_pt_en
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#define VIRT_CTRL_MU_reg word /* [63: 0] - entire register */
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typedef union {
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struct {
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u64 event_code : 8;
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u64 guest_pt_lev_fin : 1;
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u64 guest_pt_lev : 3;
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u64 ignore_wr_rights : 1;
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u64 __reserved : 51;
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};
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u64 word;
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} intc_info_mu_hdr_t;
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#define intc_mu_info_lo_get_event_code(x) ((x) & 0xff)
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/* Possible values for `INTC_INFO_MU[2 * j].event_code' */
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typedef enum e2k_int_info_mu_event_code {
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IME_FORCED = 0,
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IME_FORCED_GVA = 1,
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IME_SHADOW_DATA = 2,
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IME_GPA_DATA = 3,
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IME_GPA_INSTR = 4,
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IME_GPA_AINSTR = 5,
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IME_RESERVED_6 = 6,
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IME_RESERVED_7 = 7,
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IME_MAS_IOADDR = 8,
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IME_READ_MU = 9,
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IME_WRITE_MU = 10,
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IME_CACHE_FLUSH = 11,
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IME_CACHE_LINE_FLUSH = 12,
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IME_ICACHE_FLUSH = 13,
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IME_ICACHE_LINE_FLUSH_USER = 14,
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IME_ICACHE_LINE_FLUSH_SYSTEM = 15,
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IME_TLB_FLUSH = 16,
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IME_TLB_PAGE_FLUSH_LAST = 17,
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IME_TLB_PAGE_FLUSH_UPPER = 18,
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IME_TLB_ENTRY_PROBE = 19,
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MU_INTC_EVENTS_MAX
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} intc_info_mu_event_code_t;
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typedef struct {
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intc_info_mu_hdr_t hdr;
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unsigned long gpa;
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unsigned long gva;
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unsigned long data;
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tc_cond_t condition;
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unsigned long data_ext;
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tc_mask_t mask;
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bool no_restore;
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bool modify_data;
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unsigned long mod_data;
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unsigned long mod_data_ext;
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} intc_info_mu_t;
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#define INTC_INFO_MU_MAX 77
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#define INTC_PTR_MU_SIZE 7
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#define INTC_INFO_MU_ITEM_SIZE 7
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#define INTC_INFO_MU_ITEM_MAX (INTC_INFO_MU_MAX / INTC_INFO_MU_ITEM_SIZE)
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#endif /* _E2K_KVM_MMU_HV_REGS_TYPES_H_ */
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