151 lines
3.2 KiB
C
151 lines
3.2 KiB
C
#ifndef __ASM_E2K_PIC_H
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#define __ASM_E2K_PIC_H
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/*
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* Choose between APIC and EPIC basic functions
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*/
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#include <asm/apic.h>
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#include <asm/epic.h>
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#include <asm/machdep.h>
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/* P2V */
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static inline unsigned int boot_epic_is_bsp(void)
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{
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union cepic_ctrl reg;
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reg.raw = boot_epic_read_w(CEPIC_CTRL);
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return reg.bits.bsp_core;
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}
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static inline unsigned int boot_apic_is_bsp(void)
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{
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return BootStrap(boot_arch_apic_read(APIC_BSP));
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}
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static inline unsigned int boot_epic_read_id(void)
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{
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return cepic_id_full_to_short(boot_epic_read_w(CEPIC_ID));
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}
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static inline unsigned int boot_apic_read_id(void)
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{
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return GET_APIC_ID(boot_arch_apic_read(APIC_ID));
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}
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/*
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* Reading PIC registers is mainly done in early P2V: before and slightly
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* after the initialization of boot_machine structure. Unfortunately, the
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* structure is initalized by BSP, and AP may proceed to read PIC in the mean
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* time. The barrier can't be used that early either. As such, PIC reads in P2V
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* can't rely on CPU_FEAT_EPIC. We manually read the IDR register instead.
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*/
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#ifdef CONFIG_EPIC
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static inline bool boot_early_pic_is_bsp(void)
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{
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e2k_idr_t idr;
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unsigned int reg;
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idr = boot_read_IDR_reg();
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if (idr.IDR_mdl >= IDR_E12C_MDL)
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reg = boot_epic_is_bsp();
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else
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reg = boot_apic_is_bsp();
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return !!reg;
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}
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static inline unsigned int boot_early_pic_read_id(void)
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{
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e2k_idr_t idr;
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idr = boot_read_IDR_reg();
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if (idr.IDR_mdl >= IDR_E12C_MDL)
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return boot_epic_read_id();
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else
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return boot_apic_read_id();
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}
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#else
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static inline bool boot_early_pic_is_bsp(void)
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{
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return !!boot_apic_is_bsp();
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}
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static inline unsigned int boot_early_pic_read_id(void)
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{
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return boot_apic_read_id();
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}
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#endif
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/* Kernel */
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#ifndef E2K_P2V
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#include <asm-l/pic.h>
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#ifdef CONFIG_EPIC
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static inline bool read_pic_bsp(void)
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{
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if (cpu_has_epic())
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return read_epic_bsp();
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else
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return !!BootStrap(arch_apic_read(APIC_BSP));
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}
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extern void __init_recv e2k_setup_secondary_apic(void);
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static inline void __init_recv e2k_setup_secondary_pic(void)
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{
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if (cpu_has_epic())
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setup_cepic();
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else
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e2k_setup_secondary_apic();
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}
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extern void __init_recv setup_prepic(void);
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static inline void __init_recv setup_processor_pic(void)
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{
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if (cpu_has_epic())
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setup_prepic();
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}
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#else /* CONFIG_EPIC */
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static inline bool read_pic_bsp(void)
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{
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return !!BootStrap(arch_apic_read(APIC_BSP));
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}
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extern void __init_recv e2k_setup_secondary_apic(void);
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static inline void __init_recv e2k_setup_secondary_pic(void)
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{
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e2k_setup_secondary_apic();
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}
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extern void __init_recv e2k_apic_map_logical_id(int recovery);
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static inline void __init_recv e2k_pic_map_logical_id(int recovery)
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{
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e2k_apic_map_logical_id(recovery);
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}
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static inline void __init_recv setup_processor_pic(void)
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{
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/* Nothing to do */
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}
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extern void setup_secondary_APIC_clock(void);
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static inline void __init_recv setup_secondary_pic_clock(void)
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{
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setup_secondary_APIC_clock();
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}
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static inline int pic_get_vector(void)
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{
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return apic_get_vector();
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}
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struct pci_dev;
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int ioepic_pin_to_msi_ioapic_irq(unsigned int pin, struct pci_dev *dev);
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static inline int ioepic_pin_to_irq_pic(unsigned int pin, struct pci_dev *dev)
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{
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return ioepic_pin_to_msi_ioapic_irq(pin, dev);
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}
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#endif /* CONFIG_EPIC */
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#endif /* E2K_P2V */
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#endif /* __ASM_E2K_PIC_H */
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