58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
#pragma once
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#include <asm/sic_regs_access.h>
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#include <asm/p2v/boot_smp.h>
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static __always_inline void boot_wait_for_flush_v5_L3(unsigned char *node_nbsr)
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{
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l3_ctrl_t l3_ctrl;
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/* waiting for flush completion */
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do {
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boot_cpu_relax();
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l3_ctrl.E2K_L3_CTRL_reg =
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boot_do_sic_read_node_nbsr_reg(node_nbsr, SIC_l3_ctrl);
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} while (l3_ctrl.E2K_L3_CTRL_fl != 0);
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}
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static __always_inline void boot_wait_for_flush_v4_L3(unsigned char *node_nbsr)
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{
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l3_reg_t l3_diag;
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/* waiting for flush completion */
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l3_diag = boot_do_sic_read_node_nbsr_reg(node_nbsr, SIC_l3_b0_diag_dw);
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l3_diag = boot_do_sic_read_node_nbsr_reg(node_nbsr, SIC_l3_b1_diag_dw);
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l3_diag = boot_do_sic_read_node_nbsr_reg(node_nbsr, SIC_l3_b2_diag_dw);
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l3_diag = boot_do_sic_read_node_nbsr_reg(node_nbsr, SIC_l3_b3_diag_dw);
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l3_diag = boot_do_sic_read_node_nbsr_reg(node_nbsr, SIC_l3_b4_diag_dw);
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l3_diag = boot_do_sic_read_node_nbsr_reg(node_nbsr, SIC_l3_b5_diag_dw);
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l3_diag = boot_do_sic_read_node_nbsr_reg(node_nbsr, SIC_l3_b6_diag_dw);
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l3_diag = boot_do_sic_read_node_nbsr_reg(node_nbsr, SIC_l3_b7_diag_dw);
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__E2K_WAIT_ALL;
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}
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static __always_inline void boot_native_flush_L3(int iset_ver,
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unsigned char *node_nbsr)
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{
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l3_ctrl_t l3_ctrl;
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if (iset_ver < E2K_ISET_V4)
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/* cache L3 is absent */
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return;
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/* set bit of L3 control register to flash L3 */
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l3_ctrl.E2K_L3_CTRL_reg =
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boot_do_sic_read_node_nbsr_reg(node_nbsr, SIC_l3_ctrl);
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l3_ctrl.E2K_L3_CTRL_fl = 1;
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boot_do_sic_write_node_nbsr_reg(node_nbsr, SIC_l3_ctrl,
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l3_ctrl.E2K_L3_CTRL_reg);
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/* waiting for flush completion */
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if (iset_ver > E2K_ISET_V4)
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boot_wait_for_flush_v5_L3(node_nbsr);
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else
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boot_wait_for_flush_v4_L3(node_nbsr);
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}
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