638 lines
18 KiB
C
638 lines
18 KiB
C
#ifndef __L_ASM_MPSPEC_H
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#define __L_ASM_MPSPEC_H
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/*
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* Structure definitions for SMP machines following the
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* Intel Multiprocessing Specification 1.1 and 1.4.
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*/
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#ifndef __ASSEMBLY__
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#include <linux/init.h>
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#include <linux/cpumask.h>
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#include <asm/bootinfo.h>
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#include <asm/apicdef.h>
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#ifdef CONFIG_E2K
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#include <asm/e2k.h>
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#endif
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/*
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* This tag identifies where the SMP configuration
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* information is.
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*/
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#ifdef __LITTLE_ENDIAN
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#define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
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#elif __BIG_ENDIAN
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#define SMP_MAGIC_IDENT ('_'|('P'<<8)|('M'<<16)|('_'<<24))
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#else
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#error not byte order defined
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#endif /*__BIG_ENDIAN*/
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/*
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* a maximum of NR_CPUS APICs with the current APIC ID architecture.
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* a maximum of IO-APICs is summary:
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* each IO link can have IOHUB with IO-APIC
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* each node can have embeded IO-APIC
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*/
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#define MAX_LOCAL_APICS (NR_CPUS * 2) /* apic numbering can be with holes */
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#define MAX_IO_APICS (MAX_NUMIOLINKS + MAX_NUMNODES)
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#define MAX_APICS MAX_LOCAL_APICS
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#define SMP_FLOATING_TABLE_LEN sizeof(struct intel_mp_floating)
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struct intel_mp_floating
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{
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char mpf_signature[4]; /* "_MP_" */
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unsigned long mpf_physptr; /* Configuration table address */
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unsigned char mpf_length; /* Our length (paragraphs) */
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unsigned char mpf_specification;/* Specification version */
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unsigned char mpf_checksum; /* Checksum (makes sum 0) */
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unsigned char mpf_feature1; /* Standard or configuration ? */
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unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
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unsigned char mpf_feature3; /* Unused (0) */
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unsigned char mpf_feature4; /* Unused (0) */
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unsigned char mpf_feature5; /* Unused (0) */
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};
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#define MPF_64_BIT_SPECIFICATION 8 /* MPF specification describe */
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/* new MP table compatible */
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/* with 64-bits arch */
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#define MP_SPEC_ADDR_ALIGN 4 /* addresses can be */
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/* word-aligned */
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#define MP_NEW_ADDR_ALIGN 8 /* all addresses should be */
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/* double-word aligned */
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#define ALIGN_BYTES_DOWN(addr, bytes) (((addr) / (bytes)) * (bytes))
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#define ALIGN_BYTES_UP(addr, bytes) ((((addr) + (bytes)-1) / (bytes)) * \
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(bytes))
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#define MP_ALIGN_BYTES(addr, bytes) ALIGN_BYTES_UP(addr, bytes)
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#define IS_64_BIT_MP_SPECS() \
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(boot_mpf_found->mpf_specification == MPF_64_BIT_SPECIFICATION)
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#define MP_ADDR_ALIGN(addr) \
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(unsigned char *)(MP_ALIGN_BYTES((unsigned long long)(addr), \
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(IS_64_BIT_MP_SPECS()) ? MP_NEW_ADDR_ALIGN : \
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MP_SPEC_ADDR_ALIGN))
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#define MP_SIZE_ALIGN(addr) \
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MP_ALIGN_BYTES((unsigned long long)(addr), \
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(IS_64_BIT_MP_SPECS()) ? MP_NEW_ADDR_ALIGN : \
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MP_SPEC_ADDR_ALIGN)
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#define enable_update_mptable 0
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struct mpc_table
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{
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char mpc_signature[4];
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#define MPC_SIGNATURE "PCMP"
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unsigned short mpc_length; /* Size of table */
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char mpc_spec; /* 0x01 */
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char mpc_checksum;
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char mpc_oem[8];
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char mpc_productid[12];
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unsigned int mpc_oemptr; /* 0 if not present */
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unsigned short mpc_oemsize; /* 0 if not present */
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unsigned short mpc_oemcount;
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unsigned int mpc_lapic; /* APIC address */
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unsigned short mpe_length; /* Extended Table size */
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unsigned char mpe_checksum; /* Extended Table checksum */
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unsigned char reserved;
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};
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/* Followed by entries */
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#define MP_PROCESSOR 0
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#define MP_BUS 1
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#define MP_IOAPIC 2
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#define MP_INTSRC 3
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#define MP_LINTSRC 4
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#define MP_TIMER 5
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#define MP_I2C_SPI 6
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#define MP_IOLINK 7
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#define MP_PMC 8
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#define MP_BDEV 9
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#define MP_GPIO_ACT 10
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#define MP_IOEPIC 11
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struct mpc_config_processor
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{
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unsigned char mpc_type; /* MP_PROCESSOR */
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unsigned char mpc_apicid; /* Local APIC number */
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unsigned char mpc_apicver; /* Its versions */
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unsigned char mpc_cpuflag;
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#define CPU_ENABLED 1 /* Processor is available */
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#define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
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unsigned int mpc_cpufeature;
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#define CPU_STEPPING_MASK 0x0F
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#define CPU_MODEL_MASK 0xF0
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#define CPU_FAMILY_MASK 0xF00
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unsigned int mpc_featureflag; /* CPUID feature value */
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unsigned int mpc_cepictimerfreq; /* Frequency of CEPIC timer */
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unsigned int mpc_reserved;
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};
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struct mpc_config_bus
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{
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unsigned char mpc_type; /* MP_BUS */
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unsigned char mpc_busid;
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unsigned char mpc_bustype[6];
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};
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/* List of Bus Type string values, Intel MP Spec. */
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#define BUSTYPE_EISA "EISA"
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#define BUSTYPE_ISA "ISA"
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#define BUSTYPE_INTERN "INTERN" /* Internal BUS */
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#define BUSTYPE_MCA "MCA"
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#define BUSTYPE_VL "VL" /* Local bus */
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#define BUSTYPE_PCI "PCI"
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#define BUSTYPE_PCMCIA "PCMCIA"
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#define BUSTYPE_CBUS "CBUS"
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#define BUSTYPE_CBUSII "CBUSII"
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#define BUSTYPE_FUTURE "FUTURE"
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#define BUSTYPE_MBI "MBI"
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#define BUSTYPE_MBII "MBII"
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#define BUSTYPE_MPI "MPI"
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#define BUSTYPE_MPSA "MPSA"
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#define BUSTYPE_NUBUS "NUBUS"
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#define BUSTYPE_TC "TC"
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#define BUSTYPE_VME "VME"
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#define BUSTYPE_XPRESS "XPRESS"
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struct mpc_ioapic
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{
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unsigned char type; /* MP_IOAPIC */
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unsigned char apicid;
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unsigned char apicver;
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unsigned char flags;
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#define MPC_APIC_USABLE 0x01
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unsigned long apicaddr;
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};
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struct mpc_ioepic {
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unsigned char type; /* MP_IOEPIC */
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unsigned char epicver;
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unsigned short epicid;
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unsigned short nodeid;
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unsigned char reserved[2];
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unsigned long epicaddr;
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} __packed;
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#define MPC_IOIRQFLAG_PO_BS 0x0 /* Bus specific */
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#define MPC_IOIRQFLAG_PO_AH 0x1 /* Active high */
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#define MPC_IOIRQFLAG_PO_RES 0x2 /* Reserved */
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#define MPC_IOIRQFLAG_PO_AL 0x3 /* Active low */
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#define MPC_IOIRQFLAG_EL_BS 0x0 /* Bus specific */
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#define MPC_IOIRQFLAG_EL_FS 0x4 /* Trigger by front */
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#define MPC_IOIRQFLAG_EL_RES 0x8 /* Reserved */
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#define MPC_IOIRQFLAG_EL_LS 0xC /* Trigger by level */
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struct mpc_intsrc
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{
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unsigned char type; /* MP_INTSRC */
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unsigned char irqtype;
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unsigned short irqflag;
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unsigned char srcbus;
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unsigned char srcbusirq;
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unsigned char dstapic;
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unsigned char dstirq;
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};
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enum mp_irq_source_types {
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mp_INT = 0,
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mp_NMI = 1,
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mp_SMI = 2,
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mp_ExtINT = 3,
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mp_FixINT = 4 /* fixed interrupt pin for PCI */
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};
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#define MP_IRQDIR_DEFAULT 0
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#define MP_IRQDIR_HIGH 1
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#define MP_IRQDIR_LOW 3
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#ifdef CONFIG_BIOS
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#define MP_IRQ_POLARITY_DEFAULT 0x0
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#define MP_IRQ_POLARITY_HIGH 0x1
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#define MP_IRQ_POLARITY_LOW 0x3
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#define MP_IRQ_POLARITY_MASK 0x3
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#define MP_IRQ_TRIGGER_DEFAULT 0x0
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#define MP_IRQ_TRIGGER_EDGE 0x4
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#define MP_IRQ_TRIGGER_LEVEL 0xc
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#define MP_IRQ_TRIGGER_MASK 0xc
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#endif /* CONFIG_BIOS */
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struct mpc_config_lintsrc
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{
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unsigned char mpc_type; /* MP_LINTSRC */
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unsigned char mpc_irqtype;
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unsigned short mpc_irqflag;
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unsigned char mpc_srcbusid;
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unsigned char mpc_srcbusirq;
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unsigned char mpc_destapic;
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#define MP_APIC_ALL 0xFF
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unsigned char mpc_destapiclint;
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};
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/*
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* Default configurations
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*
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* 1 2 CPU ISA 82489DX
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* 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
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* 3 2 CPU EISA 82489DX
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* 4 2 CPU MCA 82489DX
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* 5 2 CPU ISA+PCI
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* 6 2 CPU EISA+PCI
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* 7 2 CPU MCA+PCI
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*/
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#define MAX_IRQ_SOURCES (128 * MAX_NUMIOHUBS)
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/* (32 * nodes) for PCI, and one number is a special case */
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#define MAX_MP_BUSSES 256
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enum mp_bustype {
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MP_BUS_ISA = 1,
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MP_BUS_EISA,
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MP_BUS_PCI,
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MP_BUS_MCA
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};
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/*
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* IO link configurations
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*/
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#define MAX_NUMIOLINKS MACH_MAX_NUMIOLINKS
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#define MAX_NUMIOHUBS MAX_NUMIOLINKS
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#define NODE_NUMIOLINKS MACH_NODE_NUMIOLINKS
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typedef struct mpc_config_iolink {
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unsigned char mpc_type; /* type is MP_IOLINK */
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unsigned char mpc_iolink_type; /* type of IO link: IOHUB or RDMA */
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unsigned short mpc_iolink_ver; /* version of IOHUB or RDMA */
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unsigned int mpc_reserved; /* reserved */
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int node; /* number od node: 0 - 3 */
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int link; /* local number of link on node: 0-1 */
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short bus_min; /* number of root bus on IOHUB */
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short bus_max; /* number of max bus on IOHUB */
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short apicid; /* IO-APIC id connected to the */
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/* IOHUB */
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short mpc_reserv16; /* reserved 16-bits value */
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unsigned long pci_mem_start; /* PCI mem area for IOMMU v6 */
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unsigned long pci_mem_end;
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} mpc_config_iolink_t;
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enum mp_iolink_type {
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MP_IOLINK_IOHUB = 1, /* IO link is IOHUB */
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MP_IOLINK_RDMA /* IO link is RDMA controller */
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};
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enum mp_iolink_ver {
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MP_IOHUB_FPGA_VER = 0x10, /* IOHUB implemented on FPGA (Altera) */
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};
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#define MAX_MP_TIMERS 4
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typedef struct mpc_config_timer {
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unsigned char mpc_type; /* MP_TIMER */
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unsigned char mpc_timertype;
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unsigned char mpc_timerver;
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unsigned char mpc_timerflags;
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unsigned long mpc_timeraddr;
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} mpc_config_timer_t;
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enum mp_timertype {
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MP_PIT_TYPE, /* programmed interval timer */
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MP_LT_TYPE, /* Elbrus iohub timer */
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MP_HPET_TYPE, /* High presicion eventualy timer */
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MP_RTC_TYPE, /* real time clock */
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MP_PM_TYPE /* power managment timer */
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};
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#define MP_LT_VERSION 1
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#define MP_LT_FLAGS 0
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#define MP_RTC_VER_CY14B101P 2
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#define MP_RTC_FLAG_SYNCINTR 0x01
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typedef struct mpc_config_i2c {
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unsigned char mpc_type; /* MP_I2C_SPI */
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unsigned char mpc_max_channel;
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unsigned char mpc_i2c_irq;
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unsigned char mpc_revision;
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unsigned long mpc_i2ccntrladdr;
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unsigned long mpc_i2cdataaddr;
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} mpc_config_i2c_t;
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typedef struct mpc_config_pmc {
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unsigned char mpc_type; /* MP_PMC */
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unsigned char mpc_pmc_type; /* Izumrud or Processor-2 */
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unsigned char mpc_pmc_version;
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unsigned char mpc_pmc_vmax; /* VMAX: bits 40:34 in l_pmc.vrange */
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unsigned char mpc_pmc_vmin; /* VMIN: bits 33:27 in l_pmc.vrange */
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unsigned char mpc_pmc_fmax; /* FMAX: bits 26:20 in l_pmc.vrange */
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unsigned char reserved[2];
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unsigned long mpc_pmc_cntrl_addr; /* base of pmc regs */
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unsigned long mpc_pmc_data_addr;
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unsigned int mpc_pmc_data_size;
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unsigned int mpc_pmc_p_state[4]; /* VID 15:9, DID 8:4, FID 3:0 */
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unsigned int mpc_pmc_freq; /* Frequency in KHz */
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} mpc_config_pmc_t;
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typedef struct mpc_bdev {
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unsigned char mpc_type; /* MP_BDEV */
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unsigned char mpc_bustype; /* I2C or SPI */
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unsigned char mpc_nodeid;
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unsigned char mpc_linkid;
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unsigned char mpc_busid;
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unsigned char mpc_baddr;
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unsigned char mpc_bdev_name[16];
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} mpc_bdev_t;
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#define MPC_BDEV_DTYPE_I2C 1
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#define MPC_BDEV_DTYPE_SPI 2
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typedef struct mpc_gpio_act {
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unsigned char mpc_type; /* MP_GPIO_ACT */
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unsigned char mpc_nodeid;
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unsigned char mpc_linkid;
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unsigned char mpc_busid;
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unsigned char mpc_gpio_pin;
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unsigned char mpc_pin_direction;
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unsigned char mpc_gpio_act_name[16];
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} mpc_gpio_act_t;
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#define MP_GPIO_ACT_DIRECTION_IN 1
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#define MP_GPIO_ACT_DIRECTION_OUT 2
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#ifdef __KERNEL__
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struct iohub_sysdata;
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void mp_pci_add_resources(struct list_head *resources,
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struct iohub_sysdata *sd);
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extern int __init mp_ioepic_find_bus(int ioepic_id);
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#ifdef CONFIG_IOHUB_DOMAINS
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struct iohub_sysdata;
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extern int mp_find_iolink_root_busnum(int node, int link);
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extern int mp_find_iolink_io_apicid(int node, int link);
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extern int mp_fix_io_apicid(unsigned int src_apicid, unsigned int new_apicid);
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void mp_pci_add_resources(struct list_head *resources,
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struct iohub_sysdata *sd);
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extern int mp_iohubs_num;
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#else
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static inline int mp_fix_io_apicid(unsigned int src_apicid,
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unsigned int new_apicid)
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{
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return 0;
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}
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#endif /* CONFIG_IOHUB_DOMAINS */
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extern int get_bus_to_io_apicid(int busnum);
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#if defined(CONFIG_MCA) || defined(CONFIG_EISA)
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extern int mp_bus_id_to_type [MAX_MP_BUSSES];
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#endif
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extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
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extern struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
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extern unsigned int boot_cpu_physical_apicid;
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extern int smp_found_config;
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extern void find_smp_config(boot_info_t *bblock);
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extern void get_smp_config(void);
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extern int nr_ioapics;
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extern int apic_version[MAX_LOCAL_APIC];
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extern int mp_irq_entries;
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extern struct mpc_intsrc mp_irqs [];
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extern int mpc_default_type;
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extern unsigned long mp_lapic_addr;
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extern int pic_mode;
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extern int using_apic_timer;
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extern mpc_config_timer_t mp_timers[MAX_MP_TIMERS];
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extern int nr_timers;
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extern int rtc_model;
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extern int rtc_syncintr;
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#define early_iohub_online(node, link) mach_early_iohub_online((node), (link))
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#define early_sic_init() mach_early_sic_init()
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#endif /* __KERNEL__ */
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#ifdef CONFIG_ENABLE_BIOS_MPTABLE
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#define MPE_SYSTEM_ADDRESS_SPACE 0x80
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#define MPE_BUS_HIERARCHY 0x81
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#define MPE_COMPATIBILITY_ADDRESS_SPACE 0x82
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struct mp_exten_config {
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unsigned char mpe_type;
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unsigned char mpe_length;
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};
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typedef struct mp_exten_config *mpe_t;
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struct mp_exten_system_address_space {
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unsigned char mpe_type;
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unsigned char mpe_length;
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unsigned char mpe_busid;
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unsigned char mpe_address_type;
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#define ADDRESS_TYPE_IO 0
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#define ADDRESS_TYPE_MEM 1
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#define ADDRESS_TYPE_PREFETCH 2
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unsigned int mpe_address_base_low;
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unsigned int mpe_address_base_high;
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unsigned int mpe_address_length_low;
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unsigned int mpe_address_length_high;
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};
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struct mp_exten_bus_hierarchy {
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unsigned char mpe_type;
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unsigned char mpe_length;
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unsigned char mpe_busid;
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unsigned char mpe_bus_info;
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#define BUS_SUBTRACTIVE_DECODE 1
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unsigned char mpe_parent_busid;
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unsigned char reserved[3];
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};
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struct mp_exten_compatibility_address_space {
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unsigned char mpe_type;
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unsigned char mpe_length;
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unsigned char mpe_busid;
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unsigned char mpe_address_modifier;
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#define ADDRESS_RANGE_SUBTRACT 1
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#define ADDRESS_RANGE_ADD 0
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unsigned int mpe_range_list;
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#define RANGE_LIST_IO_ISA 0
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/* X100 - X3FF
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* X500 - X7FF
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* X900 - XBFF
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* XD00 - XFFF
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*/
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#define RANGE_LIST_IO_VGA 1
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/* X3B0 - X3BB
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* X3C0 - X3DF
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* X7B0 - X7BB
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* X7C0 - X7DF
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* XBB0 - XBBB
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* XBC0 - XBDF
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* XFB0 - XFBB
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* XFC0 - XCDF
|
|
*/
|
|
};
|
|
|
|
/* Default local apic addr */
|
|
#define LAPIC_ADDR 0xFEE00000
|
|
|
|
#ifdef __KERNEL__
|
|
void *smp_next_mpc_entry(struct mpc_table *mc);
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|
void *smp_next_mpe_entry(struct mpc_table *mc);
|
|
|
|
void smp_write_processor(struct mpc_table *mc,
|
|
unsigned char apicid, unsigned char apicver,
|
|
unsigned char cpuflag, unsigned int cpufeature,
|
|
unsigned int featureflag, unsigned int cepictimerfreq);
|
|
void smp_write_processors(struct mpc_table *mc,
|
|
unsigned int phys_cpu_num);
|
|
void smp_write_bus(struct mpc_table *mc,
|
|
unsigned char id, unsigned char *bustype);
|
|
void smp_write_ioapic(struct mpc_table *mc,
|
|
unsigned char id, unsigned char ver,
|
|
unsigned long apicaddr);
|
|
void smp_write_ioepic(struct mpc_table *mc,
|
|
unsigned short id, unsigned short nodeid,
|
|
unsigned char ver, unsigned long epicaddr);
|
|
void smp_write_iolink(struct mpc_table *mc,
|
|
int node, int link,
|
|
short bus_min, short bus_max,
|
|
short picid,
|
|
unsigned long pci_mem_start, unsigned long pci_mem_end);
|
|
void smp_write_intsrc(struct mpc_table *mc,
|
|
unsigned char irqtype, unsigned short irqflag,
|
|
unsigned char srcbus, unsigned char srcbusirq,
|
|
unsigned char dstapic, unsigned char dstirq);
|
|
void smp_write_lintsrc(struct mpc_table *mc,
|
|
unsigned char irqtype, unsigned short irqflag,
|
|
unsigned char srcbusid, unsigned char srcbusirq,
|
|
unsigned char destapic, unsigned char destapiclint);
|
|
void smp_write_address_space(struct mpc_table *mc,
|
|
unsigned char busid, unsigned char address_type,
|
|
unsigned int address_base_low, unsigned int address_base_high,
|
|
unsigned int address_length_low, unsigned int address_length_high);
|
|
void smp_write_bus_hierarchy(struct mpc_table *mc,
|
|
unsigned char busid, unsigned char bus_info,
|
|
unsigned char parent_busid);
|
|
void smp_write_compatibility_address_space(struct mpc_table *mc,
|
|
unsigned char busid, unsigned char address_modifier,
|
|
unsigned int range_list);
|
|
unsigned char smp_compute_checksum(void *v, int len);
|
|
void smp_write_floating_table(struct intel_mp_floating *mpf);
|
|
unsigned int write_smp_table(struct intel_mp_floating *mpf, unsigned int phys_cpu_num);
|
|
void smp_i2c_spi_timer(struct mpc_table *mc,
|
|
unsigned char timertype, unsigned char timerver,
|
|
unsigned char timerflags, unsigned long timeraddr);
|
|
void smp_i2c_spi_dev(struct mpc_table *mc, unsigned char max_channel,
|
|
unsigned char irq, unsigned long i2cdevaddr);
|
|
//#define MAX_CPUS 16 /* 16 way CPU system */
|
|
#endif /* __KERNEL__ */
|
|
|
|
/* A table (per mainboard) listing the initial apicid of each cpu. */
|
|
//extern unsigned int initial_apicid[MAX_CPUS];
|
|
#endif /* CONFIG_ENABLE_BIOS_MPTABLE */
|
|
|
|
int generic_processor_info(int apicid, int version);
|
|
|
|
#ifdef __KERNEL__
|
|
extern void print_bootblock(bootblock_struct_t *bootblock);
|
|
#endif /* __KERNEL__ */
|
|
|
|
#ifdef CONFIG_ACPI
|
|
extern void mp_register_ioapic(int id, unsigned long address, u32 gsi_base);
|
|
extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
|
|
u32 gsi);
|
|
extern void mp_config_acpi_legacy_irqs(void);
|
|
struct device;
|
|
extern int mp_register_gsi(struct device *dev, u32 gsi, int edge_level,
|
|
int active_high_low);
|
|
extern int acpi_probe_gsi(void);
|
|
#ifdef CONFIG_L_IO_APIC
|
|
extern int mp_find_ioapic(u32 gsi);
|
|
extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
|
|
#endif
|
|
#else /* !CONFIG_ACPI: */
|
|
static inline int acpi_probe_gsi(void)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_ACPI */
|
|
|
|
/* physid definitions */
|
|
/*
|
|
* On e2k and sparc lapics number is the same as cpus number
|
|
* IO-APICs number is defined by MAX_IO_APICS
|
|
* IO-APICs IDs can be placed higher than local APICs IDs or at its hole
|
|
* so physid_t cannot be a synonim to cpumask_t.
|
|
*/
|
|
#include <linux/bitmap.h>
|
|
|
|
#define MAX_PHYSID_NUM (NR_CPUS + MAX_IO_APICS)
|
|
typedef struct physid_mask {
|
|
DECLARE_BITMAP(bits, MAX_PHYSID_NUM);
|
|
} physid_mask_t;
|
|
|
|
#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_PHYSID_NUM)
|
|
|
|
#define physid_set(physid, map) set_bit((physid), (map).bits)
|
|
#define physid_clear(physid, map) clear_bit((physid), (map).bits)
|
|
#define physid_isset(physid, map) test_bit((physid), (map).bits)
|
|
#define physid_test_and_set(physid, map) test_and_set_bit((physid), (map).bits)
|
|
|
|
#define physids_and(dstp, src1, src2) \
|
|
bitmap_and((dst).bits, (src1).bits, (src2).bits, MAX_PHYSID_NUM)
|
|
|
|
#define physids_or(dst, src1, src2) \
|
|
bitmap_or((dst).bits, (src1).bits, (src2).bits, MAX_PHYSID_NUM)
|
|
|
|
#define physids_clear(map) \
|
|
bitmap_zero((map).bits, MAX_PHYSID_NUM)
|
|
|
|
#define physids_complement(dst, src) \
|
|
bitmap_complement((dst).bits, (src).bits, MAX_PHYSID_NUM)
|
|
|
|
#define physids_empty(map) \
|
|
bitmap_empty((map).bits, MAX_PHYSID_NUM)
|
|
|
|
#define physids_equal(map1, map2) \
|
|
bitmap_equal((map1).bits, (map2).bits, MAX_PHYSID_NUM)
|
|
|
|
#define physids_weight(map) \
|
|
bitmap_weight((map).bits, MAX_PHYSID_NUM)
|
|
|
|
#define physids_shift_left(dst, src, n) \
|
|
bitmap_shift_left((dst).bits, (src).bits, (n), MAX_PHYSID_NUM)
|
|
|
|
static inline unsigned long physids_coerce(physid_mask_t *map)
|
|
{
|
|
return map->bits[0];
|
|
}
|
|
|
|
static inline void physids_promote(unsigned long physids, physid_mask_t *map)
|
|
{
|
|
physids_clear(*map);
|
|
map->bits[0] = physids;
|
|
}
|
|
|
|
static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
|
|
{
|
|
physids_clear(*map);
|
|
physid_set(physid, *map);
|
|
}
|
|
|
|
#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
|
|
#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
|
|
|
|
extern physid_mask_t phys_cpu_present_map;
|
|
extern physid_mask_t phys_cpu_offline_map;
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* __L_ASM_MPSPEC_H */
|