104 lines
3.3 KiB
C
104 lines
3.3 KiB
C
#ifndef _L_ASM_L_TIMER_H
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#define _L_ASM_L_TIMER_H
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#include <linux/types.h>
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/*
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* Elbrus timer
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*/
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extern struct clock_event_device *global_clock_event;
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extern int get_lt_timer(void);
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extern u32 lt_read(void);
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extern struct clocksource lt_cs;
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/* New timer registers */
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#define PIT_COUNTER_LIMIT 0x00
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#define PIT_COUNTER_START_VALUE 0x04
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#define PIT_COUNTER 0x08
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#define PIT_COUNTER_CONTROL 0x0c
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#define PIT_WD_COUNTER 0x10
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#define PIT_WD_COUNTER_LOW PIT_WD_COUNTER
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#define PIT_WD_COUNTER_HIGH (PIT_WD_COUNTER_LOW + 0x04)
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#define PIT_WD_LIMIT 0x18
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#define PIT_POWER_COUNTER 0x1c
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#define PIT_POWER_COUNTER_LOW PIT_POWER_COUNTER
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#define PIT_POWER_COUNTER_HIGH (PIT_POWER_COUNTER_LOW + 0x04)
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#define PIT_WD_CONTROL 0x24
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#define PIT_RESET_COUNTER 0x28
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#define PIT_RESET_COUNTER_LOW PIT_RESET_COUNTER
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#define PIT_RESET_COUNTER_HIGH (PIT_RESET_COUNTER_LOW + 0x04)
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typedef struct lt_regs {
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u32 counter_limit; /* timer counter limit value */
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u32 counter_start; /* start value of counter */
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u32 counter; /* timer counter */
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u32 counter_cntr; /* timer control register */
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u32 wd_counter; /* watchdog counter */
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u32 wd_prescaler; /* watchdog prescaler */
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u32 wd_limit; /* watchdog limit */
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u32 power_counter_lo; /* power counter low bits */
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u32 power_counter_hi; /* power counter high bits */
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u32 wd_control; /* watchdog control register */
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u32 reset_counter_lo; /* reset counter low bits */
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u32 reset_counter_hi; /* reset counter low bits */
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} lt_regs_t;
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extern unsigned long long lt_phys_base;
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extern lt_regs_t *lt_regs;
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extern void setup_lt_timer(void);
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extern int __init init_lt_clocksource(void);
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/* counters registers structure */
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#define LT_COUNTER_SHIFT 9 /* [30: 9] counters value */
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#define LT_COUNTER_LIMIT_SHIFT 31 /* [31] Limit bit */
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#define LT_COUNTER_LIMIT_BIT (1 << LT_COUNTER_LIMIT_SHIFT)
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#define LT_WRITE_COUNTER_VALUE(count) ((count) << LT_COUNTER_SHIFT)
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#define LT_READ_COUNTER_VALUE(count) ((count) >> LT_COUNTER_SHIFT)
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#define LT_NSEC_PER_COUNTER_INCR 100 /* 10 MHz == 100 nunosec */
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/* counter control register structure */
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#define LT_COUNTER_CNTR_START 0x00000001 /* start/stop timer */
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#define LT_COUNTER_CNTR_INVERTL 0x00000002 /* invert limit bit */
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#define LT_COUNTER_CNTR_LINIT 0x00000004 /* Limit bit initial state */
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/* 1 - limit bit set to 1 */
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#define LT_COUNTER_CNTR_LAUNCH (LT_COUNTER_CNTR_START)
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#define LT_INVERT_COUNTER_CNTR_LAUNCH (LT_COUNTER_CNTR_LAUNCH | \
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LT_COUNTER_CNTR_INVERTL | \
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LT_COUNTER_CNTR_LINIT)
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#define LT_COUNTER_CNTR_STOP (0)
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#define WD_CLOCK_TICK_RATE 10000000L
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#define WD_LATCH(tick_rate) (((tick_rate) + HZ/2) / HZ)
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#define WD_LIMIT_SHIFT 12
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#define WD_WRITE_COUNTER_VALUE(count) (count)
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#define WD_READ_COUNTER_VALUE(count) ((count) << WD_LIMIT_SHIFT)
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#define WD_SET_COUNTER_VAL(sek) \
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(WD_WRITE_COUNTER_VALUE(WD_CLOCK_TICK_RATE * (sek)))
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#define WD_INTR_MODE 0x1
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#define WD_ENABLE 0x2
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#define WD_EVENT 0x4
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#define WD_COUNTER_BASE 0x10
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/* System timer Registers (structure see asm/l_timer_regs.h) */
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#define COUNTER_LIMIT 0x00
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#define COUNTER_START_VALUE 0x04
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#define L_COUNTER 0x08
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#define COUNTER_CONTROL 0x0c
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#define WD_COUNTER_L 0x10
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#define WD_COUNTER_H 0x14
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#define WD_LIMIT 0x18
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#define POWER_COUNTER_L 0x1c
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#define POWER_COUNTER_H 0x20
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#define WD_CONTROL 0x24
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#define RESET_COUNTER_L 0x28
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#define RESET_COUNTER_H 0x2c
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#endif /* _L_ASM_L_TIMER_H */
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