550 lines
20 KiB
C
550 lines
20 KiB
C
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#ifndef _E2K_CPU_REGS_ACCESS_H_
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#define _E2K_CPU_REGS_ACCESS_H_
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <asm/cpu_regs_types.h>
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#include <asm/native_cpu_regs_access.h>
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#ifndef __ASSEMBLY__
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#if CONFIG_CPU_ISET >= 3
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# define native_read_CORE_MODE_reg_value() \
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NATIVE_READ_CORE_MODE_REG_VALUE()
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# define native_write_CORE_MODE_reg_value(modes) \
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NATIVE_WRITE_CORE_MODE_REG_VALUE((modes));
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#else
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# define native_read_CORE_MODE_reg_value() \
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(machine.rrd(E2K_REG_CORE_MODE))
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# define native_write_CORE_MODE_reg_value(modes) \
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(machine.rwd(E2K_REG_CORE_MODE, modes))
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#endif
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#define native_read_OSCUTD_reg_value() \
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(machine.rrd(E2K_REG_OSCUTD))
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#define native_write_OSCUTD_reg_value(modes) \
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(machine.rwd(E2K_REG_OSCUTD, modes))
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#define native_read_OSCUIR_reg_value() \
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(machine.rrd(E2K_REG_OSCUIR))
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#define native_write_OSCUIR_reg_value() \
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(machine.rwd(E2K_REG_OSCUIR))
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#define boot_native_read_CORE_MODE_reg_value() \
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({ \
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typeof(boot_machine.boot_rrd) func; \
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func = boot_native_vp_to_pp(boot_machine.boot_rrd); \
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func(E2K_REG_CORE_MODE); \
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})
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#define boot_native_write_CORE_MODE_reg_value(modes) \
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({ \
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typeof(boot_machine.boot_rwd) func; \
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func = boot_native_vp_to_pp(boot_machine.boot_rwd); \
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func(E2K_REG_CORE_MODE, modes); \
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})
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#define boot_native_read_OSCUTD_reg_value() \
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({ \
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typeof(boot_machine.boot_rrd) func; \
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func = boot_native_vp_to_pp(boot_machine.boot_rrd); \
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func(E2K_REG_OSCUTD); \
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})
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#define boot_native_write_OSCUTD_reg_value(v) \
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({ \
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typeof(boot_machine.boot_rwd) func; \
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func = boot_native_vp_to_pp(boot_machine.boot_rwd); \
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func(E2K_REG_OSCUTD, (v)); \
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})
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#define boot_native_read_OSCUIR_reg_value() \
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({ \
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typeof(boot_machine.boot_rrd) func; \
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func = boot_native_vp_to_pp(boot_machine.boot_rrd); \
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func(E2K_REG_OSCUIR); \
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})
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#define boot_native_write_OSCUIR_reg_value(v) \
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({ \
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typeof(boot_machine.boot_rwd) func; \
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func = boot_native_vp_to_pp(boot_machine.boot_rwd); \
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func(E2K_REG_OSCUIR, v); \
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})
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#ifdef CONFIG_KVM_GUEST_KERNEL
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/* it is native guest kernel (not paravirtualized based on pv_ops) */
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#include <asm/kvm/cpu_regs_access.h>
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#elif defined(CONFIG_PARAVIRT_GUEST)
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/* it is paravirtualized host and guest kernel */
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#include <asm/paravirt/cpu_regs_access.h>
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#else /* native kernel */
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/* it is native kernel without any virtualization */
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/* or host kernel with virtualization support */
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/*
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* Set flags of updated VCPU registers
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*/
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#define PUT_UPDATED_CPU_REGS_FLAGS(flags)
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/*
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* Read/write word Procedure Stack Harware Top Pointer (PSHTP)
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*/
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#define READ_PSHTP_REG_VALUE() NATIVE_NV_READ_PSHTP_REG_VALUE()
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#define WRITE_PSHTP_REG_VALUE(PSHTP_value) \
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NATIVE_WRITE_PSHTP_REG_VALUE(PSHTP_value)
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/*
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* Read/write word Procedure Chain Stack Harware Top Pointer (PCSHTP)
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*/
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#define READ_PCSHTP_REG_SVALUE() NATIVE_READ_PCSHTP_REG_SVALUE()
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#define WRITE_PCSHTP_REG_SVALUE(PCSHTP_svalue) \
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NATIVE_WRITE_PCSHTP_REG_SVALUE(PCSHTP_svalue)
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/*
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* Read/write low/high double-word OS Compilation Unit Descriptor (OSCUD)
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*/
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#define READ_OSCUD_LO_REG_VALUE() NATIVE_READ_OSCUD_LO_REG_VALUE()
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#define READ_OSCUD_HI_REG_VALUE() NATIVE_READ_OSCUD_HI_REG_VALUE()
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#define BOOT_READ_OSCUD_LO_REG_VALUE() NATIVE_READ_OSCUD_LO_REG_VALUE()
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#define BOOT_READ_OSCUD_HI_REG_VALUE() NATIVE_READ_OSCUD_HI_REG_VALUE()
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#define WRITE_OSCUD_LO_REG_VALUE(OSCUD_lo_value) \
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NATIVE_WRITE_OSCUD_LO_REG_VALUE(OSCUD_lo_value)
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#define WRITE_OSCUD_HI_REG_VALUE(OSCUD_hi_value) \
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NATIVE_WRITE_OSCUD_HI_REG_VALUE(OSCUD_hi_value)
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#define BOOT_WRITE_OSCUD_LO_REG_VALUE(OSCUD_lo_value) \
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NATIVE_WRITE_OSCUD_LO_REG_VALUE(OSCUD_lo_value)
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#define BOOT_WRITE_OSCUD_HI_REG_VALUE(OSCUD_hi_value) \
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NATIVE_WRITE_OSCUD_HI_REG_VALUE(OSCUD_hi_value)
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/*
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* Read/write low/hgh double-word OS Globals Register (OSGD)
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*/
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#define READ_OSGD_LO_REG_VALUE() NATIVE_READ_OSGD_LO_REG_VALUE()
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#define READ_OSGD_HI_REG_VALUE() NATIVE_READ_OSGD_HI_REG_VALUE()
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#define BOOT_READ_OSGD_LO_REG_VALUE() NATIVE_READ_OSGD_LO_REG_VALUE()
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#define BOOT_READ_OSGD_HI_REG_VALUE() NATIVE_READ_OSGD_HI_REG_VALUE()
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#define WRITE_OSGD_LO_REG_VALUE(OSGD_lo_value) \
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NATIVE_WRITE_OSGD_LO_REG_VALUE(OSGD_lo_value)
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#define WRITE_OSGD_HI_REG_VALUE(OSGD_hi_value) \
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NATIVE_WRITE_OSGD_HI_REG_VALUE(OSGD_hi_value)
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#define BOOT_WRITE_OSGD_LO_REG_VALUE(OSGD_lo_value) \
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NATIVE_WRITE_OSGD_LO_REG_VALUE(OSGD_lo_value)
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#define BOOT_WRITE_OSGD_HI_REG_VALUE(OSGD_hi_value) \
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NATIVE_WRITE_OSGD_HI_REG_VALUE(OSGD_hi_value)
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/*
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* Read/write low/high double-word Compilation Unit Register (CUD)
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*/
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#define READ_CUD_LO_REG_VALUE() NATIVE_READ_CUD_LO_REG_VALUE()
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#define READ_CUD_HI_REG_VALUE() NATIVE_READ_CUD_HI_REG_VALUE()
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#define BOOT_READ_CUD_LO_REG_VALUE() NATIVE_READ_CUD_LO_REG_VALUE()
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#define BOOT_READ_CUD_HI_REG_VALUE() NATIVE_READ_CUD_HI_REG_VALUE()
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#define WRITE_CUD_LO_REG_VALUE(CUD_lo_value) \
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NATIVE_WRITE_CUD_LO_REG_VALUE(CUD_lo_value)
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#define WRITE_CUD_HI_REG_VALUE(CUD_hi_value) \
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NATIVE_WRITE_CUD_HI_REG_VALUE(CUD_hi_value)
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#define BOOT_WRITE_CUD_LO_REG_VALUE(CUD_lo_value) \
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NATIVE_WRITE_CUD_LO_REG_VALUE(CUD_lo_value)
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#define BOOT_WRITE_CUD_HI_REG_VALUE(CUD_hi_value) \
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NATIVE_WRITE_CUD_HI_REG_VALUE(CUD_hi_value)
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/*
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* Read/write low/high double-word Globals Register (GD)
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*/
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#define READ_GD_LO_REG_VALUE() NATIVE_READ_GD_LO_REG_VALUE()
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#define READ_GD_HI_REG_VALUE() NATIVE_READ_GD_HI_REG_VALUE()
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#define BOOT_READ_GD_LO_REG_VALUE() NATIVE_READ_GD_LO_REG_VALUE()
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#define BOOT_READ_GD_HI_REG_VALUE() NATIVE_READ_GD_HI_REG_VALUE()
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#define WRITE_GD_LO_REG_VALUE(GD_lo_value) \
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NATIVE_WRITE_GD_LO_REG_VALUE(GD_lo_value)
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#define WRITE_GD_HI_REG_VALUE(GD_hi_value) \
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NATIVE_WRITE_GD_HI_REG_VALUE(GD_hi_value)
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#define BOOT_WRITE_GD_LO_REG_VALUE(GD_lo_value) \
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NATIVE_WRITE_GD_LO_REG_VALUE(GD_lo_value)
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#define BOOT_WRITE_GD_HI_REG_VALUE(GD_hi_value) \
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NATIVE_WRITE_GD_HI_REG_VALUE(GD_hi_value)
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/*
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* Read/write low/high quad-word Procedure Stack Pointer Register (PSP)
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*/
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#define READ_PSP_LO_REG_VALUE() NATIVE_NV_READ_PSP_LO_REG_VALUE()
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#define READ_PSP_HI_REG_VALUE() NATIVE_NV_READ_PSP_HI_REG_VALUE()
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#define BOOT_READ_PSP_LO_REG_VALUE() NATIVE_NV_READ_PSP_LO_REG_VALUE()
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#define BOOT_READ_PSP_HI_REG_VALUE() NATIVE_NV_READ_PSP_HI_REG_VALUE()
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#define WRITE_PSP_LO_REG_VALUE(PSP_lo_value) \
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NATIVE_NV_WRITE_PSP_LO_REG_VALUE(PSP_lo_value)
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#define WRITE_PSP_HI_REG_VALUE(PSP_hi_value) \
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NATIVE_NV_NOIRQ_WRITE_PSP_HI_REG_VALUE(PSP_hi_value)
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#define BOOT_WRITE_PSP_LO_REG_VALUE(PSP_lo_value) \
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NATIVE_NV_WRITE_PSP_LO_REG_VALUE(PSP_lo_value)
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#define BOOT_WRITE_PSP_HI_REG_VALUE(PSP_hi_value) \
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NATIVE_NV_NOIRQ_WRITE_PSP_HI_REG_VALUE(PSP_hi_value)
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/*
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* Read/write low/high quad-word Procedure Chain Stack Pointer Register (PCSP)
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*/
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#define READ_PCSP_LO_REG_VALUE() NATIVE_NV_READ_PCSP_LO_REG_VALUE()
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#define READ_PCSP_HI_REG_VALUE() NATIVE_NV_READ_PCSP_HI_REG_VALUE()
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#define BOOT_READ_PCSP_LO_REG_VALUE() NATIVE_NV_READ_PCSP_LO_REG_VALUE()
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#define BOOT_READ_PCSP_HI_REG_VALUE() NATIVE_NV_READ_PCSP_HI_REG_VALUE()
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#define WRITE_PCSP_LO_REG_VALUE(PCSP_lo_value) \
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NATIVE_NV_WRITE_PCSP_LO_REG_VALUE(PCSP_lo_value)
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#define WRITE_PCSP_HI_REG_VALUE(PCSP_hi_value) \
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NATIVE_NV_NOIRQ_WRITE_PCSP_HI_REG_VALUE(PCSP_hi_value)
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#define BOOT_WRITE_PCSP_LO_REG_VALUE(PCSP_lo_value) \
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NATIVE_NV_WRITE_PCSP_LO_REG_VALUE(PCSP_lo_value)
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#define BOOT_WRITE_PCSP_HI_REG_VALUE(PCSP_hi_value) \
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NATIVE_NV_NOIRQ_WRITE_PCSP_HI_REG_VALUE(PCSP_hi_value)
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/*
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* Read/write low/high quad-word Current Chain Register (CR0/CR1)
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*/
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#define READ_CR0_LO_REG_VALUE() NATIVE_NV_READ_CR0_LO_REG_VALUE()
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#define READ_CR0_HI_REG_VALUE() NATIVE_NV_READ_CR0_HI_REG_VALUE()
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#define READ_CR1_LO_REG_VALUE() NATIVE_NV_READ_CR1_LO_REG_VALUE()
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#define READ_CR1_HI_REG_VALUE() NATIVE_NV_READ_CR1_HI_REG_VALUE()
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#define WRITE_CR0_LO_REG_VALUE(CR0_lo_value) \
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NATIVE_NV_NOIRQ_WRITE_CR0_LO_REG_VALUE(CR0_lo_value)
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#define WRITE_CR0_HI_REG_VALUE(CR0_hi_value) \
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NATIVE_NV_NOIRQ_WRITE_CR0_HI_REG_VALUE(CR0_hi_value)
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#define WRITE_CR1_LO_REG_VALUE(CR1_lo_value) \
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NATIVE_NV_NOIRQ_WRITE_CR1_LO_REG_VALUE(CR1_lo_value)
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#define WRITE_CR1_HI_REG_VALUE(CR1_hi_value) \
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NATIVE_NV_NOIRQ_WRITE_CR1_HI_REG_VALUE(CR1_hi_value)
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/*
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* Read/write double-word Control Transfer Preparation Registers
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* (CTPR1/CTPR2/CTPR3)
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*/
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#define READ_CTPR_REG_VALUE(reg_no) NATIVE_NV_READ_CTPR_REG_VALUE(reg_no)
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#define WRITE_CTPR_REG_VALUE(reg_no, CTPR_value) \
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NATIVE_WRITE_CTPR_REG_VALUE(reg_no, CTPR_value)
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/*
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* Read/write low/high double-word Non-Protected User Stack Descriptor
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* Register (USD)
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*/
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#define READ_USD_LO_REG_VALUE() NATIVE_NV_READ_USD_LO_REG_VALUE()
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#define READ_USD_HI_REG_VALUE() NATIVE_NV_READ_USD_HI_REG_VALUE()
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#define BOOT_READ_USD_LO_REG_VALUE() NATIVE_NV_READ_USD_LO_REG_VALUE()
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#define BOOT_READ_USD_HI_REG_VALUE() NATIVE_NV_READ_USD_HI_REG_VALUE()
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#define WRITE_USD_LO_REG_VALUE(USD_lo_value) \
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NATIVE_NV_WRITE_USD_LO_REG_VALUE(USD_lo_value)
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#define WRITE_USD_HI_REG_VALUE(USD_hi_value) \
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NATIVE_NV_WRITE_USD_HI_REG_VALUE(USD_hi_value)
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#define BOOT_WRITE_USD_LO_REG_VALUE(USD_lo_value) \
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NATIVE_NV_WRITE_USD_LO_REG_VALUE(USD_lo_value)
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#define BOOT_WRITE_USD_HI_REG_VALUE(USD_hi_value) \
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NATIVE_NV_WRITE_USD_HI_REG_VALUE(USD_hi_value)
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/*
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* Read/write low/high double-word Protected User Stack Descriptor
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* Register (PUSD)
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*/
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#define READ_PUSD_LO_REG_VALUE() NATIVE_NV_READ_PUSD_LO_REG_VALUE()
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#define READ_PUSD_HI_REG_VALUE() NATIVE_NV_READ_PUSD_HI_REG_VALUE()
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#define WRITE_PUSD_LO_REG_VALUE(PUSD_lo_value) \
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NATIVE_NV_WRITE_PUSD_LO_REG_VALUE(PUSD_lo_value)
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#define WRITE_PUSD_HI_REG_VALUE(PUSD_hi_value) \
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NATIVE_NV_WRITE_PUSD_HI_REG_VALUE(PUSD_hi_value)
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/*
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* Read/write double-word User Stacks Base Register (USBR)
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*/
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#define READ_USBR_REG_VALUE() NATIVE_NV_READ_USBR_REG_VALUE()
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#define READ_SBR_REG_VALUE() NATIVE_NV_READ_SBR_REG_VALUE()
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#define BOOT_READ_USBR_REG_VALUE() NATIVE_NV_READ_USBR_REG_VALUE()
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#define BOOT_READ_SBR_REG_VALUE() NATIVE_NV_READ_SBR_REG_VALUE()
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#define WRITE_USBR_REG_VALUE(USBR_value) \
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NATIVE_NV_WRITE_USBR_REG_VALUE(USBR_value)
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#define WRITE_SBR_REG_VALUE(SBR_value) \
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NATIVE_NV_WRITE_SBR_REG_VALUE(SBR_value)
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#define BOOT_WRITE_USBR_REG_VALUE(USBR_value) \
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NATIVE_NV_WRITE_USBR_REG_VALUE(USBR_value)
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#define BOOT_WRITE_SBR_REG_VALUE(SBR_value) \
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NATIVE_NV_WRITE_SBR_REG_VALUE(SBR_value)
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/*
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* Read/write double-word Window Descriptor Register (WD)
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*/
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#define READ_WD_REG_VALUE() NATIVE_READ_WD_REG_VALUE()
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#define WRITE_WD_REG_VALUE(WD_value) \
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NATIVE_WRITE_WD_REG_VALUE(WD_value)
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#ifdef NEED_PARAVIRT_LOOP_REGISTERS
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/*
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* Read/write double-word Loop Status Register (LSR)
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*/
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#define READ_LSR_REG_VALUE() NATIVE_READ_LSR_REG_VALUE()
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#define WRITE_LSR_REG_VALUE(LSR_value) \
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NATIVE_WRITE_LSR_REG_VALUE(LSR_value)
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/*
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* Read/write double-word Initial Loop Counters Register (ILCR)
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*/
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#define READ_ILCR_REG_VALUE() NATIVE_READ_ILCR_REG_VALUE()
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#define WRITE_ILCR_REG_VALUE(ILCR_value) \
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NATIVE_WRITE_ILCR_REG_VALUE(ILCR_value)
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/*
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* Write double-word LSR/ILCR registers in complex
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*/
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#define WRITE_LSR_LSR1_ILCR_ILCR1_REGS_VALUE(lsr, lsr1, ilcr, ilcr1) \
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NATIVE_WRITE_LSR_LSR1_ILCR_ILCR1_REGS_VALUE(lsr, lsr1, \
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ilcr, ilcr1)
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#endif /* NEED_PARAVIRT_LOOP_REGISTERS */
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/*
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* Read/write OS register which point to current process thread info
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* structure (OSR0)
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*/
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#define READ_CURRENT_REG_VALUE() NATIVE_NV_READ_OSR0_REG_VALUE()
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#define BOOT_READ_CURRENT_REG_VALUE() NATIVE_NV_READ_OSR0_REG_VALUE()
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#define WRITE_CURRENT_REG_VALUE(osr0_value) \
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NATIVE_NV_WRITE_OSR0_REG_VALUE(osr0_value)
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#define BOOT_WRITE_CURRENT_REG_VALUE(osr0_value) \
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NATIVE_NV_WRITE_OSR0_REG_VALUE(osr0_value)
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/*
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* Read/write OS Entries Mask (OSEM)
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*/
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#define READ_OSEM_REG_VALUE() NATIVE_READ_OSEM_REG_VALUE()
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#define WRITE_OSEM_REG_VALUE(osem_value) \
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NATIVE_WRITE_OSEM_REG_VALUE(osem_value)
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/*
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* Read/write word Base Global Register (BGR)
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*/
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#define READ_BGR_REG_VALUE() NATIVE_READ_BGR_REG_VALUE()
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#define BOOT_READ_BGR_REG_VALUE() NATIVE_READ_BGR_REG_VALUE()
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#define WRITE_BGR_REG_VALUE(BGR_value) \
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NATIVE_WRITE_BGR_REG_VALUE(BGR_value)
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#define BOOT_WRITE_BGR_REG_VALUE(BGR_value) \
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NATIVE_WRITE_BGR_REG_VALUE(BGR_value)
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/*
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* Read CPU current clock regigister (CLKR)
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*/
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#define READ_CLKR_REG_VALUE() NATIVE_READ_CLKR_REG_VALUE()
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/*
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* Read/Write system clock registers (SCLKM)
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*/
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#define READ_SCLKR_REG_VALUE() NATIVE_READ_SCLKR_REG_VALUE()
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#define READ_SCLKM1_REG_VALUE() NATIVE_READ_SCLKM1_REG_VALUE()
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#define READ_SCLKM2_REG_VALUE() NATIVE_READ_SCLKM2_REG_VALUE()
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#define READ_SCLKM3_REG_VALUE() NATIVE_READ_SCLKM3_REG_VALUE()
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#define WRITE_SCLKR_REG_VALUE(reg_value) \
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NATIVE_WRITE_SCLKR_REG_VALUE(reg_value)
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#define WRITE_SCLKM1_REG_VALUE(reg_value) \
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NATIVE_WRITE_SCLKM1_REG_VALUE(reg_value)
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#define WRITE_SCLKM2_REG_VALUE(reg_value) \
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NATIVE_WRITE_SCLKM2_REG_VALUE(reg_value)
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#define WRITE_SCLKM3_REG_VALUE(reg_value) \
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NATIVE_WRITE_SCLKM3_REG_VALUE(reg_value)
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/*
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* Read/Write Control Unit HardWare registers (CU_HW0/CU_HW1)
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*/
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#define READ_CU_HW0_REG_VALUE() NATIVE_READ_CU_HW0_REG_VALUE()
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#define READ_CU_HW1_REG_VALUE() NATIVE_READ_CU_HW1_REG_VALUE()
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#define WRITE_CU_HW0_REG_VALUE(reg) NATIVE_WRITE_CU_HW0_REG_VALUE(reg)
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#define WRITE_CU_HW1_REG_VALUE(reg) NATIVE_WRITE_CU_HW1_REG_VALUE(reg)
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/*
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* Read/write low/high double-word Recovery point register (RPR)
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*/
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#define READ_RPR_LO_REG_VALUE() NATIVE_READ_RPR_LO_REG_VALUE()
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#define READ_RPR_HI_REG_VALUE() NATIVE_READ_RPR_HI_REG_VALUE()
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#define READ_SBBP_REG_VALUE() NATIVE_READ_SBBP_REG_VALUE()
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#define WRITE_RPR_LO_REG_VALUE(RPR_lo_value) \
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NATIVE_WRITE_RPR_LO_REG_VALUE(RPR_lo_value)
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#define WRITE_RPR_HI_REG_VALUE(RPR_hi_value) \
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NATIVE_WRITE_RPR_HI_REG_VALUE(RPR_hi_value)
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/*
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* Read double-word CPU current Instruction Pointer register (IP)
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*/
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#define READ_IP_REG_VALUE() NATIVE_NV_READ_IP_REG_VALUE()
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/*
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* Read debug and monitors regigisters
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*/
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#define READ_DIBCR_REG_VALUE() NATIVE_READ_DIBCR_REG_VALUE()
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#define READ_DIBSR_REG_VALUE() NATIVE_READ_DIBSR_REG_VALUE()
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#define READ_DIMCR_REG_VALUE() NATIVE_READ_DIMCR_REG_VALUE()
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#define READ_DIBAR0_REG_VALUE() NATIVE_READ_DIBAR0_REG_VALUE()
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#define READ_DIBAR1_REG_VALUE() NATIVE_READ_DIBAR1_REG_VALUE()
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#define READ_DIBAR2_REG_VALUE() NATIVE_READ_DIBAR2_REG_VALUE()
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#define READ_DIBAR3_REG_VALUE() NATIVE_READ_DIBAR3_REG_VALUE()
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#define READ_DIMAR0_REG_VALUE() NATIVE_READ_DIMAR0_REG_VALUE()
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#define READ_DIMAR1_REG_VALUE() NATIVE_READ_DIMAR1_REG_VALUE()
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#define WRITE_DIBCR_REG_VALUE(DIBCR_value) \
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NATIVE_WRITE_DIBCR_REG_VALUE(DIBCR_value)
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#define WRITE_DIBSR_REG_VALUE(DIBSR_value) \
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NATIVE_WRITE_DIBSR_REG_VALUE(DIBSR_value)
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#define WRITE_DIMCR_REG_VALUE(DIMCR_value) \
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NATIVE_WRITE_DIMCR_REG_VALUE(DIMCR_value)
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#define WRITE_DIBAR0_REG_VALUE(DIBAR0_value) \
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NATIVE_WRITE_DIBAR0_REG_VALUE(DIBAR0_value)
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#define WRITE_DIBAR1_REG_VALUE(DIBAR1_value) \
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NATIVE_WRITE_DIBAR1_REG_VALUE(DIBAR1_value)
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#define WRITE_DIBAR2_REG_VALUE(DIBAR2_value) \
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NATIVE_WRITE_DIBAR2_REG_VALUE(DIBAR2_value)
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#define WRITE_DIBAR3_REG_VALUE(DIBAR3_value) \
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NATIVE_WRITE_DIBAR3_REG_VALUE(DIBAR3_value)
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#define WRITE_DIMAR0_REG_VALUE(DIMAR0_value) \
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NATIVE_WRITE_DIMAR0_REG_VALUE(DIMAR0_value)
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#define WRITE_DIMAR1_REG_VALUE(DIMAR1_value) \
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NATIVE_WRITE_DIMAR1_REG_VALUE(DIMAR1_value)
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/*
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* Read/write double-word Compilation Unit Table Register (CUTD)
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*/
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#define READ_CUTD_REG_VALUE() NATIVE_NV_READ_CUTD_REG_VALUE()
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#define WRITE_CUTD_REG_VALUE(CUTD_value) \
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NATIVE_NV_NOIRQ_WRITE_CUTD_REG_VALUE(CUTD_value)
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/*
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* Read word Compilation Unit Index Register (CUIR)
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*/
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#define READ_CUIR_REG_VALUE() NATIVE_READ_CUIR_REG_VALUE()
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/*
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* Read/write word Processor State Register (PSR)
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*/
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#define READ_PSR_REG_VALUE() NATIVE_NV_READ_PSR_REG_VALUE()
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#define BOOT_READ_PSR_REG_VALUE() NATIVE_NV_READ_PSR_REG_VALUE()
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#define WRITE_PSR_REG_VALUE(PSR_value) \
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NATIVE_WRITE_PSR_REG_VALUE(PSR_value)
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#define BOOT_WRITE_PSR_REG_VALUE(PSR_value) \
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NATIVE_WRITE_PSR_REG_VALUE(PSR_value)
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#define WRITE_PSR_IRQ_BARRIER(PSR_value) \
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NATIVE_WRITE_PSR_IRQ_BARRIER(PSR_value)
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/*
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* Read/write word User Processor State Register (UPSR)
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*/
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#define READ_UPSR_REG_VALUE() NATIVE_NV_READ_UPSR_REG_VALUE()
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#define BOOT_READ_UPSR_REG_VALUE() NATIVE_NV_READ_UPSR_REG_VALUE()
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#define WRITE_UPSR_REG_VALUE(UPSR_value) \
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NATIVE_WRITE_UPSR_REG_VALUE(UPSR_value)
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#define BOOT_WRITE_UPSR_REG_VALUE(UPSR_value) \
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NATIVE_WRITE_UPSR_REG_VALUE(UPSR_value)
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#define WRITE_UPSR_IRQ_BARRIER(UPSR_value) \
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NATIVE_WRITE_UPSR_IRQ_BARRIER(UPSR_value)
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/*
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|
* Read/write word floating point control registers (PFPFR/FPCR/FPSR)
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|
*/
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#define READ_PFPFR_REG_VALUE() NATIVE_NV_READ_PFPFR_REG_VALUE()
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#define READ_FPCR_REG_VALUE() NATIVE_NV_READ_FPCR_REG_VALUE()
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#define READ_FPSR_REG_VALUE() NATIVE_NV_READ_FPSR_REG_VALUE()
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#define WRITE_PFPFR_REG_VALUE(PFPFR_value) \
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NATIVE_NV_WRITE_PFPFR_REG_VALUE(PFPFR_value)
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#define WRITE_FPCR_REG_VALUE(FPCR_value) \
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NATIVE_NV_WRITE_FPCR_REG_VALUE(FPCR_value)
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#define WRITE_FPSR_REG_VALUE(FPSR_value) \
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NATIVE_NV_WRITE_FPSR_REG_VALUE(FPSR_value)
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/*
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|
* Read/write low/high double-word Intel segments registers (xS)
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|
*/
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#define READ_CS_LO_REG_VALUE() NATIVE_READ_CS_LO_REG_VALUE()
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#define READ_CS_HI_REG_VALUE() NATIVE_READ_CS_HI_REG_VALUE()
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#define READ_DS_LO_REG_VALUE() NATIVE_READ_DS_LO_REG_VALUE()
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#define READ_DS_HI_REG_VALUE() NATIVE_READ_DS_HI_REG_VALUE()
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#define READ_ES_LO_REG_VALUE() NATIVE_READ_ES_LO_REG_VALUE()
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#define READ_ES_HI_REG_VALUE() NATIVE_READ_ES_HI_REG_VALUE()
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#define READ_FS_LO_REG_VALUE() NATIVE_READ_FS_LO_REG_VALUE()
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#define READ_FS_HI_REG_VALUE() NATIVE_READ_FS_HI_REG_VALUE()
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#define READ_GS_LO_REG_VALUE() NATIVE_READ_GS_LO_REG_VALUE()
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#define READ_GS_HI_REG_VALUE() NATIVE_READ_GS_HI_REG_VALUE()
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#define READ_SS_LO_REG_VALUE() NATIVE_READ_SS_LO_REG_VALUE()
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#define READ_SS_HI_REG_VALUE() NATIVE_READ_SS_HI_REG_VALUE()
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#define WRITE_CS_LO_REG_VALUE(sd) NATIVE_CL_WRITE_CS_LO_REG_VALUE(sd)
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#define WRITE_CS_HI_REG_VALUE(sd) NATIVE_CL_WRITE_CS_HI_REG_VALUE(sd)
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|
#define WRITE_DS_LO_REG_VALUE(sd) NATIVE_CL_WRITE_DS_LO_REG_VALUE(sd)
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|
#define WRITE_DS_HI_REG_VALUE(sd) NATIVE_CL_WRITE_DS_HI_REG_VALUE(sd)
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|
#define WRITE_ES_LO_REG_VALUE(sd) NATIVE_CL_WRITE_ES_LO_REG_VALUE(sd)
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|
#define WRITE_ES_HI_REG_VALUE(sd) NATIVE_CL_WRITE_ES_HI_REG_VALUE(sd)
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|
#define WRITE_FS_LO_REG_VALUE(sd) NATIVE_CL_WRITE_FS_LO_REG_VALUE(sd)
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|
#define WRITE_FS_HI_REG_VALUE(sd) NATIVE_CL_WRITE_FS_HI_REG_VALUE(sd)
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|
#define WRITE_GS_LO_REG_VALUE(sd) NATIVE_CL_WRITE_GS_LO_REG_VALUE(sd)
|
|
#define WRITE_GS_HI_REG_VALUE(sd) NATIVE_CL_WRITE_GS_HI_REG_VALUE(sd)
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|
#define WRITE_SS_LO_REG_VALUE(sd) NATIVE_CL_WRITE_SS_LO_REG_VALUE(sd)
|
|
#define WRITE_SS_HI_REG_VALUE(sd) NATIVE_CL_WRITE_SS_HI_REG_VALUE(sd)
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|
|
|
/*
|
|
* Read doubleword User Processor Identification Register (IDR)
|
|
*/
|
|
#define READ_IDR_REG_VALUE() NATIVE_READ_IDR_REG_VALUE()
|
|
#define BOOT_READ_IDR_REG_VALUE() NATIVE_READ_IDR_REG_VALUE()
|
|
|
|
/*
|
|
* Processor Core Mode Register (CORE_MODE)
|
|
*/
|
|
#define READ_CORE_MODE_REG_VALUE() native_read_CORE_MODE_reg_value()
|
|
#define BOOT_READ_CORE_MODE_REG_VALUE() boot_native_read_CORE_MODE_reg_value()
|
|
#define WRITE_CORE_MODE_REG_VALUE(modes) \
|
|
native_write_CORE_MODE_reg_value(modes)
|
|
#define BOOT_WRITE_CORE_MODE_REG_VALUE(modes) \
|
|
boot_native_write_CORE_MODE_reg_value(modes)
|
|
|
|
/*
|
|
* OS Compilation Unit Table Descriptor Register (OSCUTD)
|
|
*/
|
|
#define READ_OSCUTD_REG_VALUE() native_read_OSCUTD_reg_value()
|
|
#define BOOT_READ_OSCUTD_REG_VALUE() boot_native_read_OSCUTD_reg_value()
|
|
#define WRITE_OSCUTD_REG_VALUE(desc) \
|
|
native_write_OSCUTD_reg_value(desc)
|
|
#define BOOT_WRITE_OSCUTD_REG_VALUE(desc) \
|
|
boot_native_write_OSCUTD_reg_value((desc))
|
|
|
|
/*
|
|
* OS Compilation Unit Index Register (OSCUIR)
|
|
*/
|
|
#define READ_OSCUIR_REG_VALUE() native_read_OSCUIR_reg_value()
|
|
#define WRITE_OSCUIR_REG_VALUE(v) native_write_OSCUIR_reg_value((v))
|
|
#define BOOT_READ_OSCUIR_REG_VALUE() boot_native_read_OSCUIR_reg_value()
|
|
#define BOOT_WRITE_OSCUIR_REG_VALUE(v) boot_native_write_OSCUIR_reg_value((v))
|
|
|
|
#endif /* CONFIG_KVM_GUEST_KERNEL */
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif /* _E2K_CPU_REGS_ACCESS_H_ */
|