555 lines
20 KiB
C
555 lines
20 KiB
C
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#ifndef _E2K_NATIVE_CPU_REGS_ACCESS_H_
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#define _E2K_NATIVE_CPU_REGS_ACCESS_H_
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <asm/e2k_api.h>
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#include <asm/cpu_regs_types.h>
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/*
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* Read/write low/high double-word OS Compilation Unit Descriptor (OSCUD)
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*/
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#define NATIVE_READ_OSCUD_LO_REG_VALUE() NATIVE_GET_DSREG_CLOSED(oscud.lo)
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#define NATIVE_READ_OSCUD_HI_REG_VALUE() NATIVE_GET_DSREG_CLOSED(oscud.hi)
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#define NATIVE_WRITE_OSCUD_LO_REG_VALUE(OSCUD_lo_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(oscud.lo, OSCUD_lo_value, 5)
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#define NATIVE_WRITE_OSCUD_HI_REG_VALUE(OSCUD_hi_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(oscud.hi, OSCUD_hi_value, 5)
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#define NATIVE_WRITE_OSCUD_LO_REG(OSCUD_lo) \
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({ \
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NATIVE_WRITE_OSCUD_LO_REG_VALUE(OSCUD_lo.OSCUD_lo_half); \
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})
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#define NATIVE_NV_NOIRQ_WRITE_OSCUD_HI_REG(OSCUD_hi) \
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({ \
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NATIVE_WRITE_OSCUD_HI_REG_VALUE(OSCUD_hi.OSCUD_hi_half); \
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})
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#define NATIVE_WRITE_OSCUD_REG_VALUE(OSCUD_hi_value, OSCUD_lo_value) \
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({ \
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NATIVE_WRITE_OSCUD_HI_REG_VALUE(OSCUD_hi_value); \
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NATIVE_WRITE_OSCUD_LO_REG_VALUE(OSCUD_lo_value); \
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})
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#define NATIVE_WRITE_OSCUD_REG(OSCUD_hi, OSCUD_lo) \
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({ \
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NATIVE_WRITE_OSCUD_REG_VALUE(OSCUD_hi.OSCUD_hi_half, \
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OSCUD_lo.OSCUD_lo_half); \
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})
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/*
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* Read/write low/hgh double-word OS Globals Register (OSGD)
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*/
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#define NATIVE_READ_OSGD_LO_REG_VALUE() NATIVE_GET_DSREG_CLOSED(osgd.lo)
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#define NATIVE_READ_OSGD_HI_REG_VALUE() NATIVE_GET_DSREG_CLOSED(osgd.hi)
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#define NATIVE_WRITE_OSGD_LO_REG_VALUE(OSGD_lo_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(osgd.lo, OSGD_lo_value, 5)
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#define NATIVE_WRITE_OSGD_HI_REG_VALUE(OSGD_hi_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(osgd.hi, OSGD_hi_value, 5)
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#define NATIVE_WRITE_OSGD_LO_REG(OSGD_lo) \
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({ \
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NATIVE_WRITE_OSGD_LO_REG_VALUE(OSGD_lo.OSGD_lo_half); \
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})
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#define NATIVE_WRITE_OSGD_HI_REG(OSGD_hi) \
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({ \
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NATIVE_WRITE_OSGD_HI_REG_VALUE(OSGD_hi.OSGD_hi_half); \
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})
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#define NATIVE_WRITE_OSGD_REG_VALUE(OSGD_hi_value, OSGD_lo_value) \
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({ \
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NATIVE_WRITE_OSGD_HI_REG_VALUE(OSGD_hi_value); \
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NATIVE_WRITE_OSGD_LO_REG_VALUE(OSGD_lo_value); \
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})
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#define NATIVE_WRITE_OSGD_REG(OSGD_hi, OSGD_lo) \
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({ \
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NATIVE_WRITE_OSGD_REG_VALUE(OSGD_hi.OSGD_hi_half, \
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OSGD_lo.OSGD_lo_half); \
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})
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/*
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* Read/write low/high double-word Compilation Unit Register (CUD)
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*/
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#define NATIVE_READ_CUD_LO_REG_VALUE() NATIVE_GET_DSREG_CLOSED(cud.lo)
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#define NATIVE_READ_CUD_HI_REG_VALUE() NATIVE_GET_DSREG_CLOSED(cud.hi)
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#define NATIVE_WRITE_CUD_LO_REG_VALUE(CUD_lo_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(cud.lo, CUD_lo_value, 4)
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#define NATIVE_WRITE_CUD_HI_REG_VALUE(CUD_hi_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(cud.hi, CUD_hi_value, 4)
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#define NATIVE_WRITE_CUD_LO_REG(CUD_lo) \
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({ \
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NATIVE_WRITE_CUD_LO_REG_VALUE(CUD_lo.CUD_lo_half); \
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})
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#define NATIVE_WRITE_CUD_HI_REG(CUD_hi) \
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({ \
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NATIVE_WRITE_CUD_HI_REG_VALUE(CUD_hi.CUD_hi_half); \
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})
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#define NATIVE_WRITE_CUD_REG_VALUE(CUD_hi_value, CUD_lo_value) \
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({ \
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NATIVE_WRITE_CUD_HI_REG_VALUE(CUD_hi_value); \
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NATIVE_WRITE_CUD_LO_REG_VALUE(CUD_lo_value); \
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})
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#define NATIVE_WRITE_CUD_REG(CUD_hi, CUD_lo) \
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({ \
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NATIVE_WRITE_CUD_REG_VALUE(CUD_hi.CUD_hi_half, CUD_lo.CUD_lo_half); \
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})
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/*
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* Read/write low/high double-word Globals Register (GD)
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*/
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#define NATIVE_READ_GD_LO_REG_VALUE() NATIVE_GET_DSREG_CLOSED(gd.lo)
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#define NATIVE_READ_GD_HI_REG_VALUE() NATIVE_GET_DSREG_CLOSED(gd.hi)
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#define NATIVE_WRITE_GD_LO_REG_VALUE(GD_lo_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(gd.lo, GD_lo_value, 4)
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#define NATIVE_WRITE_GD_HI_REG_VALUE(GD_hi_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(gd.hi, GD_hi_value, 4)
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#define NATIVE_WRITE_GD_LO_REG(GD_lo) \
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NATIVE_WRITE_GD_LO_REG_VALUE(GD_lo.GD_lo_half)
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#define NATIVE_WRITE_GD_HI_REG(GD_hi) \
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NATIVE_WRITE_GD_HI_REG_VALUE(GD_hi.GD_hi_half)
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#define NATIVE_WRITE_GD_REG_VALUE(GD_hi_value, GD_lo_value) \
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({ \
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NATIVE_WRITE_GD_HI_REG_VALUE(GD_hi_value); \
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NATIVE_WRITE_GD_LO_REG_VALUE(GD_lo_value); \
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})
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#define NATIVE_WRITE_GD_REG(GD_hi, GD_lo) \
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({ \
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NATIVE_WRITE_GD_REG_VALUE(GD_hi.GD_hi_half, GD_lo.GD_lo_half); \
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})
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/*
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* Read/write low/high quad-word Procedure Stack Pointer Register (PSP)
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*/
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#define NATIVE_NV_READ_PSP_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(psp.lo)
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#define NATIVE_NV_READ_PSP_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(psp.hi)
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#define NATIVE_NV_WRITE_PSP_LO_REG_VALUE(PSP_lo_value) \
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NATIVE_SET_DSREG_OPEN(psp.lo, PSP_lo_value)
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#define NATIVE_NV_NOIRQ_WRITE_PSP_HI_REG_VALUE(PSP_hi_value) \
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NATIVE_SET_DSREG_OPEN_NOIRQ(psp.hi, PSP_hi_value)
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/*
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* Read/write word Procedure Stack Harware Top Pointer (PSHTP)
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*/
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#define NATIVE_NV_READ_PSHTP_REG_VALUE() NATIVE_GET_DSREG_OPEN(pshtp)
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#define NATIVE_WRITE_PSHTP_REG_VALUE(PSHTP_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(pshtp, PSHTP_value, 5)
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/*
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* Read/write low/high quad-word Procedure Chain Stack Pointer Register (PCSP)
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*/
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#define NATIVE_NV_READ_PCSP_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(pcsp.lo)
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#define NATIVE_NV_READ_PCSP_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(pcsp.hi)
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#define NATIVE_NV_WRITE_PCSP_LO_REG_VALUE(PCSP_lo_value) \
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NATIVE_SET_DSREG_OPEN(pcsp.lo, PCSP_lo_value)
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#define NATIVE_NV_NOIRQ_WRITE_PCSP_HI_REG_VALUE(PCSP_hi_value) \
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NATIVE_SET_DSREG_OPEN_NOIRQ(pcsp.hi, PCSP_hi_value)
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/*
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* Read/write low/high quad-word Current Chain Register (CR0/CR1)
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*/
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#define NATIVE_NV_READ_CR0_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(cr0.lo)
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#define NATIVE_NV_READ_CR0_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(cr0.hi)
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#define NATIVE_NV_READ_CR1_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(cr1.lo)
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#define NATIVE_NV_READ_CR1_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(cr1.hi)
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#define NATIVE_NV_NOIRQ_WRITE_CR0_LO_REG_VALUE(CR0_lo_value) \
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NATIVE_SET_DSREG_OPEN_NOIRQ(cr0.lo, CR0_lo_value)
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#define NATIVE_NV_NOIRQ_WRITE_CR0_HI_REG_VALUE(CR0_hi_value) \
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NATIVE_SET_DSREG_OPEN_NOIRQ(cr0.hi, CR0_hi_value)
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#define NATIVE_NV_NOIRQ_WRITE_CR1_LO_REG_VALUE(CR1_lo_value) \
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NATIVE_SET_DSREG_OPEN_NOIRQ(cr1.lo, CR1_lo_value)
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#define NATIVE_NV_NOIRQ_WRITE_CR1_HI_REG_VALUE(CR1_hi_value) \
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NATIVE_SET_DSREG_OPEN_NOIRQ(cr1.hi, CR1_hi_value)
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/*
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* Read/write word Procedure Chain Stack Harware Top Pointer (PCSHTP)
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*/
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#define NATIVE_READ_PCSHTP_REG_SVALUE() \
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PCSHTP_SIGN_EXTEND(NATIVE_GET_SREG_OPEN(pcshtp))
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#define NATIVE_WRITE_PCSHTP_REG_SVALUE(PCSHTP_svalue) \
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NATIVE_SET_SREG_CLOSED_NOEXC(pcshtp, PCSHTP_svalue, 5)
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/*
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* Read/write double-word Control Transfer Preparation Registers
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* (CTPR1/CTPR2/CTPR3)
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*/
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#define NATIVE_NV_READ_CTPR_REG_VALUE(reg_no) \
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NATIVE_GET_DSREG_OPEN(ctpr##reg_no)
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#define NATIVE_READ_CTPR_HI_REG_VALUE(reg_no) \
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NATIVE_GET_DSREG_CLOSED_CLOBBERS(ctpr##reg_no.hi, \
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__stringify(ctpr##reg_no))
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#define NATIVE_WRITE_CTPR_REG_VALUE(reg_no, CTPR_value) \
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NATIVE_SET_DSREG_OPEN(ctpr##reg_no, CTPR_value)
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#define NATIVE_WRITE_CTPR_HI_REG_VALUE(reg_no, value) \
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NATIVE_SET_DSREG_CLOSED_EXC_CLOBBERS(ctpr##reg_no.hi, value, \
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4, __stringify(ctpr##reg_no))
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/*
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* Read/write low/high double-word Trap Info Registers (TIRs)
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*/
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#define NATIVE_READ_TIR_LO_REG_VALUE() NATIVE_GET_DSREG_CLOSED(tir.lo)
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#define NATIVE_READ_TIR_HI_REG_VALUE() NATIVE_GET_DSREG_CLOSED(tir.hi)
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#define NATIVE_WRITE_TIR_LO_REG_VALUE(TIR_lo_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(tir.lo, TIR_lo_value, 4)
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#define NATIVE_WRITE_TIR_HI_REG_VALUE(TIR_hi_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(tir.hi, TIR_hi_value, 4)
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/*
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* Read/write low/high double-word Trap Info Registers (TIRs)
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* as the low/high word structure
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*/
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#define NATIVE_READ_TIR_LO_REG() \
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({ \
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e2k_tir_lo_t TIR_lo; \
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TIR_lo.TIR_lo_reg = NATIVE_READ_TIR_LO_REG_VALUE(); \
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TIR_lo; \
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})
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#define NATIVE_READ_TIR_HI_REG() \
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({ \
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e2k_tir_hi_t TIR_hi; \
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TIR_hi.TIR_hi_reg = NATIVE_READ_TIR_HI_REG_VALUE(); \
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TIR_hi; \
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})
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static inline e2k_tir_lo_t
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native_read_TIR_lo_reg(void)
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{
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return NATIVE_READ_TIR_LO_REG();
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}
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static inline e2k_tir_hi_t
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native_read_TIR_hi_reg(void)
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{
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return NATIVE_READ_TIR_HI_REG();
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}
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/*
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* Read/write low/high double-word Non-Protected User Stack Descriptor
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* Register (USD)
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*/
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#define NATIVE_NV_READ_USD_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(usd.lo)
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#define NATIVE_NV_READ_USD_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(usd.hi)
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#define NATIVE_NV_WRITE_USD_LO_REG_VALUE(USD_lo_value) \
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NATIVE_SET_DSREG_OPEN(usd.lo, USD_lo_value)
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#define NATIVE_NV_WRITE_USD_HI_REG_VALUE(USD_hi_value) \
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NATIVE_SET_DSREG_OPEN(usd.hi, USD_hi_value)
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#define NATIVE_NV_WRITE_USBR_USD_REG_VALUE(usbr, usd_hi, usd_lo) \
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do { \
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NATIVE_NV_WRITE_USBR_REG_VALUE(usbr); \
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if (cpu_has(CPU_HWBUG_USD_ALIGNMENT)) \
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NATIVE_NV_WRITE_USD_LO_REG_VALUE(usd_lo); \
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NATIVE_NV_WRITE_USD_HI_REG_VALUE(usd_hi); \
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NATIVE_NV_WRITE_USD_LO_REG_VALUE(usd_lo); \
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} while (0)
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#define NATIVE_NV_WRITE_USBR_USD_REG(usbr, usd_hi, usd_lo) \
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do { \
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NATIVE_NV_WRITE_USBR_REG(usbr); \
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if (cpu_has(CPU_HWBUG_USD_ALIGNMENT)) \
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NATIVE_NV_WRITE_USD_LO_REG(usd_lo); \
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NATIVE_NV_WRITE_USD_HI_REG(usd_hi); \
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NATIVE_NV_WRITE_USD_LO_REG(usd_lo); \
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} while (0)
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/*
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* Read/write low/high double-word Protected User Stack Descriptor
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* Register (PUSD)
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*/
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#define NATIVE_NV_READ_PUSD_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(usd.lo)
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#define NATIVE_NV_READ_PUSD_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(usd.hi)
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#define NATIVE_NV_WRITE_PUSD_LO_REG_VALUE(PUSD_lo_value) \
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NATIVE_SET_DSREG_OPEN(usd.lo, PUSD_lo_value)
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#define NATIVE_NV_WRITE_PUSD_HI_REG_VALUE(PUSD_hi_value) \
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NATIVE_SET_DSREG_OPEN(usd.hi, PUSD_hi_value)
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/*
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* Read/write double-word User Stacks Base Register (USBR)
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*/
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#define NATIVE_NV_READ_USBR_REG_VALUE() NATIVE_GET_DSREG_OPEN(sbr)
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#define NATIVE_NV_READ_SBR_REG_VALUE() NATIVE_GET_DSREG_OPEN(sbr)
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#define NATIVE_NV_WRITE_USBR_REG_VALUE(USBR_value) \
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NATIVE_SET_DSREG_OPEN(sbr, USBR_value)
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#define NATIVE_NV_WRITE_SBR_REG_VALUE(SBR_value) \
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NATIVE_SET_DSREG_OPEN(sbr, SBR_value)
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#define NATIVE_NV_WRITE_USBR_REG(USBR) \
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NATIVE_NV_WRITE_USBR_REG_VALUE(USBR.USBR_reg)
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/*
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* Read/write double-word Window Descriptor Register (WD)
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*/
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#define NATIVE_READ_WD_REG_VALUE() NATIVE_GET_DSREG_OPEN(wd)
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#define NATIVE_WRITE_WD_REG_VALUE(WD_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(wd, WD_value, 5)
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/*
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* Read/write double-word Loop Status Register (LSR/LSR1)
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*/
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#define NATIVE_READ_LSR_REG_VALUE() NATIVE_GET_DSREG_OPEN(lsr)
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#define NATIVE_READ_LSR1_REG_VALUE() NATIVE_GET_DSREG_OPEN(lsr1)
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#define NATIVE_WRITE_LSR_REG_VALUE(LSR_value) \
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NATIVE_SET_DSREG_OPEN(lsr, LSR_value)
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#define NATIVE_WRITE_LSR1_REG_VALUE(LSR1_value) \
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NATIVE_SET_DSREG_OPEN(lsr1, LSR1_value)
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/*
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* Read/write double-word Loop Status Register (ILCR/ILCR1)
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*/
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#define NATIVE_READ_ILCR_REG_VALUE() NATIVE_GET_DSREG_OPEN(ilcr)
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#define NATIVE_READ_ILCR1_REG_VALUE() NATIVE_GET_DSREG_CLOSED(ilcr1)
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#define NATIVE_WRITE_ILCR_REG_VALUE(ILCR_value) \
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NATIVE_SET_DSREG_OPEN(ilcr, ILCR_value)
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#define NATIVE_WRITE_ILCR1_REG_VALUE(ILCR1_value) \
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NATIVE_SET_DSREG_CLOSED_EXC(ilcr1, ILCR1_value, 4)
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/*
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* Read/write OS register which point to current process thread info
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* structure (OSR0)
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*/
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#define NATIVE_NV_READ_OSR0_REG_VALUE() NATIVE_GET_DSREG_OPEN(osr0)
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#define NATIVE_NV_WRITE_OSR0_REG_VALUE(osr0_value) \
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NATIVE_SET_DSREG_OPEN(osr0, osr0_value)
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/*
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* Read/write OS Entries Mask (OSEM)
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*/
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#define NATIVE_READ_OSEM_REG_VALUE() NATIVE_GET_SREG_CLOSED(osem)
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#define NATIVE_WRITE_OSEM_REG_VALUE(osem_value) \
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NATIVE_SET_SREG_CLOSED_NOEXC(osem, osem_value, 5)
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/*
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* Read/write word Base Global Register (BGR)
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*/
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#define NATIVE_READ_BGR_REG_VALUE() NATIVE_GET_SREG_OPEN(bgr)
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#define NATIVE_WRITE_BGR_REG_VALUE(BGR_value) \
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NATIVE_SET_SREG_CLOSED_NOEXC(bgr, BGR_value, 5)
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/*
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* Read CPU current clock register (CLKR)
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*/
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#define NATIVE_READ_CLKR_REG_VALUE() NATIVE_GET_DSREG_CLOSED(clkr)
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#define NATIVE_WRITE_CLKR_REG_VALUE() \
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NATIVE_SET_DSREG_CLOSED_NOEXC(clkr, 0, 4)
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/*
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* Read/Write system clock registers (SCLKM)
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*/
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#define NATIVE_READ_SCLKR_REG_VALUE() NATIVE_GET_DSREG_OPEN(sclkr)
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#define NATIVE_READ_SCLKM1_REG_VALUE() NATIVE_GET_DSREG_OPEN(sclkm1)
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#define NATIVE_READ_SCLKM2_REG_VALUE() NATIVE_GET_DSREG_OPEN(sclkm2)
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#define NATIVE_READ_SCLKM3_REG_VALUE() NATIVE_GET_DSREG_CLOSED(sclkm3)
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#define NATIVE_WRITE_SCLKR_REG_VALUE(reg_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sclkr, reg_value, 4)
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#define NATIVE_WRITE_SCLKM1_REG_VALUE(reg_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sclkm1, reg_value, 4)
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#define NATIVE_WRITE_SCLKM2_REG_VALUE(reg_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sclkm2, reg_value, 4)
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#define NATIVE_WRITE_SCLKM3_REG_VALUE(reg_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(sclkm3, reg_value, 4)
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extern unsigned long native_read_SCLKR_reg_value(void);
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extern unsigned long native_read_SCLKM1_reg_value(void);
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extern unsigned long native_read_SCLKM2_reg_value(void);
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extern void native_write_SCLKR_reg_value(unsigned long reg_value);
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extern void native_write_SCLKM1_reg_value(unsigned long reg_value);
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extern void native_write_SCLKM2_reg_value(unsigned long reg_value);
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/*
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* Read/Write Control Unit HardWare registers (CU_HW0/CU_HW1)
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*/
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#define NATIVE_READ_CU_HW0_REG_VALUE() NATIVE_GET_DSREG_CLOSED(cu_hw0)
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#define NATIVE_READ_CU_HW1_REG_VALUE() NATIVE_GET_DSREG_CLOSED(cu_hw1)
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#define NATIVE_WRITE_CU_HW0_REG_VALUE(reg) \
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NATIVE_SET_DSREG_CLOSED_EXC(cu_hw0, reg, 5)
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#define NATIVE_WRITE_CU_HW1_REG_VALUE(reg) \
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NATIVE_SET_DSREG_CLOSED_EXC(cu_hw1, reg, 5)
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/*
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* Read/write low/high double-word Recovery point register (RPR)
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*/
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#define NATIVE_READ_RPR_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(rpr.lo)
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#define NATIVE_READ_RPR_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(rpr.hi)
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#define NATIVE_READ_SBBP_REG_VALUE() NATIVE_GET_DSREG_OPEN(sbbp)
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#define NATIVE_WRITE_SBBP_REG_VALUE(x) \
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NATIVE_SET_DSREG_CLOSED_EXC(sbbp, (x), 0)
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#define NATIVE_WRITE_RPR_LO_REG_VALUE(RPR_lo_value) \
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NATIVE_SET_DSREG_OPEN(rpr.lo, RPR_lo_value)
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#define NATIVE_WRITE_RPR_HI_REG_VALUE(RPR_hi_value) \
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NATIVE_SET_DSREG_OPEN(rpr.hi, RPR_hi_value)
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/*
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* Read double-word CPU current Instruction Pointer register (IP)
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*/
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#define NATIVE_READ_IP_REG_VALUE() NATIVE_GET_DSREG_CLOSED(ip)
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#define NATIVE_NV_READ_IP_REG_VALUE() NATIVE_GET_DSREG_OPEN(ip)
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/*
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* Read debug and monitors registers
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*/
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#define NATIVE_READ_DIBCR_REG_VALUE() NATIVE_GET_SREG_CLOSED(dibcr)
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#define NATIVE_READ_DIBSR_REG_VALUE() NATIVE_GET_SREG_CLOSED(dibsr)
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#define NATIVE_READ_DIMCR_REG_VALUE() NATIVE_GET_DSREG_CLOSED(dimcr)
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#define NATIVE_READ_DIBAR0_REG_VALUE() NATIVE_GET_DSREG_OPEN(dibar0)
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#define NATIVE_READ_DIBAR1_REG_VALUE() NATIVE_GET_DSREG_OPEN(dibar1)
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#define NATIVE_READ_DIBAR2_REG_VALUE() NATIVE_GET_DSREG_OPEN(dibar2)
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#define NATIVE_READ_DIBAR3_REG_VALUE() NATIVE_GET_DSREG_OPEN(dibar3)
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#define NATIVE_READ_DIMAR0_REG_VALUE() NATIVE_GET_DSREG_OPEN(dimar0)
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#define NATIVE_READ_DIMAR1_REG_VALUE() NATIVE_GET_DSREG_OPEN(dimar1)
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#define NATIVE_WRITE_DIBCR_REG_VALUE(DIBCR_value) \
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NATIVE_SET_SREG_CLOSED_NOEXC(dibcr, DIBCR_value, 4)
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#define NATIVE_WRITE_DIBSR_REG_VALUE(DIBSR_value) \
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NATIVE_SET_SREG_CLOSED_NOEXC(dibsr, DIBSR_value, 4)
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/* 6 cycles delay guarantess that all counting
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* is stopped and %dibsr is updated accordingly. */
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#define NATIVE_WRITE_DIMCR_REG_VALUE(DIMCR_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(dimcr, DIMCR_value, 5)
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#define NATIVE_WRITE_DIBAR0_REG_VALUE(DIBAR0_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(dibar0, DIBAR0_value, 4)
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#define NATIVE_WRITE_DIBAR1_REG_VALUE(DIBAR1_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(dibar1, DIBAR1_value, 4)
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#define NATIVE_WRITE_DIBAR2_REG_VALUE(DIBAR2_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(dibar2, DIBAR2_value, 4)
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#define NATIVE_WRITE_DIBAR3_REG_VALUE(DIBAR3_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(dibar3, DIBAR3_value, 4)
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#define NATIVE_WRITE_DIMAR0_REG_VALUE(DIMAR0_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(dimar0, DIMAR0_value, 4)
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#define NATIVE_WRITE_DIMAR1_REG_VALUE(DIMAR1_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(dimar1, DIMAR1_value, 4)
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/*
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* Read/write double-word Compilation Unit Table Register (CUTD/OSCUTD)
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*/
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#define NATIVE_NV_READ_CUTD_REG_VALUE() NATIVE_GET_DSREG_OPEN(cutd)
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#define NATIVE_READ_OSCUTD_REG_VALUE() NATIVE_GET_DSREG_CLOSED(oscutd)
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#define NATIVE_NV_NOIRQ_WRITE_CUTD_REG_VALUE(CUTD_value) \
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NATIVE_SET_DSREG_OPEN_NOIRQ(cutd, CUTD_value)
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#define NATIVE_WRITE_OSCUTD_REG_VALUE(CUTD_value) \
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NATIVE_SET_DSREG_CLOSED_NOEXC(oscutd, CUTD_value, 5)
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/*
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* Read/write word Compilation Unit Index Register (CUIR/OSCUIR)
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*/
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#define NATIVE_READ_CUIR_REG_VALUE() NATIVE_GET_SREG_CLOSED(cuir)
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#define NATIVE_READ_OSCUIR_REG_VALUE() NATIVE_GET_SREG_CLOSED(oscuir)
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#define NATIVE_WRITE_CUIR_REG_VALUE(x) \
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NATIVE_SET_SREG_CLOSED_NOEXC(cuir, (x), 5)
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#define NATIVE_WRITE_OSCUIR_REG_VALUE(x) \
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NATIVE_SET_SREG_CLOSED_NOEXC(oscuir, (x), 5)
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/*
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* Read/write word Processor State Register (PSR)
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*/
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#define NATIVE_NV_READ_PSR_REG_VALUE() NATIVE_GET_SREG_OPEN(psr)
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#define NATIVE_WRITE_PSR_REG_VALUE(PSR_value) \
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NATIVE_SET_SREG_CLOSED_EXC(psr, PSR_value, 5)
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#define NATIVE_WRITE_PSR_IRQ_BARRIER(psr_val) \
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NATIVE_SET_PSR_IRQ_BARRIER(psr_val)
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|
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/*
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* Read/write word User Processor State Register (UPSR)
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*/
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|
/* upsr reg - byte register, but linux used long flag
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* to save arch_local_irq_save.To avoid casting to long(redundant stx command)
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* we can used read long register.Suprisingly, but size of image.boot decreased
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* 4096 byte
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*/
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#define NATIVE_NV_READ_UPSR_REG_VALUE() NATIVE_GET_DSREG_OPEN(upsr)
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#define NATIVE_WRITE_UPSR_REG_VALUE(UPSR_value) \
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NATIVE_SET_SREG_CLOSED_EXC(upsr, UPSR_value, 4)
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#define NATIVE_WRITE_UPSR_IRQ_BARRIER(upsr_val) \
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NATIVE_SET_UPSR_IRQ_BARRIER(upsr_val)
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/*
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* Read/write word floating point control registers (PFPFR/FPCR/FPSR)
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*/
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#define NATIVE_NV_READ_PFPFR_REG_VALUE() NATIVE_GET_SREG_OPEN(pfpfr)
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#define NATIVE_NV_READ_FPCR_REG_VALUE() NATIVE_GET_SREG_OPEN(fpcr)
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#define NATIVE_NV_READ_FPSR_REG_VALUE() NATIVE_GET_SREG_OPEN(fpsr)
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#define NATIVE_NV_WRITE_PFPFR_REG_VALUE(PFPFR_value) \
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NATIVE_SET_SREG_OPEN(pfpfr, PFPFR_value)
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#define NATIVE_NV_WRITE_FPCR_REG_VALUE(FPCR_value) \
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NATIVE_SET_SREG_OPEN(fpcr, FPCR_value)
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#define NATIVE_NV_WRITE_FPSR_REG_VALUE(FPSR_value) \
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NATIVE_SET_SREG_OPEN(fpsr, FPSR_value)
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|
|
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/*
|
|
* Read/write low/high double-word Intel segments registers (xS)
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|
*/
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|
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|
#define NATIVE_READ_CS_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(cs.lo)
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|
#define NATIVE_READ_CS_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(cs.hi)
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#define NATIVE_READ_DS_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(ds.lo)
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|
#define NATIVE_READ_DS_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(ds.hi)
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#define NATIVE_READ_ES_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(es.lo)
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#define NATIVE_READ_ES_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(es.hi)
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|
#define NATIVE_READ_FS_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(fs.lo)
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|
#define NATIVE_READ_FS_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(fs.hi)
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|
#define NATIVE_READ_GS_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(gs.lo)
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|
#define NATIVE_READ_GS_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(gs.hi)
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|
#define NATIVE_READ_SS_LO_REG_VALUE() NATIVE_GET_DSREG_OPEN(ss.lo)
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|
#define NATIVE_READ_SS_HI_REG_VALUE() NATIVE_GET_DSREG_OPEN(ss.hi)
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|
|
|
#define NATIVE_CL_WRITE_CS_LO_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(cs.lo, sd)
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|
#define NATIVE_CL_WRITE_CS_HI_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(cs.hi, sd)
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|
#define NATIVE_CL_WRITE_DS_LO_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(ds.lo, sd)
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|
#define NATIVE_CL_WRITE_DS_HI_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(ds.hi, sd)
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|
#define NATIVE_CL_WRITE_ES_LO_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(es.lo, sd)
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|
#define NATIVE_CL_WRITE_ES_HI_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(es.hi, sd)
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|
#define NATIVE_CL_WRITE_FS_LO_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(fs.lo, sd)
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|
#define NATIVE_CL_WRITE_FS_HI_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(fs.hi, sd)
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|
#define NATIVE_CL_WRITE_GS_LO_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(gs.lo, sd)
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|
#define NATIVE_CL_WRITE_GS_HI_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(gs.hi, sd)
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|
#define NATIVE_CL_WRITE_SS_LO_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(ss.lo, sd)
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|
#define NATIVE_CL_WRITE_SS_HI_REG_VALUE(sd) NATIVE_SET_DSREG_OPEN(ss.hi, sd)
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|
|
|
/*
|
|
* Read doubleword User Processor Identification Register (IDR)
|
|
*/
|
|
#define NATIVE_READ_IDR_REG_VALUE() NATIVE_GET_DSREG_OPEN(idr)
|
|
|
|
/*
|
|
* Read/Write Processor Core Mode Register (CORE_MODE)
|
|
*/
|
|
#if __LCC__ > 125 || __LCC__ == 125 && __LCC_MINOR__ >= 8
|
|
# define NATIVE_READ_CORE_MODE_REG_VALUE() NATIVE_GET_SREG_OPEN(core_mode)
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|
#else
|
|
# define NATIVE_READ_CORE_MODE_REG_VALUE() NATIVE_GET_SREG_CLOSED(core_mode)
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|
#endif
|
|
#define NATIVE_WRITE_CORE_MODE_REG_VALUE(modes) \
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|
NATIVE_SET_SREG_CLOSED_NOEXC(core_mode, modes, 5)
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|
|
#endif /* __ASSEMBLY__ */
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|
|
|
#endif /* __KERNEL__ */
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|
|
#endif /* _E2K_NATIVE_CPU_REGS_ACCESS_H_ */
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