339 lines
9.7 KiB
C
339 lines
9.7 KiB
C
/*
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* native E2K MMU structures & registers.
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*
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* Copyright 2014 Salavat S. Guiliazov (atic@mcst.ru)
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*/
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#ifndef _E2K_NATIVE_MMU_REGS_ACCESS_H_
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#define _E2K_NATIVE_MMU_REGS_ACCESS_H_
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/irqflags.h>
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#include <asm/e2k_api.h>
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#include <asm/e2k.h>
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#include <asm/debug_print.h>
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#endif /* __ASSEMBLY__ */
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#include <asm/mmu_regs_types.h>
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#include <asm/mas.h>
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#include <asm/native_dcache_regs_access.h>
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#undef DEBUG_MR_MODE
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#undef DebugMR
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#define DEBUG_MR_MODE 0 /* MMU registers access */
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#define DebugMR(...) DebugPrint(DEBUG_MR_MODE, ##__VA_ARGS__)
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#ifndef __ASSEMBLY__
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/*
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* Write/read MMU register
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*/
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#define NATIVE_WRITE_MMU_REG(addr_val, reg_val) \
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NATIVE_WRITE_MAS_D((addr_val), (reg_val), MAS_MMU_REG)
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#define NATIVE_READ_MMU_REG(addr_val) \
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NATIVE_READ_MAS_D((addr_val), MAS_MMU_REG)
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#define NATIVE_WRITE_MMU_CR(mmu_cr) \
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NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_CR_NO), \
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mmu_reg_val(mmu_cr))
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#define NATIVE_WRITE_MMU_TRAP_POINT(mmu_tc) \
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NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_TRAP_POINT_NO), \
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mmu_reg_val(mmu_tc))
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#define NATIVE_READ_MMU_TRAP_POINT() \
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NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_TRAP_POINT_NO))
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#define NATIVE_WRITE_MMU_US_CL_D(us_cl_d) \
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NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_US_CL_D_NO), \
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mmu_reg_val(us_cl_d))
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#define NATIVE_READ_MMU_US_CL_D() \
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NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_US_CL_D_NO))
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#define NATIVE_WRITE_MMU_OS_PPTB_REG_VALUE(mmu_phys_ptb) \
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NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_PPTB_NO), \
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mmu_reg_val(mmu_phys_ptb))
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#define NATIVE_READ_MMU_OS_PPTB_REG_VALUE() \
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NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_PPTB_NO))
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#define NATIVE_WRITE_MMU_OS_VPTB_REG_VALUE(mmu_virt_ptb) \
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NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_VPTB_NO), \
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mmu_reg_val(mmu_virt_ptb))
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#define NATIVE_READ_MMU_OS_VPTB_REG_VALUE() \
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NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_VPTB_NO))
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#define NATIVE_WRITE_MMU_OS_VAB_REG_VALUE(kernel_offset) \
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NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_VAB_NO), \
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mmu_reg_val(kernel_offset))
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#define NATIVE_READ_MMU_OS_VAB_REG_VALUE() \
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NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_VAB_NO))
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#define BOOT_NATIVE_WRITE_MMU_REG(addr_val, reg_val) \
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NATIVE_WRITE_MMU_REG(addr_val, reg_val)
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#define BOOT_NATIVE_READ_MMU_REG(addr_val) \
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NATIVE_READ_MMU_REG(addr_val)
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#define BOOT_NATIVE_WRITE_MMU_CR(mmu_cr) \
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BOOT_NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_CR_NO), \
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mmu_reg_val(mmu_cr))
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#define BOOT_NATIVE_WRITE_MMU_TRAP_POINT(mmu_tc) \
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BOOT_NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_TRAP_POINT_NO), \
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mmu_reg_val(mmu_tc))
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#define BOOT_NATIVE_READ_MMU_TRAP_POINT() \
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BOOT_NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_TRAP_POINT_NO))
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#define BOOT_NATIVE_WRITE_MMU_OS_PPTB_REG_VALUE(mmu_phys_ptb) \
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BOOT_NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_PPTB_NO), \
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mmu_reg_val(mmu_phys_ptb))
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#define BOOT_NATIVE_READ_MMU_OS_PPTB_REG_VALUE() \
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BOOT_NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_PPTB_NO))
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#define BOOT_NATIVE_WRITE_MMU_OS_VPTB_REG_VALUE(mmu_virt_ptb) \
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BOOT_NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_VPTB_NO), \
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mmu_reg_val(mmu_virt_ptb))
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#define BOOT_NATIVE_READ_MMU_OS_VPTB_REG_VALUE() \
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BOOT_NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_VPTB_NO))
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#define BOOT_NATIVE_WRITE_MMU_OS_VAB_REG_VALUE(kernel_offset) \
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BOOT_NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_VAB_NO), \
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mmu_reg_val(kernel_offset))
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#define BOOT_NATIVE_READ_MMU_OS_VAB_REG_VALUE() \
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BOOT_NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_OS_VAB_NO))
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/*
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* Write/read Data TLB register
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*/
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#define NATIVE_WRITE_DTLB_REG(tlb_addr, tlb_value) \
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NATIVE_WRITE_MAS_D((tlb_addr), (tlb_value), MAS_DTLB_REG)
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#define NATIVE_READ_DTLB_REG(tlb_addr) \
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NATIVE_READ_MAS_D((tlb_addr), MAS_DTLB_REG)
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/*
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* Flush TLB page/entry
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*/
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#define NATIVE_FLUSH_TLB_ENTRY(flush_op, addr) \
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NATIVE_WRITE_MAS_D((flush_op), (addr), MAS_TLB_PAGE_FLUSH)
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/*
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* Flush ICACHE line
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*/
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#define NATIVE_FLUSH_ICACHE_LINE(flush_op, addr) \
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NATIVE_WRITE_MAS_D((flush_op), (addr), MAS_ICACHE_LINE_FLUSH)
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/*
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* Flush and invalidate or write back CACHE(s) (invalidate all caches
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* of the processor)
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*/
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#define NATIVE_FLUSH_CACHE_L12(flush_op) \
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NATIVE_WRITE_MAS_D((flush_op), (0), MAS_CACHE_FLUSH)
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static inline void
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native_invalidate_CACHE_L12(void)
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{
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int invalidate_supported;
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unsigned long flags;
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DebugMR("Flush : Invalidate all CACHEs (op 0x%lx)\n",
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_flush_op_invalidate_cache_L12);
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/* Invalidate operation was removed in E2S */
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invalidate_supported = NATIVE_IS_MACHINE_ES2;
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raw_all_irq_save(flags);
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E2K_WAIT_MA;
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if (invalidate_supported)
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NATIVE_FLUSH_CACHE_L12(_flush_op_invalidate_cache_L12);
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else
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NATIVE_FLUSH_CACHE_L12(_flush_op_write_back_cache_L12);
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E2K_WAIT_FLUSH;
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raw_all_irq_restore(flags);
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}
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static inline void
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native_write_back_CACHE_L12(void)
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{
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unsigned long flags;
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DebugMR("Flush : Write back all CACHEs (op 0x%lx)\n",
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_flush_op_write_back_cache_L12);
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raw_all_irq_save(flags);
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E2K_WAIT_MA;
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NATIVE_FLUSH_CACHE_L12(_flush_op_write_back_cache_L12);
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E2K_WAIT_FLUSH;
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raw_all_irq_restore(flags);
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}
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/*
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* Flush TLB (invalidate all TLBs of the processor)
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*/
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#define NATIVE_FLUSH_TLB_ALL(flush_op) \
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NATIVE_WRITE_MAS_D((flush_op), (0), MAS_TLB_FLUSH)
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static inline void
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native_flush_TLB_all(void)
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{
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unsigned long flags;
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DebugMR("Flush all TLBs (op 0x%lx)\n", _flush_op_tlb_all);
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raw_all_irq_save(flags);
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E2K_WAIT_ST;
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NATIVE_FLUSH_TLB_ALL(_flush_op_tlb_all);
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E2K_WAIT(_fl_c | _ma_c);
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raw_all_irq_restore(flags);
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}
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/*
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* Flush ICACHE (invalidate instruction caches of the processor)
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*/
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#define NATIVE_FLUSH_ICACHE_ALL(flush_op) \
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NATIVE_WRITE_MAS_D((flush_op), (0), MAS_ICACHE_FLUSH)
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static inline void
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native_flush_ICACHE_all(void)
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{
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DebugMR("Flush all ICACHE op 0x%lx\n", _flush_op_icache_all);
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E2K_WAIT_ST;
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NATIVE_FLUSH_ICACHE_ALL(_flush_op_icache_all);
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E2K_WAIT_FLUSH;
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}
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/*
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* Get Entry probe for virtual address
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*/
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#define NATIVE_ENTRY_PROBE_MMU_OP(addr_val) \
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NATIVE_READ_MAS_D((addr_val), MAS_ENTRY_PROBE)
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/*
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* Get physical address for virtual address
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*/
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#define NATIVE_ADDRESS_PROBE_MMU_OP(addr_val) \
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NATIVE_READ_MAS_D((addr_val), MAS_VA_PROBE)
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/*
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* Read CLW register
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*/
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#define NATIVE_READ_CLW_REG(clw_addr) \
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NATIVE_READ_MAS_D_5((clw_addr), MAS_CLW_REG)
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/*
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* Write CLW register
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*/
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#define NATIVE_WRITE_CLW_REG(clw_addr, val) \
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NATIVE_WRITE_MAS_D((clw_addr), (val), MAS_CLW_REG)
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/*
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* native MMU DEBUG registers access
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*/
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#define NATIVE_READ_DDBAR0_REG_VALUE() \
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NATIVE_GET_MMUREG(ddbar0)
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#define NATIVE_READ_DDBAR1_REG_VALUE() \
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NATIVE_GET_MMUREG(ddbar1)
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#define NATIVE_READ_DDBAR2_REG_VALUE() \
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NATIVE_GET_MMUREG(ddbar2)
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#define NATIVE_READ_DDBAR3_REG_VALUE() \
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NATIVE_GET_MMUREG(ddbar3)
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#define NATIVE_READ_DDBCR_REG_VALUE() \
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NATIVE_GET_MMUREG(ddbcr)
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#define NATIVE_READ_DDBSR_REG_VALUE() \
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NATIVE_GET_MMUREG(ddbsr)
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#define NATIVE_READ_DDMAR0_REG_VALUE() \
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NATIVE_GET_MMUREG(ddmar0)
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#define NATIVE_READ_DDMAR1_REG_VALUE() \
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NATIVE_GET_MMUREG(ddmar1)
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#define NATIVE_READ_DDMCR_REG_VALUE() \
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NATIVE_GET_MMUREG(ddmcr)
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#define NATIVE_WRITE_DDBAR0_REG_VALUE(value) \
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NATIVE_SET_MMUREG(ddbar0, value)
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#define NATIVE_WRITE_DDBAR1_REG_VALUE(value) \
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NATIVE_SET_MMUREG(ddbar1, value)
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#define NATIVE_WRITE_DDBAR2_REG_VALUE(value) \
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NATIVE_SET_MMUREG(ddbar2, value)
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#define NATIVE_WRITE_DDBAR3_REG_VALUE(value) \
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NATIVE_SET_MMUREG(ddbar3, value)
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#define NATIVE_WRITE_DDBCR_REG_VALUE(value) \
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NATIVE_SET_MMUREG(ddbcr, value)
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#define NATIVE_WRITE_DDBSR_REG_VALUE(value) \
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NATIVE_SET_MMUREG(ddbsr, value)
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#define NATIVE_WRITE_DDMAR0_REG_VALUE(value) \
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NATIVE_SET_MMUREG(ddmar0, value)
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#define NATIVE_WRITE_DDMAR1_REG_VALUE(value) \
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NATIVE_SET_MMUREG(ddmar1, value)
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/* 4 cycles delay guarantess that all counting
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* is stopped and %ddbsr is updated accordingly. */
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#define NATIVE_WRITE_DDMCR_REG_VALUE(value) \
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NATIVE_SET_MMUREG_CLOSED(ddmcr, value, 3)
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#define NATIVE_READ_DDBAR0_REG() \
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NATIVE_READ_DDBAR0_REG_VALUE()
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#define NATIVE_READ_DDBAR1_REG() \
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NATIVE_READ_DDBAR1_REG_VALUE()
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#define NATIVE_READ_DDBAR2_REG() \
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NATIVE_READ_DDBAR2_REG_VALUE()
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#define NATIVE_READ_DDBAR3_REG() \
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NATIVE_READ_DDBAR3_REG_VALUE()
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#define NATIVE_READ_DDBCR_REG() \
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({ \
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e2k_ddbcr_t ddbcr; \
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\
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ddbcr.DDBCR_reg = NATIVE_READ_DDBCR_REG_VALUE(); \
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ddbcr; \
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})
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#define NATIVE_READ_DDBSR_REG() \
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({ \
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e2k_ddbsr_t ddbsr; \
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\
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ddbsr.DDBSR_reg = NATIVE_READ_DDBSR_REG_VALUE(); \
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ddbsr; \
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})
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#define NATIVE_READ_DDMAR0_REG() \
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NATIVE_READ_DDMAR0_REG_VALUE()
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#define NATIVE_READ_DDMAR1_REG() \
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NATIVE_READ_DDMAR1_REG_VALUE()
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#define NATIVE_READ_DDMCR_REG() \
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({ \
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e2k_ddmcr_t ddmcr; \
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\
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ddmcr.DDMCR_reg = NATIVE_READ_DDMCR_REG_VALUE(); \
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ddmcr; \
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})
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#define NATIVE_WRITE_DDBAR0_REG(value) \
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NATIVE_WRITE_DDBAR0_REG_VALUE(value)
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#define NATIVE_WRITE_DDBAR1_REG(value) \
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NATIVE_WRITE_DDBAR1_REG_VALUE(value)
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#define NATIVE_WRITE_DDBAR2_REG(value) \
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NATIVE_WRITE_DDBAR2_REG_VALUE(value)
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#define NATIVE_WRITE_DDBAR3_REG(value) \
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NATIVE_WRITE_DDBAR3_REG_VALUE(value)
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#define NATIVE_WRITE_DDBCR_REG(value) \
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NATIVE_WRITE_DDBCR_REG_VALUE(value.DDBCR_reg)
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#define NATIVE_WRITE_DDBSR_REG(value) \
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NATIVE_WRITE_DDBSR_REG_VALUE(value.DDBSR_reg)
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#define NATIVE_WRITE_DDMAR0_REG(value) \
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NATIVE_WRITE_DDMAR0_REG_VALUE(value)
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#define NATIVE_WRITE_DDMAR1_REG(value) \
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NATIVE_WRITE_DDMAR1_REG_VALUE(value)
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#define NATIVE_WRITE_DDMCR_REG(value) \
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NATIVE_WRITE_DDMCR_REG_VALUE(value.DDMCR_reg)
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#endif /* ! __ASSEMBLY__ */
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#endif /* _E2K_NATIVE_MMU_REGS_ACCESS_H_ */
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