295 lines
5.6 KiB
C
295 lines
5.6 KiB
C
#pragma once
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/* HC monitors */
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#define HC_MCR 0x360
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#define HC_MID 0x364
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#define HC_MAR0_LO 0x368
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#define HC_MAR0_HI 0x36c
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#define HC_MAR1_LO 0x370
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#define HC_MAR1_HI 0x374
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/* IOMMU monitors - all processors */
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#define IOMMU_MCR 0x3c0
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#define IOMMU_MID 0x3c4
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#define IOMMU_MAR0_LO 0x3c8
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#define IOMMU_MAR0_HI 0x3cc
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#define IOMMU_MAR1_LO 0x3d0
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#define IOMMU_MAR1_HI 0x3d4
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/* Additional IOMMU monitors - e2c3 only.
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* EDBC_IOMMU_* registers are used only to broadcast
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* writing into ED{26-31}_IOMMU_* registers. */
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#define EDBC_IOMMU_MCR 0x50c0
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#define EDBC_IOMMU_MID 0x50c4
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#define EDBC_IOMMU_MAR0_LO 0x50c8
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#define EDBC_IOMMU_MAR0_HI 0x50cc
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#define EDBC_IOMMU_MAR1_LO 0x50d0
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#define EDBC_IOMMU_MAR1_HI 0x50d4
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#define ED26_IOMMU_MCR 0x5d40
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#define ED26_IOMMU_MID 0x5d44
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#define ED26_IOMMU_MAR0_LO 0x5d48
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#define ED26_IOMMU_MAR0_HI 0x5d4c
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#define ED26_IOMMU_MAR1_LO 0x5d50
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#define ED26_IOMMU_MAR1_HI 0x5d54
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#define ED27_IOMMU_MCR 0x5dc0
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#define ED27_IOMMU_MID 0x5dc4
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#define ED27_IOMMU_MAR0_LO 0x5dc8
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#define ED27_IOMMU_MAR0_HI 0x5dcc
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#define ED27_IOMMU_MAR1_LO 0x5dd0
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#define ED27_IOMMU_MAR1_HI 0x5dd4
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#define ED28_IOMMU_MCR 0x5e40
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#define ED28_IOMMU_MID 0x5e44
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#define ED28_IOMMU_MAR0_LO 0x5e48
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#define ED28_IOMMU_MAR0_HI 0x5e4c
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#define ED28_IOMMU_MAR1_LO 0x5e50
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#define ED28_IOMMU_MAR1_HI 0x5e54
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#define ED29_IOMMU_MCR 0x5ec0
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#define ED29_IOMMU_MID 0x5ec4
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#define ED29_IOMMU_MAR0_LO 0x5ec8
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#define ED29_IOMMU_MAR0_HI 0x5ecc
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#define ED29_IOMMU_MAR1_LO 0x5ed0
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#define ED29_IOMMU_MAR1_HI 0x5ed4
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#define ED30_IOMMU_MCR 0x5f40
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#define ED30_IOMMU_MID 0x5f44
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#define ED30_IOMMU_MAR0_LO 0x5f48
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#define ED30_IOMMU_MAR0_HI 0x5f4c
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#define ED30_IOMMU_MAR1_LO 0x5f50
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#define ED30_IOMMU_MAR1_HI 0x5f54
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#define ED31_IOMMU_MCR 0x5fc0
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#define ED31_IOMMU_MID 0x5fc4
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#define ED31_IOMMU_MAR0_LO 0x5fc8
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#define ED31_IOMMU_MAR0_HI 0x5fcc
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#define ED31_IOMMU_MAR1_LO 0x5fd0
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#define ED31_IOMMU_MAR1_HI 0x5fd4
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/* MC monitors */
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#define MC_CH 0x400
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#define MC_STATUS 0x44c
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#define MC_MON_CTL 0x450
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#define MC_MON_CTR0 0x454
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#define MC_MON_CTR1 0x458
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#define MC_MON_CTRext 0x45c
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/* HMU monitors */
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#define HMU_MIC 0xd00
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#define HMU_MCR 0xd14
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#define HMU0_MAR0_LO 0xd44
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#define HMU0_MAR0_HI 0xd48
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#define HMU0_MAR1_LO 0xd4c
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#define HMU0_MAR1_HI 0xd50
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#define HMU1_MAR0_LO 0xd74
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#define HMU1_MAR0_HI 0xd78
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#define HMU1_MAR1_LO 0xd7c
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#define HMU1_MAR1_HI 0xd80
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#define HMU2_MAR0_LO 0xda4
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#define HMU2_MAR0_HI 0xda8
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#define HMU2_MAR1_LO 0xdac
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#define HMU2_MAR1_HI 0xdb0
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#define HMU3_MAR0_LO 0xdd4
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#define HMU3_MAR0_HI 0xdd8
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#define HMU3_MAR1_LO 0xddc
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#define HMU3_MAR1_HI 0xde0
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/* PREPIC monitors */
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#define PREPIC_MCR 0x8070
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#define PREPIC_MID 0x8074
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#define PREPIC_MAR0_LO 0x8080
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#define PREPIC_MAR0_HI 0x8084
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#define PREPIC_MAR1_LO 0x8090
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#define PREPIC_MAR1_HI 0x8094
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/*
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* HC monitor control register (HC_MCR)
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*/
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typedef union {
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struct {
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u32 v0 : 1;
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u32 __unused1 : 1;
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u32 es0 : 6;
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u32 v1 : 1;
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u32 __unused2 : 1;
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u32 es1 : 6;
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u32 __unused3 : 16;
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};
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u32 word;
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} e2k_hc_mcr_t;
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/*
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* HC monitor ID register (HC_MID)
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*/
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typedef union {
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struct {
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u32 id0 : 16;
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u32 id1 : 16;
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};
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u32 word;
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} e2k_hc_mid_t;
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/*
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* IOMMU monitor control register (IOMMU_MCR)
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*/
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typedef union {
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struct {
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u32 v0 : 1;
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u32 __unused1 : 1;
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u32 es0 : 6;
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u32 v1 : 1;
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u32 __unused2 : 1;
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u32 es1 : 6;
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u32 __unused3 : 16;
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};
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u32 word;
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} e2k_iommu_mcr_t;
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/*
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* IOMMU monitor ID register (IOMMU_MID)
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*/
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typedef union {
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struct {
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u32 id0 : 16;
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u32 id1 : 16;
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};
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u32 word;
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} e2k_iommu_mid_t;
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/*
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* MC status register (MC_STATUS)
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*/
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typedef union {
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struct {
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u32 ecc_err : 1;
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u32 ddrint_err : 1;
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u32 phyccm_par_err : 1;
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u32 dmem_par_err : 1;
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u32 bridge_par_err : 1;
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u32 phy_interrupt : 1;
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u32 phy_init_complete : 1;
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u32 dfi_par_err : 1;
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u32 meminit_finish : 1;
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u32 mon0_of : 1;
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u32 mon1_of : 1;
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u32 dfi_err : 1;
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u32 dfi_err_info : 1;
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u32 par_alert_delay : 6;
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u32 rst_done : 1;
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u32 wrcrc_aleert_delay : 6;
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u32 __unused : 6;
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};
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u32 word;
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} e2k_mc_status_t;
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/*
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* MC channel select register (MC_CH)
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*/
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typedef union {
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struct {
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u32 n : 4;
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u32 __unused : 28;
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};
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u32 word;
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} e2k_mc_ch_t;
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/*
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* MC monitor control register (MC_MON_CTL)
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*/
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typedef union {
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struct {
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u32 rst0 : 1;
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u32 rst1 : 1;
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u32 frz0 : 1;
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u32 frz1 : 1;
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u32 ld0 : 1;
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u32 ld1 : 1;
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u32 es0 : 5;
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u32 es1 : 5;
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u32 lb0 : 8;
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u32 lb1 : 8;
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};
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struct {
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u32 __pad : 16;
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u32 ba0 : 2;
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u32 bg0 : 2;
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u32 cid0 : 3;
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u32 all0 : 1;
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u32 ba1 : 2;
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u32 bg1 : 2;
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u32 cid1 : 3;
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u32 all1 : 1;
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};
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u32 word;
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} e2k_mc_mon_ctl_t;
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/*
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* MC monitor #0,1 counter high (MC_MON_CTRext)
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*/
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typedef union {
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u16 cnt[2];
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u32 word;
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} e2k_mc_mon_ctrext_t;
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/*
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* HMU memory interleaving control register (HMU_MIC)
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*/
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typedef union {
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struct {
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u32 mcil_bit0 : 6;
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u32 mcil_bit1 : 6;
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u32 mcil_bit2 : 6;
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u32 mcil_bit3 : 6;
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u32 mcen : 8;
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};
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u32 word;
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} e2k_hmu_mic_t;
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/*
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* HMU monitor control register (HMU_MCR)
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*/
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typedef union {
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struct {
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u32 v0 : 1;
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u32 __unused1 : 1;
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u32 es0 : 6;
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u32 v1 : 1;
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u32 __unused2 : 1;
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u32 es1 : 6;
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u32 flt0_off : 1;
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u32 flt0_rqid : 7;
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u32 flt0_cid : 1;
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u32 flt0_bid : 1;
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u32 flt0_xid : 1;
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u32 flt1_off : 1;
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u32 flt1_node : 2;
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u32 flt1_rnode : 1;
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u32 __unused3 : 1;
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};
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u32 word;
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} e2k_hmu_mcr_t;
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/*
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* PREPIC monitor control register (PREPIC_MCR)
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*/
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typedef union {
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struct {
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u32 vc0 : 1;
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u32 __unused1 : 1;
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u32 es0 : 6;
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u32 vc1 : 1;
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u32 __unused2 : 1;
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u32 es1 : 6;
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u32 __unused3 : 16;
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};
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u32 word;
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} e2k_prepic_mcr_t;
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/*
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* PREPIC monitor ID register (PREPIC_MID)
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*/
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typedef union {
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struct {
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u32 id0 : 16;
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u32 id1 : 16;
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};
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u32 word;
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} e2k_prepic_mid_t;
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