319 lines
9.8 KiB
C
319 lines
9.8 KiB
C
/*
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* asm-e2k/mmu_regs_access.h: E2K MMU structures & registers.
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*
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* Copyright 2014 Salavat S. Guiliazov (atic@mcst.ru)
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*/
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#ifndef _E2K_MMU_REGS_ACCESS_H_
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#define _E2K_MMU_REGS_ACCESS_H_
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <asm/e2k_api.h>
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#endif /* __ASSEMBLY__ */
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#include <asm/mmu_regs_types.h>
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#include <asm/mas.h>
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#include <asm/native_mmu_regs_access.h>
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extern unsigned long native_read_MMU_OS_PPTB_reg_value(void);
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extern void native_write_MMU_OS_PPTB_reg_value(unsigned long value);
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extern unsigned long native_read_MMU_OS_VPTB_reg_value(void);
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extern void native_write_MMU_OS_VPTB_reg_value(unsigned long value);
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extern unsigned long native_read_MMU_OS_VAB_reg_value(void);
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extern void native_write_MMU_OS_VAB_reg_value(unsigned long value);
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extern unsigned long boot_native_read_MMU_OS_PPTB_reg_value(void);
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extern void boot_native_write_MMU_OS_PPTB_reg_value(unsigned long value);
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extern unsigned long boot_native_read_MMU_OS_VPTB_reg_value(void);
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extern void boot_native_write_MMU_OS_VPTB_reg_value(unsigned long value);
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extern unsigned long boot_native_read_MMU_OS_VAB_reg_value(void);
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extern void boot_native_write_MMU_OS_VAB_reg_value(unsigned long value);
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#define NATIVE_WRITE_MMU_OS_PPTB_REG(reg_val) \
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native_write_MMU_OS_PPTB_reg_value(reg_val)
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#define NATIVE_READ_MMU_OS_PPTB_REG() \
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native_read_MMU_OS_PPTB_reg_value()
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#define NATIVE_WRITE_MMU_OS_VPTB_REG(reg_val) \
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native_write_MMU_OS_VPTB_reg_value(reg_val)
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#define NATIVE_READ_MMU_OS_VPTB_REG() \
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native_read_MMU_OS_VPTB_reg_value()
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#define NATIVE_WRITE_MMU_OS_VAB_REG(reg_val) \
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native_write_MMU_OS_VAB_reg_value(reg_val)
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#define NATIVE_READ_MMU_OS_VAB_REG() \
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native_read_MMU_OS_VAB_reg_value()
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#define NATIVE_READ_MMU_PID_REG() \
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NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_PID_NO))
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#define NATIVE_WRITE_MMU_PID_REG(reg_val) \
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NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_PID_NO), \
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mmu_reg_val(reg_val))
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#define NATIVE_READ_MMU_U_PPTB_REG() \
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NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_U_PPTB_NO))
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#define NATIVE_WRITE_MMU_U_PPTB_REG(reg_val) \
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NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_U_PPTB_NO), \
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mmu_reg_val(reg_val))
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#define NATIVE_READ_MMU_U_VPTB_REG() \
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NATIVE_READ_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_U_VPTB_NO))
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#define NATIVE_WRITE_MMU_U_VPTB_REG(reg_val) \
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NATIVE_WRITE_MMU_REG( \
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_MMU_REG_NO_TO_MMU_ADDR_VAL(_MMU_U_VPTB_NO), \
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mmu_reg_val(reg_val))
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#define BOOT_NATIVE_WRITE_MMU_OS_PPTB_REG(reg_val) \
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boot_native_write_MMU_OS_PPTB_reg_value(reg_val)
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#define BOOT_NATIVE_READ_MMU_OS_PPTB_REG() \
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boot_native_read_MMU_OS_PPTB_reg_value()
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#define BOOT_NATIVE_WRITE_MMU_OS_VPTB_REG(reg_val) \
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boot_native_write_MMU_OS_VPTB_reg_value(reg_val)
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#define BOOT_NATIVE_READ_MMU_OS_VPTB_REG() \
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boot_native_read_MMU_OS_VPTB_reg_value()
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#define BOOT_NATIVE_WRITE_MMU_OS_VAB_REG(reg_val) \
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boot_native_write_MMU_OS_VAB_reg_value(reg_val)
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#define BOOT_NATIVE_READ_MMU_OS_VAB_REG() \
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boot_native_read_MMU_OS_VAB_reg_value()
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#define BOOT_NATIVE_WRITE_MMU_PID_REG(reg_val) \
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NATIVE_WRITE_MMU_PID_REG(reg_val)
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#define BOOT_NATIVE_READ_MMU_PID_REG() \
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NATIVE_READ_MMU_PID_REG()
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#ifdef CONFIG_KVM_GUEST_KERNEL
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/* it is native guest kernel (not paravirtualized based on pv_ops) */
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#include <asm/kvm/mmu_regs_access.h>
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#elif defined(CONFIG_PARAVIRT_GUEST)
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/* it is paravirtualized host and guest kernel */
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#include <asm/paravirt/mmu_regs_access.h>
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#else /* ! CONFIG_KVM_GUEST_KERNEL && ! CONFIG_PARAVIRT_GUEST */
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/* it is native kernel without any virtualization */
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/* or host kernel with virtualization support */
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/*
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* MMU registers operations
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*/
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#ifndef __ASSEMBLY__
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/*
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* Write/read MMU register
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*/
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#define WRITE_MMU_REG(addr_val, reg_val) \
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NATIVE_WRITE_MMU_REG(addr_val, reg_val)
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#define READ_MMU_REG(addr_val) \
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NATIVE_READ_MMU_REG(addr_val)
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#define BOOT_WRITE_MMU_REG(addr_val, reg_val) \
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BOOT_NATIVE_WRITE_MMU_REG(addr_val, reg_val)
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#define BOOT_READ_MMU_REG(addr_val) \
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BOOT_NATIVE_READ_MMU_REG(addr_val)
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#define WRITE_MMU_OS_PPTB(reg_val) \
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NATIVE_WRITE_MMU_OS_PPTB_REG(reg_val)
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#define READ_MMU_OS_PPTB() \
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NATIVE_READ_MMU_OS_PPTB_REG()
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#define WRITE_MMU_OS_VPTB(reg_val) \
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NATIVE_WRITE_MMU_OS_VPTB_REG(reg_val)
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#define READ_MMU_OS_VPTB() \
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NATIVE_READ_MMU_OS_VPTB_REG()
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#define WRITE_MMU_OS_VAB(reg_val) \
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NATIVE_WRITE_MMU_OS_VAB_REG(reg_val)
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#define READ_MMU_OS_VAB() \
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NATIVE_READ_MMU_OS_VAB_REG()
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#define WRITE_MMU_PID(reg_val) \
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NATIVE_WRITE_MMU_PID_REG(reg_val)
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#define READ_MMU_PID() \
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NATIVE_READ_MMU_PID_REG()
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#define BOOT_WRITE_MMU_OS_PPTB(reg_val) \
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BOOT_NATIVE_WRITE_MMU_OS_PPTB_REG(reg_val)
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#define BOOT_READ_MMU_OS_PPTB() \
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BOOT_NATIVE_READ_MMU_OS_PPTB_REG()
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#define BOOT_WRITE_MMU_OS_VPTB(reg_val) \
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BOOT_NATIVE_WRITE_MMU_OS_VPTB_REG(reg_val)
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#define BOOT_READ_MMU_OS_VPTB() \
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BOOT_NATIVE_READ_MMU_OS_VPTB_REG()
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#define BOOT_WRITE_MMU_OS_VAB(reg_val) \
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BOOT_NATIVE_WRITE_MMU_OS_VAB_REG(reg_val)
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#define BOOT_READ_MMU_OS_VAB() \
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BOOT_NATIVE_READ_MMU_OS_VAB_REG()
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#define BOOT_WRITE_MMU_PID(reg_val) \
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BOOT_NATIVE_WRITE_MMU_PID_REG(reg_val)
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#define BOOT_READ_MMU_PID() \
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BOOT_NATIVE_READ_MMU_PID_REG()
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/*
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* Write/read Data TLB register
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*/
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#define WRITE_DTLB_REG(tlb_addr, tlb_value) \
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NATIVE_WRITE_DTLB_REG(tlb_addr, tlb_value)
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#define READ_DTLB_REG(tlb_addr) \
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NATIVE_READ_DTLB_REG(tlb_addr)
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/*
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* Flush TLB page/entry
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*/
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#define FLUSH_TLB_ENTRY(flush_op, addr) \
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NATIVE_FLUSH_TLB_ENTRY(flush_op, addr)
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/*
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* Flush DCACHE line
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*/
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#define FLUSH_DCACHE_LINE(virt_addr) \
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NATIVE_FLUSH_DCACHE_LINE(virt_addr)
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#define FLUSH_DCACHE_LINE_OFFSET(virt_addr, offset) \
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NATIVE_FLUSH_DCACHE_LINE_OFFSET((virt_addr), (offset))
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/*
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* Clear DCACHE L1 set
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*/
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#define CLEAR_DCACHE_L1_SET(virt_addr, set) \
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NATIVE_CLEAR_DCACHE_L1_SET(virt_addr, set)
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/*
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* Write DCACHE L2 registers
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*/
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#define WRITE_L2_REG(reg_val, reg_num, bank_num) \
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NATIVE_WRITE_L2_REG(reg_val, reg_num, bank_num)
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/*
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* Read DCACHE L2 registers
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*/
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#define READ_L2_REG(reg_num, bank_num) \
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NATIVE_READ_L2_REG(reg_num, bank_num)
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/*
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* Flush ICACHE line
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*/
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#define FLUSH_ICACHE_LINE(flush_op, addr) \
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NATIVE_FLUSH_ICACHE_LINE(flush_op, addr)
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/*
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* Flush and invalidate or write back L1/L2 CACHE(s)
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*/
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#define FLUSH_CACHE_L12(flush_op) \
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native_write_back_CACHE_L12()
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/*
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* Flush TLB (invalidate all TLBs of the processor)
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*/
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#define FLUSH_TLB_ALL(flush_op) \
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native_flush_TLB_all()
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/*
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* Flush ICACHE (invalidate instruction caches of the processor)
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*/
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#define FLUSH_ICACHE_ALL(flush_op) \
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native_flush_ICACHE_all()
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/*
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* Get Entry probe for virtual address
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*/
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#define ENTRY_PROBE_MMU_OP(addr_val) \
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NATIVE_ENTRY_PROBE_MMU_OP(addr_val)
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/*
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* Get physical address for virtual address
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*/
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#define ADDRESS_PROBE_MMU_OP(addr_val) \
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NATIVE_ADDRESS_PROBE_MMU_OP(addr_val)
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/*
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* Read CLW register
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*/
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#define READ_CLW_REG(clw_addr) \
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NATIVE_READ_CLW_REG(clw_addr)
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/*
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* Write CLW register
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*/
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#define WRITE_CLW_REG(clw_addr, val) \
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NATIVE_WRITE_CLW_REG(clw_addr, val)
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/*
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* MMU DEBUG registers access
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*/
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#define READ_DDBAR0_REG_VALUE() NATIVE_READ_DDBAR0_REG_VALUE()
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#define READ_DDBAR1_REG_VALUE() NATIVE_READ_DDBAR1_REG_VALUE()
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#define READ_DDBAR2_REG_VALUE() NATIVE_READ_DDBAR2_REG_VALUE()
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#define READ_DDBAR3_REG_VALUE() NATIVE_READ_DDBAR3_REG_VALUE()
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#define READ_DDBCR_REG_VALUE() NATIVE_READ_DDBCR_REG_VALUE()
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#define READ_DDBSR_REG_VALUE() NATIVE_READ_DDBSR_REG_VALUE()
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#define READ_DDMAR0_REG_VALUE() NATIVE_READ_DDMAR0_REG_VALUE()
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#define READ_DDMAR1_REG_VALUE() NATIVE_READ_DDMAR1_REG_VALUE()
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#define READ_DDMCR_REG_VALUE() NATIVE_READ_DDMCR_REG_VALUE()
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#define WRITE_DDBAR0_REG_VALUE(value) NATIVE_WRITE_DDBAR0_REG_VALUE(value)
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#define WRITE_DDBAR1_REG_VALUE(value) NATIVE_WRITE_DDBAR1_REG_VALUE(value)
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#define WRITE_DDBAR2_REG_VALUE(value) NATIVE_WRITE_DDBAR2_REG_VALUE(value)
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#define WRITE_DDBAR3_REG_VALUE(value) NATIVE_WRITE_DDBAR3_REG_VALUE(value)
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#define WRITE_DDBCR_REG_VALUE(value) NATIVE_WRITE_DDBCR_REG_VALUE(value)
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#define WRITE_DDBSR_REG_VALUE(value) NATIVE_WRITE_DDBSR_REG_VALUE(value)
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#define WRITE_DDMAR0_REG_VALUE(value) NATIVE_WRITE_DDMAR0_REG_VALUE(value)
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#define WRITE_DDMAR1_REG_VALUE(value) NATIVE_WRITE_DDMAR1_REG_VALUE(value)
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#define WRITE_DDMCR_REG_VALUE(value) NATIVE_WRITE_DDMCR_REG_VALUE(value)
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#endif /* ! __ASSEMBLY__ */
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#endif /* CONFIG_KVM_GUEST_KERNEL */
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#ifndef __ASSEMBLY__
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#define READ_DDBAR0_REG() \
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READ_DDBAR0_REG_VALUE()
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#define READ_DDBAR1_REG() \
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READ_DDBAR1_REG_VALUE()
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#define READ_DDBAR2_REG() \
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READ_DDBAR2_REG_VALUE()
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#define READ_DDBAR3_REG() \
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READ_DDBAR3_REG_VALUE()
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#define READ_DDBCR_REG() \
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({ \
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e2k_ddbcr_t ddbcr; \
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\
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ddbcr.DDBCR_reg = READ_DDBCR_REG_VALUE(); \
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ddbcr; \
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})
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#define READ_DDBSR_REG() \
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({ \
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e2k_ddbsr_t ddbsr; \
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\
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ddbsr.DDBSR_reg = READ_DDBSR_REG_VALUE(); \
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ddbsr; \
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})
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#define READ_DDMAR0_REG() \
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READ_DDMAR0_REG_VALUE()
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#define READ_DDMAR1_REG() \
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READ_DDMAR1_REG_VALUE()
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#define READ_DDMCR_REG() \
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({ \
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e2k_ddmcr_t ddmcr; \
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\
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ddmcr.DDMCR_reg = READ_DDMCR_REG_VALUE(); \
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ddmcr; \
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})
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#define WRITE_DDBAR0_REG(value) \
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WRITE_DDBAR0_REG_VALUE(value)
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#define WRITE_DDBAR1_REG(value) \
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WRITE_DDBAR1_REG_VALUE(value)
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#define WRITE_DDBAR2_REG(value) \
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WRITE_DDBAR2_REG_VALUE(value)
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#define WRITE_DDBAR3_REG(value) \
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WRITE_DDBAR3_REG_VALUE(value)
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#define WRITE_DDBCR_REG(value) \
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WRITE_DDBCR_REG_VALUE(value.DDBCR_reg)
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#define WRITE_DDBSR_REG(value) \
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WRITE_DDBSR_REG_VALUE(value.DDBSR_reg)
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#define WRITE_DDMAR0_REG(value) \
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WRITE_DDMAR0_REG_VALUE(value)
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#define WRITE_DDMAR1_REG(value) \
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WRITE_DDMAR1_REG_VALUE(value)
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#define WRITE_DDMCR_REG(value) \
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WRITE_DDMCR_REG_VALUE(value.DDMCR_reg)
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#endif /* ! __ASSEMBLY__ */
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#endif /* _E2K_MMU_REGS_ACCESS_H_ */
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