652 lines
13 KiB
C
652 lines
13 KiB
C
/*
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* E2K MMU registers access paravirtualization
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*
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* Copyright 2017 Salavat S. Guiliazov (atic@mcst.ru)
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*/
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#ifndef _E2K_PARAVIRT_MMU_REGS_ACCESS_H_
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#define _E2K_PARAVIRT_MMU_REGS_ACCESS_H_
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <asm/paravirt/pv_ops.h>
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/*
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* Write/read MMU register
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*/
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#ifdef CONFIG_KVM_GUEST
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#include <asm/kvm/mmu_regs_access.h>
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static inline void
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PV_WRITE_MMU_REG(mmu_addr_t mmu_addr, mmu_reg_t mmu_reg)
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{
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pv_mmu_ops.write_mmu_reg(mmu_addr, mmu_reg);
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}
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static inline mmu_reg_t
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PV_READ_MMU_REG(mmu_addr_t mmu_addr)
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{
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return pv_mmu_ops.read_mmu_reg(mmu_addr);
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}
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static inline void PV_WRITE_MMU_OS_PPTB_REG(mmu_reg_t reg_val)
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{
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PV_WRITE_MMU_REG(MMU_ADDR_OS_PPTB, reg_val);
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}
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static inline unsigned long PV_READ_MMU_OS_PPTB_REG(void)
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{
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return mmu_reg_val(PV_READ_MMU_REG(MMU_ADDR_OS_PPTB));
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}
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static inline void PV_WRITE_MMU_OS_VPTB_REG(mmu_reg_t reg_val)
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{
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PV_WRITE_MMU_REG(MMU_ADDR_OS_VPTB, reg_val);
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}
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static inline unsigned long PV_READ_MMU_OS_VPTB_REG(void)
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{
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return mmu_reg_val(PV_READ_MMU_REG(MMU_ADDR_OS_VPTB));
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}
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static inline void PV_WRITE_MMU_OS_VAB_REG(mmu_reg_t reg_val)
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{
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PV_WRITE_MMU_REG(MMU_ADDR_OS_VAB, reg_val);
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}
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static inline unsigned long PV_READ_MMU_OS_VAB_REG(void)
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{
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return mmu_reg_val(PV_READ_MMU_REG(MMU_ADDR_OS_VAB));
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}
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static inline void
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BOOT_PV_WRITE_MMU_REG(mmu_addr_t mmu_addr, mmu_reg_t mmu_reg)
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{
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BOOT_PARAVIRT_WRITE_MMU_REG(mmu_addr, mmu_reg);
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}
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static inline mmu_reg_t
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BOOT_PV_READ_MMU_REG(mmu_addr_t mmu_addr)
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{
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return BOOT_PARAVIRT_READ_MMU_REG(mmu_addr);
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}
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static inline void BOOT_PV_WRITE_MMU_OS_PPTB_REG(mmu_reg_t reg_val)
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{
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BOOT_PV_WRITE_MMU_REG(MMU_ADDR_OS_PPTB, reg_val);
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}
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static inline unsigned long BOOT_PV_READ_MMU_OS_PPTB_REG(void)
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{
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return mmu_reg_val(BOOT_PV_READ_MMU_REG(MMU_ADDR_OS_PPTB));
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}
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static inline void BOOT_PV_WRITE_MMU_OS_VPTB_REG(mmu_reg_t reg_val)
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{
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BOOT_PV_WRITE_MMU_REG(MMU_ADDR_OS_VPTB, reg_val);
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}
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static inline unsigned long BOOT_PV_READ_MMU_OS_VPTB_REG(void)
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{
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return mmu_reg_val(BOOT_PV_READ_MMU_REG(MMU_ADDR_OS_VPTB));
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}
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static inline void BOOT_PV_WRITE_MMU_OS_VAB_REG(mmu_reg_t reg_val)
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{
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BOOT_PV_WRITE_MMU_REG(MMU_ADDR_OS_VAB, reg_val);
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}
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static inline unsigned long BOOT_PV_READ_MMU_OS_VAB_REG(void)
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{
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return mmu_reg_val(BOOT_PV_READ_MMU_REG(MMU_ADDR_OS_VAB));
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}
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/*
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* Write/read Data TLB register
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*/
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static inline void
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PV_WRITE_DTLB_REG(tlb_addr_t tlb_addr, mmu_reg_t mmu_reg)
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{
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pv_mmu_ops.write_dtlb_reg(tlb_addr, mmu_reg);
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}
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static inline mmu_reg_t
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PV_READ_DTLB_REG(tlb_addr_t tlb_addr)
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{
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return pv_mmu_ops.read_dtlb_reg(tlb_addr);
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}
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/*
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* Flush TLB page/entry
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*/
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static inline void
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PV_FLUSH_TLB_ENTRY(flush_op_t flush_op, flush_addr_t flush_addr)
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{
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pv_mmu_ops.flush_tlb_entry(flush_op, flush_addr);
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}
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/*
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* Flush DCACHE line
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*/
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static inline void
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PV_FLUSH_DCACHE_LINE(e2k_addr_t virt_addr)
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{
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pv_mmu_ops.flush_dcache_line(virt_addr);
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}
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/*
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* Clear DCACHE L1 set
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*/
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static inline void
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PV_CLEAR_DCACHE_L1_SET(e2k_addr_t virt_addr, unsigned long set)
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{
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pv_mmu_ops.clear_dcache_l1_set(virt_addr, set);
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}
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/*
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* Write/read DCACHE L2 registers
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*/
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static inline void
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PV_WRITE_L2_REG(unsigned long reg_val, int reg_num, int bank_num)
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{
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pv_mmu_ops.write_dcache_l2_reg(reg_val, reg_num, bank_num);
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}
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static inline unsigned long
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PV_READ_L2_REG(int reg_num, int bank_num)
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{
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return pv_mmu_ops.read_dcache_l2_reg(reg_num, bank_num);
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}
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/*
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* Flush ICACHE line
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*/
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static inline void
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PV_FLUSH_ICACHE_LINE(flush_op_t flush_op, flush_addr_t flush_addr)
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{
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pv_mmu_ops.flush_icache_line(flush_op, flush_addr);
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}
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/*
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* Flush and invalidate or write back CACHE(s) (invalidate all caches
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* of the processor)
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*/
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static inline void
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PV_FLUSH_CACHE_L12(flush_op_t flush_op)
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{
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pv_mmu_ops.flush_cache_all(flush_op);
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}
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/*
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* Flush TLB (invalidate all TLBs of the processor)
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*/
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static inline void
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PV_FLUSH_TLB_ALL(flush_op_t flush_op)
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{
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pv_mmu_ops.do_flush_tlb_all(flush_op);
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}
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/*
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* Flush ICACHE (invalidate instruction caches of the processor)
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*/
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static inline void
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PV_FLUSH_ICACHE_ALL(flush_op_t flush_op)
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{
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pv_mmu_ops.flush_icache_all(flush_op);
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}
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/*
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* Get Entry probe for virtual address
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*/
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static inline probe_entry_t
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PV_ENTRY_PROBE_MMU_OP(e2k_addr_t virt_addr)
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{
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return pv_mmu_ops.entry_probe_mmu_op(virt_addr);
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}
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/*
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* Get physical address for virtual address
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*/
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static inline probe_entry_t
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PV_ADDRESS_PROBE_MMU_OP(e2k_addr_t virt_addr)
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{
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return pv_mmu_ops.address_probe_mmu_op(virt_addr);
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}
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/*
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* Read CLW register
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*/
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static inline clw_reg_t
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PV_READ_CLW_REG(clw_addr_t clw_addr)
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{
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return pv_mmu_ops.read_clw_reg(clw_addr);
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}
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/*
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* Write CLW register
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*/
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static inline void
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PV_WRITE_CLW_REG(clw_addr_t clw_addr, clw_reg_t val)
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{
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pv_mmu_ops.write_clw_reg(clw_addr, val);
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}
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/*
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* MMU DEBUG registers access
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*/
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static inline void
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PV_WRITE_MMU_DEBUG_REG_VALUE(int reg_no, mmu_reg_t mmu_reg)
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{
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pv_mmu_ops.write_mmu_debug_reg(reg_no, mmu_reg);
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}
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static inline mmu_reg_t
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PV_READ_MMU_DEBUG_REG_VALUE(int reg_no)
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{
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return pv_mmu_ops.read_mmu_debug_reg(reg_no);
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}
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static inline mmu_reg_t
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PV_READ_DDBAR0_REG_VALUE(void)
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{
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return PV_READ_MMU_DEBUG_REG_VALUE(MMU_DDBAR0_REG_NO);
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}
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static inline mmu_reg_t
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PV_READ_DDBAR1_REG_VALUE(void)
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{
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return PV_READ_MMU_DEBUG_REG_VALUE(MMU_DDBAR1_REG_NO);
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}
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static inline mmu_reg_t
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PV_READ_DDBAR2_REG_VALUE(void)
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{
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return PV_READ_MMU_DEBUG_REG_VALUE(MMU_DDBAR2_REG_NO);
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}
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static inline mmu_reg_t
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PV_READ_DDBAR3_REG_VALUE(void)
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{
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return PV_READ_MMU_DEBUG_REG_VALUE(MMU_DDBAR3_REG_NO);
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}
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static inline mmu_reg_t
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PV_READ_DDBCR_REG_VALUE(void)
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{
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return PV_READ_MMU_DEBUG_REG_VALUE(MMU_DDBCR_REG_NO);
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}
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static inline mmu_reg_t
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PV_READ_DDBSR_REG_VALUE(void)
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{
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return PV_READ_MMU_DEBUG_REG_VALUE(MMU_DDBSR_REG_NO);
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}
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static inline mmu_reg_t
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PV_READ_DDMAR0_REG_VALUE(void)
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{
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return PV_READ_MMU_DEBUG_REG_VALUE(MMU_DDMAR0_REG_NO);
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}
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static inline mmu_reg_t
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PV_READ_DDMAR1_REG_VALUE(void)
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{
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return PV_READ_MMU_DEBUG_REG_VALUE(MMU_DDMAR1_REG_NO);
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}
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static inline mmu_reg_t
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PV_READ_DDMCR_REG_VALUE(void)
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{
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return PV_READ_MMU_DEBUG_REG_VALUE(MMU_DDMCR_REG_NO);
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}
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static inline void
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PV_WRITE_DDBAR0_REG_VALUE(mmu_reg_t mmu_reg)
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{
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PV_WRITE_MMU_DEBUG_REG_VALUE(MMU_DDBAR0_REG_NO, mmu_reg);
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}
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static inline void
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PV_WRITE_DDBAR1_REG_VALUE(mmu_reg_t mmu_reg)
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{
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PV_WRITE_MMU_DEBUG_REG_VALUE(MMU_DDBAR1_REG_NO, mmu_reg);
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}
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static inline void
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PV_WRITE_DDBAR2_REG_VALUE(mmu_reg_t mmu_reg)
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{
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PV_WRITE_MMU_DEBUG_REG_VALUE(MMU_DDBAR2_REG_NO, mmu_reg);
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}
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static inline void
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PV_WRITE_DDBAR3_REG_VALUE(mmu_reg_t mmu_reg)
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{
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PV_WRITE_MMU_DEBUG_REG_VALUE(MMU_DDBAR3_REG_NO, mmu_reg);
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}
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static inline void
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PV_WRITE_DDBCR_REG_VALUE(mmu_reg_t mmu_reg)
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{
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PV_WRITE_MMU_DEBUG_REG_VALUE(MMU_DDBCR_REG_NO, mmu_reg);
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}
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static inline void
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PV_WRITE_DDBSR_REG_VALUE(mmu_reg_t mmu_reg)
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{
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PV_WRITE_MMU_DEBUG_REG_VALUE(MMU_DDBSR_REG_NO, mmu_reg);
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}
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static inline void
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PV_WRITE_DDMAR0_REG_VALUE(mmu_reg_t mmu_reg)
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{
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PV_WRITE_MMU_DEBUG_REG_VALUE(MMU_DDMAR0_REG_NO, mmu_reg);
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}
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static inline void
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PV_WRITE_DDMAR1_REG_VALUE(mmu_reg_t mmu_reg)
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{
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PV_WRITE_MMU_DEBUG_REG_VALUE(MMU_DDMAR1_REG_NO, mmu_reg);
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}
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static inline void
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PV_WRITE_DDMCR_REG_VALUE(mmu_reg_t mmu_reg)
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{
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PV_WRITE_MMU_DEBUG_REG_VALUE(MMU_DDMCR_REG_NO, mmu_reg);
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}
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#else /* ! CONFIG_KVM_GUEST */
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#error "Unknown virtualization type"
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#endif /* CONFIG_KVM_GUEST */
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#ifdef CONFIG_PARAVIRT_GUEST
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/* It is paravirtualized host and guest kernel */
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static inline void WRITE_MMU_REG(mmu_addr_t mmu_addr, mmu_reg_t mmu_reg)
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{
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PV_WRITE_MMU_REG(mmu_addr, mmu_reg);
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}
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static inline mmu_reg_t READ_MMU_REG(mmu_addr_t mmu_addr)
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{
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return (mmu_reg_t)PV_READ_MMU_REG(mmu_addr);
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}
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static inline void WRITE_MMU_OS_PPTB(mmu_reg_t reg_val)
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{
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PV_WRITE_MMU_OS_PPTB_REG(reg_val);
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}
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static inline unsigned long READ_MMU_OS_PPTB(void)
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{
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return PV_READ_MMU_OS_PPTB_REG();
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}
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static inline void WRITE_MMU_OS_VPTB(mmu_reg_t reg_val)
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{
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PV_WRITE_MMU_OS_VPTB_REG(reg_val);
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}
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static inline unsigned long READ_MMU_OS_VPTB(void)
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{
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return PV_READ_MMU_OS_VPTB_REG();
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}
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static inline void WRITE_MMU_OS_VAB(mmu_reg_t reg_val)
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{
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PV_WRITE_MMU_OS_VAB_REG(reg_val);
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}
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static inline unsigned long READ_MMU_OS_VAB(void)
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{
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return PV_READ_MMU_OS_VAB_REG();
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}
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static inline void
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BOOT_WRITE_MMU_REG(mmu_addr_t mmu_addr, mmu_reg_t mmu_reg)
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{
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BOOT_PV_WRITE_MMU_REG(mmu_addr, mmu_reg);
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}
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static inline mmu_reg_t
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BOOT_READ_MMU_REG(mmu_addr_t mmu_addr)
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{
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return BOOT_PV_READ_MMU_REG(mmu_addr);
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}
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static inline void BOOT_WRITE_MMU_OS_PPTB(mmu_reg_t reg_val)
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{
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BOOT_PV_WRITE_MMU_OS_PPTB_REG(reg_val);
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}
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static inline unsigned long BOOT_READ_MMU_OS_PPTB(void)
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{
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return BOOT_PV_READ_MMU_OS_PPTB_REG();
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}
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static inline void BOOT_WRITE_MMU_OS_VPTB(mmu_reg_t reg_val)
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{
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BOOT_PV_WRITE_MMU_OS_VPTB_REG(reg_val);
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}
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static inline unsigned long BOOT_READ_MMU_OS_VPTB(void)
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{
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return BOOT_PV_READ_MMU_OS_VPTB_REG();
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}
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static inline void BOOT_WRITE_MMU_OS_VAB(mmu_reg_t reg_val)
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{
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BOOT_PV_WRITE_MMU_OS_VAB_REG(reg_val);
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}
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static inline unsigned long BOOT_READ_MMU_OS_VAB(void)
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{
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return BOOT_PV_READ_MMU_OS_VAB_REG();
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}
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/*
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* Write/read Data TLB register
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*/
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static inline void
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WRITE_DTLB_REG(tlb_addr_t tlb_addr, mmu_reg_t mmu_reg)
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{
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PV_WRITE_DTLB_REG(tlb_addr, mmu_reg);
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}
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static inline mmu_reg_t
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READ_DTLB_REG(tlb_addr_t tlb_addr)
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{
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return PV_READ_DTLB_REG(tlb_addr);
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}
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/*
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* Flush TLB page/entry
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*/
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static inline void
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FLUSH_TLB_ENTRY(flush_op_t flush_op, flush_addr_t flush_addr)
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{
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PV_FLUSH_TLB_ENTRY(flush_op, flush_addr);
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}
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/*
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* Flush DCACHE line
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*/
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static inline void FLUSH_DCACHE_LINE(e2k_addr_t virt_addr)
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{
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PV_FLUSH_DCACHE_LINE(virt_addr);
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}
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static inline void FLUSH_DCACHE_LINE_OFFSET(e2k_addr_t virt_addr, size_t offset)
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{
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PV_FLUSH_DCACHE_LINE(virt_addr + offset);
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}
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/*
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* Clear DCACHE L1 set
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*/
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static inline void
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CLEAR_DCACHE_L1_SET(e2k_addr_t virt_addr, unsigned long set)
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{
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PV_CLEAR_DCACHE_L1_SET(virt_addr, set);
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}
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/*
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* Write/read DCACHE L2 registers
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*/
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static inline void
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WRITE_L2_REG(unsigned long reg_val, int reg_num, int bank_num)
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{
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PV_WRITE_L2_REG(reg_val, reg_num, bank_num);
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}
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static inline unsigned long
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READ_L2_REG(int reg_num, int bank_num)
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{
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return PV_READ_L2_REG(reg_num, bank_num);
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}
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/*
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* Flush ICACHE line
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*/
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static inline void
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FLUSH_ICACHE_LINE(flush_op_t flush_op, flush_addr_t flush_addr)
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{
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PV_FLUSH_ICACHE_LINE(flush_op, flush_addr);
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}
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/*
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* Flush and invalidate or write back CACHE(s) (invalidate all caches
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* of the processor)
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*/
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static inline void
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FLUSH_CACHE_L12(flush_op_t flush_op)
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{
|
|
PV_FLUSH_CACHE_L12(flush_op);
|
|
}
|
|
|
|
/*
|
|
* Flush TLB (invalidate all TLBs of the processor)
|
|
*/
|
|
|
|
static inline void
|
|
FLUSH_TLB_ALL(flush_op_t flush_op)
|
|
{
|
|
PV_FLUSH_TLB_ALL(flush_op);
|
|
}
|
|
|
|
/*
|
|
* Flush ICACHE (invalidate instruction caches of the processor)
|
|
*/
|
|
|
|
static inline void
|
|
FLUSH_ICACHE_ALL(flush_op_t flush_op)
|
|
{
|
|
PV_FLUSH_ICACHE_ALL(flush_op);
|
|
}
|
|
|
|
/*
|
|
* Get Entry probe for virtual address
|
|
*/
|
|
|
|
static inline probe_entry_t
|
|
ENTRY_PROBE_MMU_OP(e2k_addr_t virt_addr)
|
|
{
|
|
return PV_ENTRY_PROBE_MMU_OP(virt_addr);
|
|
}
|
|
|
|
/*
|
|
* Get physical address for virtual address
|
|
*/
|
|
|
|
static inline probe_entry_t
|
|
ADDRESS_PROBE_MMU_OP(e2k_addr_t virt_addr)
|
|
{
|
|
return PV_ADDRESS_PROBE_MMU_OP(virt_addr);
|
|
}
|
|
|
|
/*
|
|
* Read CLW register
|
|
*/
|
|
|
|
static inline clw_reg_t
|
|
READ_CLW_REG(clw_addr_t clw_addr)
|
|
{
|
|
return PV_READ_CLW_REG(clw_addr);
|
|
}
|
|
|
|
/*
|
|
* Write CLW register
|
|
*/
|
|
|
|
static inline void
|
|
WRITE_CLW_REG(clw_addr_t clw_addr, clw_reg_t val)
|
|
{
|
|
PV_WRITE_CLW_REG(clw_addr, val);
|
|
}
|
|
|
|
/*
|
|
* KVM MMU DEBUG registers access
|
|
*/
|
|
static inline mmu_reg_t
|
|
READ_DDBAR0_REG_VALUE(void)
|
|
{
|
|
return PV_READ_DDBAR0_REG_VALUE();
|
|
}
|
|
static inline mmu_reg_t
|
|
READ_DDBAR1_REG_VALUE(void)
|
|
{
|
|
return PV_READ_DDBAR1_REG_VALUE();
|
|
}
|
|
static inline mmu_reg_t
|
|
READ_DDBAR2_REG_VALUE(void)
|
|
{
|
|
return PV_READ_DDBAR2_REG_VALUE();
|
|
}
|
|
static inline mmu_reg_t
|
|
READ_DDBAR3_REG_VALUE(void)
|
|
{
|
|
return PV_READ_DDBAR3_REG_VALUE();
|
|
}
|
|
static inline mmu_reg_t
|
|
READ_DDBCR_REG_VALUE(void)
|
|
{
|
|
return PV_READ_DDBCR_REG_VALUE();
|
|
}
|
|
static inline mmu_reg_t
|
|
READ_DDBSR_REG_VALUE(void)
|
|
{
|
|
return PV_READ_DDBSR_REG_VALUE();
|
|
}
|
|
static inline mmu_reg_t
|
|
READ_DDMAR0_REG_VALUE(void)
|
|
{
|
|
return PV_READ_DDMAR0_REG_VALUE();
|
|
}
|
|
static inline mmu_reg_t
|
|
READ_DDMAR1_REG_VALUE(void)
|
|
{
|
|
return PV_READ_DDMAR1_REG_VALUE();
|
|
}
|
|
static inline mmu_reg_t
|
|
READ_DDMCR_REG_VALUE(void)
|
|
{
|
|
return PV_READ_DDMCR_REG_VALUE();
|
|
}
|
|
static inline void
|
|
WRITE_DDBAR0_REG_VALUE(mmu_reg_t value)
|
|
{
|
|
PV_WRITE_DDBAR0_REG_VALUE(value);
|
|
}
|
|
static inline void
|
|
WRITE_DDBAR1_REG_VALUE(mmu_reg_t value)
|
|
{
|
|
PV_WRITE_DDBAR1_REG_VALUE(value);
|
|
}
|
|
static inline void
|
|
WRITE_DDBAR2_REG_VALUE(mmu_reg_t value)
|
|
{
|
|
PV_WRITE_DDBAR2_REG_VALUE(value);
|
|
}
|
|
static inline void
|
|
WRITE_DDBAR3_REG_VALUE(mmu_reg_t value)
|
|
{
|
|
PV_WRITE_DDBAR3_REG_VALUE(value);
|
|
}
|
|
static inline void
|
|
WRITE_DDBCR_REG_VALUE(mmu_reg_t value)
|
|
{
|
|
PV_WRITE_DDBCR_REG_VALUE(value);
|
|
}
|
|
static inline void
|
|
WRITE_DDBSR_REG_VALUE(mmu_reg_t value)
|
|
{
|
|
PV_WRITE_DDBSR_REG_VALUE(value);
|
|
}
|
|
static inline void
|
|
WRITE_DDMAR0_REG_VALUE(mmu_reg_t value)
|
|
{
|
|
PV_WRITE_DDMAR0_REG_VALUE(value);
|
|
}
|
|
static inline void
|
|
WRITE_DDMAR1_REG_VALUE(mmu_reg_t value)
|
|
{
|
|
PV_WRITE_DDMAR1_REG_VALUE(value);
|
|
}
|
|
static inline void
|
|
WRITE_DDMCR_REG_VALUE(mmu_reg_t value)
|
|
{
|
|
PV_WRITE_DDMCR_REG_VALUE(value);
|
|
}
|
|
|
|
#endif /* CONFIG_PARAVIRT_GUEST */
|
|
|
|
#endif /* ! __ASSEMBLY__ */
|
|
|
|
#endif /* _E2K_PARAVIRT_MMU_REGS_ACCESS_H_ */
|