2005-04-17 00:20:36 +02:00
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#ifndef _ASM_M32R_ASSEMBLER_H
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#define _ASM_M32R_ASSEMBLER_H
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/*
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* linux/asm-m32r/assembler.h
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*
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* Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
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*
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* This file contains M32R architecture specific macro definitions.
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*/
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#ifndef __STR
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#ifdef __ASSEMBLY__
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#define __STR(x) x
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#else
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#define __STR(x) #x
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#endif
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#endif /* __STR */
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#ifdef CONFIG_SMP
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#define M32R_LOCK __STR(lock)
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#define M32R_UNLOCK __STR(unlock)
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#else
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#define M32R_LOCK __STR(ld)
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#define M32R_UNLOCK __STR(st)
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#endif
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#ifdef __ASSEMBLY__
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#undef ENTRY
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#define ENTRY(name) ENTRY_M name
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.macro ENTRY_M name
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.global \name
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ALIGN
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\name:
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.endm
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#endif
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/**
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* LDIMM - load immediate value
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* STI - enable interruption
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* CLI - disable interruption
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*/
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#ifdef __ASSEMBLY__
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#define LDIMM(reg,x) LDIMM reg x
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.macro LDIMM reg x
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seth \reg, #high(\x)
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or3 \reg, \reg, #low(\x)
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.endm
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2006-01-06 09:18:41 +01:00
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#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
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2007-08-20 13:53:50 +02:00
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#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
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.macro ENABLE_INTERRUPTS reg
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2005-04-17 00:20:36 +02:00
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setpsw #0x40 -> nop
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; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
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.endm
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2007-08-20 13:53:50 +02:00
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#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
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.macro DISABLE_INTERRUPTS reg
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2005-04-17 00:20:36 +02:00
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clrpsw #0x40 -> nop
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; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
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.endm
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2006-01-06 09:18:41 +01:00
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#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
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2007-08-20 13:53:50 +02:00
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#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
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.macro ENABLE_INTERRUPTS reg
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2005-04-17 00:20:36 +02:00
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mvfc \reg, psw
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or3 \reg, \reg, #0x0040
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mvtc \reg, psw
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.endm
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2007-08-20 13:53:50 +02:00
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#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
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.macro DISABLE_INTERRUPTS reg
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2005-04-17 00:20:36 +02:00
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mvfc \reg, psw
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and3 \reg, \reg, #0xffbf
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mvtc \reg, psw
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.endm
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#endif /* CONFIG_CHIP_M32102 */
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.macro SAVE_ALL
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push r0 ; orig_r0
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push sp ; spi (r15)
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push lr ; r14
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push r13
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mvfc r13, cr3 ; spu
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push r13
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mvfc r13, bbpc
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push r13
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mvfc r13, bbpsw
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push r13
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mvfc r13, bpc
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push r13
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mvfc r13, psw
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push r13
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#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
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mvfaclo r13, a1
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push r13
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mvfachi r13, a1
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push r13
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mvfaclo r13, a0
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push r13
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mvfachi r13, a0
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push r13
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#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
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mvfaclo r13
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push r13
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mvfachi r13
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push r13
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[PATCH] m32r: Fix pt_regs for !COFNIG_ISA_DSP_LEVEL2 target
This modification is required to fix debugging function for m32r targets
with !CONFIG_ISA_DSP_LEVEL2, by unifying 'struct pt_regs' and 'struct
sigcontext' size for all M32R ISA.
Some m32r processor core with !CONFIG_ISA_DSP_LEVEL2 configuration has only
single accumulator a0 (ex. VDEC2 core, M32102 core, etc.), the others with
CONFIG_ISA_DSP_LEVEL2 has two accumulators, a0 and a1.
This means there are two variations of thread context. So far, we reduced
and changed stackframe size at a syscall for their context size. However,
this causes a problem that a GDB for processors with CONFIG_ISA_DSP_LEVEL2
cannot be used for processors with !CONFIG_ISA_DSP_LEVEL2.
From the viewpoint of GDB support, we should reduce such variation of
stackframe size for simplicity.
In this patch, dummy members are added to 'struct pt_regs' and 'struct
sigcontext' to adjust their size for !CONFIG_ISA_DSP_LEVEL2.
This modification is also a one step for a GDB update in future.
Currently, on the m32r, GDB can access process's context by using ptrace
functions in a simple way of register by register access. By unifying
stackframe size, we have a possibility to make use of ptrace functions of
not only a single register access but also block register access,
PTRACE_{GETREGS,PUTREGS}.
However, for this purpose, we might have to modify stackframe structure
some more; for example, PSW (processor status word) register should be
pre-processed before pushing to stack at a syscall, and so on. In this
case, we must update carefully both kernel and GDB at a time...
Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Cc: Kei Sakamoto <ksakamot@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-19 07:21:20 +02:00
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ldi r13, #0
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push r13 ; dummy push acc1h
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push r13 ; dummy push acc1l
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2005-04-17 00:20:36 +02:00
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#else
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#error unknown isa configuration
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#endif
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ldi r13, #-1
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push r13 ; syscall_nr (default: -1)
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push r12
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push r11
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push r10
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push r9
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push r8
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push r7
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push r3
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push r2
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push r1
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push r0
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addi sp, #-4 ; room for implicit pt_regs parameter
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push r6
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push r5
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push r4
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.endm
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.macro RESTORE_ALL
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pop r4
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pop r5
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pop r6
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addi sp, #4
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pop r0
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pop r1
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pop r2
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pop r3
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pop r7
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pop r8
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pop r9
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pop r10
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pop r11
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pop r12
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addi r15, #4 ; Skip syscall number
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#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
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pop r13
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mvtachi r13, a0
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pop r13
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mvtaclo r13, a0
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pop r13
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mvtachi r13, a1
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pop r13
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mvtaclo r13, a1
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#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
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[PATCH] m32r: Fix pt_regs for !COFNIG_ISA_DSP_LEVEL2 target
This modification is required to fix debugging function for m32r targets
with !CONFIG_ISA_DSP_LEVEL2, by unifying 'struct pt_regs' and 'struct
sigcontext' size for all M32R ISA.
Some m32r processor core with !CONFIG_ISA_DSP_LEVEL2 configuration has only
single accumulator a0 (ex. VDEC2 core, M32102 core, etc.), the others with
CONFIG_ISA_DSP_LEVEL2 has two accumulators, a0 and a1.
This means there are two variations of thread context. So far, we reduced
and changed stackframe size at a syscall for their context size. However,
this causes a problem that a GDB for processors with CONFIG_ISA_DSP_LEVEL2
cannot be used for processors with !CONFIG_ISA_DSP_LEVEL2.
From the viewpoint of GDB support, we should reduce such variation of
stackframe size for simplicity.
In this patch, dummy members are added to 'struct pt_regs' and 'struct
sigcontext' to adjust their size for !CONFIG_ISA_DSP_LEVEL2.
This modification is also a one step for a GDB update in future.
Currently, on the m32r, GDB can access process's context by using ptrace
functions in a simple way of register by register access. By unifying
stackframe size, we have a possibility to make use of ptrace functions of
not only a single register access but also block register access,
PTRACE_{GETREGS,PUTREGS}.
However, for this purpose, we might have to modify stackframe structure
some more; for example, PSW (processor status word) register should be
pre-processed before pushing to stack at a syscall, and so on. In this
case, we must update carefully both kernel and GDB at a time...
Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Cc: Kei Sakamoto <ksakamot@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-19 07:21:20 +02:00
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pop r13 ; dummy pop acc1h
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pop r13 ; dummy pop acc1l
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2005-04-17 00:20:36 +02:00
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pop r13
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mvtachi r13
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pop r13
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mvtaclo r13
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#else
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#error unknown isa configuration
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#endif
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pop r14
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mvtc r14, psw
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pop r14
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mvtc r14, bpc
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addi sp, #8 ; Skip bbpsw, bbpc
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pop r14
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mvtc r14, cr3 ; spu
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pop r13
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pop lr ; r14
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pop sp ; spi (r15)
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addi sp, #4 ; Skip orig_r0
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.fillinsn
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1: rte
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.section .fixup,"ax"
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2: bl do_exit
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.previous
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.section __ex_table,"a"
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ALIGN
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.long 1b, 2b
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.previous
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.endm
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#define GET_CURRENT(reg) get_current reg
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.macro get_current reg
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ldi \reg, #-8192
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and \reg, sp
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.endm
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2006-01-06 09:18:41 +01:00
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#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
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2005-04-17 00:20:36 +02:00
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.macro SWITCH_TO_KERNEL_STACK
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; switch to kernel stack (spi)
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clrpsw #0x80 -> nop
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.endm
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2006-01-06 09:18:41 +01:00
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#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
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2005-04-17 00:20:36 +02:00
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.macro SWITCH_TO_KERNEL_STACK
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push r0 ; save r0 for working
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mvfc r0, psw
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and3 r0, r0, #0x00ff7f
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mvtc r0, psw
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slli r0, #16
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bltz r0, 1f ; check BSM-bit
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;
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;; called from kernel context: previous stack = spi
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pop r0 ; retrieve r0
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bra 2f
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.fillinsn
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1:
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;; called from user context: previous stack = spu
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mvfc r0, cr3 ; spu
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addi r0, #4
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mvtc r0, cr3 ; spu
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ld r0, @(-4,r0) ; retrieve r0
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.fillinsn
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2:
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.endm
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2006-01-06 09:18:41 +01:00
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#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
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2005-04-17 00:20:36 +02:00
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_M32R_ASSEMBLER_H */
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