usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
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/**
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* debugfs.c - DesignWare USB3 DRD Controller DebugFS file
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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2013-06-30 13:15:11 +02:00
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
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*
|
2013-06-30 13:15:11 +02:00
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/ptrace.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <linux/delay.h>
|
2011-11-04 11:32:47 +01:00
|
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|
#include <linux/uaccess.h>
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
|
2012-01-02 17:38:30 +01:00
|
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|
#include <linux/usb/ch9.h>
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|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
#include "core.h"
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#include "gadget.h"
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#include "io.h"
|
2011-11-04 11:40:05 +01:00
|
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|
#include "debug.h"
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
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|
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|
|
#define dump_register(nm) \
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|
|
|
{ \
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|
.name = __stringify(nm), \
|
2016-04-12 15:53:39 +02:00
|
|
|
.offset = DWC3_ ##nm, \
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
}
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|
2016-04-12 15:53:39 +02:00
|
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|
#define dump_ep_register_set(n) \
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{ \
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.name = "DEPCMDPAR2("__stringify(n)")", \
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.offset = DWC3_DEP_BASE(n) + \
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DWC3_DEPCMDPAR2, \
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}, \
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{ \
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.name = "DEPCMDPAR1("__stringify(n)")", \
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.offset = DWC3_DEP_BASE(n) + \
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DWC3_DEPCMDPAR1, \
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}, \
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|
{ \
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.name = "DEPCMDPAR0("__stringify(n)")", \
|
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.offset = DWC3_DEP_BASE(n) + \
|
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|
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DWC3_DEPCMDPAR0, \
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|
}, \
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|
{ \
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.name = "DEPCMD("__stringify(n)")", \
|
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.offset = DWC3_DEP_BASE(n) + \
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DWC3_DEPCMD, \
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}
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|
2013-02-22 15:17:31 +01:00
|
|
|
static const struct debugfs_reg32 dwc3_regs[] = {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
dump_register(GSBUSCFG0),
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|
dump_register(GSBUSCFG1),
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dump_register(GTXTHRCFG),
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|
|
dump_register(GRXTHRCFG),
|
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|
|
dump_register(GCTL),
|
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|
|
dump_register(GEVTEN),
|
|
|
|
|
dump_register(GSTS),
|
2016-05-13 12:13:46 +02:00
|
|
|
dump_register(GUCTL1),
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
dump_register(GSNPSID),
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dump_register(GGPIO),
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dump_register(GUID),
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|
dump_register(GUCTL),
|
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|
dump_register(GBUSERRADDR0),
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dump_register(GBUSERRADDR1),
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dump_register(GPRTBIMAP0),
|
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dump_register(GPRTBIMAP1),
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dump_register(GHWPARAMS0),
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dump_register(GHWPARAMS1),
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|
dump_register(GHWPARAMS2),
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|
|
|
dump_register(GHWPARAMS3),
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|
|
dump_register(GHWPARAMS4),
|
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|
|
|
dump_register(GHWPARAMS5),
|
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|
dump_register(GHWPARAMS6),
|
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|
dump_register(GHWPARAMS7),
|
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|
|
dump_register(GDBGFIFOSPACE),
|
|
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|
|
dump_register(GDBGLTSSM),
|
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|
|
dump_register(GPRTBIMAP_HS0),
|
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|
|
dump_register(GPRTBIMAP_HS1),
|
|
|
|
|
dump_register(GPRTBIMAP_FS0),
|
|
|
|
|
dump_register(GPRTBIMAP_FS1),
|
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|
|
|
|
|
|
|
|
dump_register(GUSB2PHYCFG(0)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(1)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(2)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(3)),
|
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|
|
|
dump_register(GUSB2PHYCFG(4)),
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|
|
|
dump_register(GUSB2PHYCFG(5)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(6)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(7)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(8)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(9)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(10)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(11)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(12)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(13)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(14)),
|
|
|
|
|
dump_register(GUSB2PHYCFG(15)),
|
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|
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|
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|
|
|
|
dump_register(GUSB2I2CCTL(0)),
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|
|
|
|
dump_register(GUSB2I2CCTL(1)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(2)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(3)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(4)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(5)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(6)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(7)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(8)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(9)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(10)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(11)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(12)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(13)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(14)),
|
|
|
|
|
dump_register(GUSB2I2CCTL(15)),
|
|
|
|
|
|
|
|
|
|
dump_register(GUSB2PHYACC(0)),
|
|
|
|
|
dump_register(GUSB2PHYACC(1)),
|
|
|
|
|
dump_register(GUSB2PHYACC(2)),
|
|
|
|
|
dump_register(GUSB2PHYACC(3)),
|
|
|
|
|
dump_register(GUSB2PHYACC(4)),
|
|
|
|
|
dump_register(GUSB2PHYACC(5)),
|
|
|
|
|
dump_register(GUSB2PHYACC(6)),
|
|
|
|
|
dump_register(GUSB2PHYACC(7)),
|
|
|
|
|
dump_register(GUSB2PHYACC(8)),
|
|
|
|
|
dump_register(GUSB2PHYACC(9)),
|
|
|
|
|
dump_register(GUSB2PHYACC(10)),
|
|
|
|
|
dump_register(GUSB2PHYACC(11)),
|
|
|
|
|
dump_register(GUSB2PHYACC(12)),
|
|
|
|
|
dump_register(GUSB2PHYACC(13)),
|
|
|
|
|
dump_register(GUSB2PHYACC(14)),
|
|
|
|
|
dump_register(GUSB2PHYACC(15)),
|
|
|
|
|
|
|
|
|
|
dump_register(GUSB3PIPECTL(0)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(1)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(2)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(3)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(4)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(5)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(6)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(7)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(8)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(9)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(10)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(11)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(12)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(13)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(14)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(15)),
|
|
|
|
|
|
|
|
|
|
dump_register(GTXFIFOSIZ(0)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(1)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(2)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(3)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(4)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(5)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(6)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(7)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(8)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(9)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(10)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(11)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(12)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(13)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(14)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(15)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(16)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(17)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(18)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(19)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(20)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(21)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(22)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(23)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(24)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(25)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(26)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(27)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(28)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(29)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(30)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(31)),
|
|
|
|
|
|
|
|
|
|
dump_register(GRXFIFOSIZ(0)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(1)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(2)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(3)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(4)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(5)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(6)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(7)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(8)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(9)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(10)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(11)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(12)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(13)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(14)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(15)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(16)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(17)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(18)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(19)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(20)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(21)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(22)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(23)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(24)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(25)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(26)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(27)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(28)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(29)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(30)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(31)),
|
|
|
|
|
|
|
|
|
|
dump_register(GEVNTADRLO(0)),
|
|
|
|
|
dump_register(GEVNTADRHI(0)),
|
|
|
|
|
dump_register(GEVNTSIZ(0)),
|
|
|
|
|
dump_register(GEVNTCOUNT(0)),
|
|
|
|
|
|
|
|
|
|
dump_register(GHWPARAMS8),
|
|
|
|
|
dump_register(DCFG),
|
|
|
|
|
dump_register(DCTL),
|
|
|
|
|
dump_register(DEVTEN),
|
|
|
|
|
dump_register(DSTS),
|
|
|
|
|
dump_register(DGCMDPAR),
|
|
|
|
|
dump_register(DGCMD),
|
|
|
|
|
dump_register(DALEPENA),
|
|
|
|
|
|
2016-04-12 15:53:39 +02:00
|
|
|
dump_ep_register_set(0),
|
|
|
|
|
dump_ep_register_set(1),
|
|
|
|
|
dump_ep_register_set(2),
|
|
|
|
|
dump_ep_register_set(3),
|
|
|
|
|
dump_ep_register_set(4),
|
|
|
|
|
dump_ep_register_set(5),
|
|
|
|
|
dump_ep_register_set(6),
|
|
|
|
|
dump_ep_register_set(7),
|
|
|
|
|
dump_ep_register_set(8),
|
|
|
|
|
dump_ep_register_set(9),
|
|
|
|
|
dump_ep_register_set(10),
|
|
|
|
|
dump_ep_register_set(11),
|
|
|
|
|
dump_ep_register_set(12),
|
|
|
|
|
dump_ep_register_set(13),
|
|
|
|
|
dump_ep_register_set(14),
|
|
|
|
|
dump_ep_register_set(15),
|
|
|
|
|
dump_ep_register_set(16),
|
|
|
|
|
dump_ep_register_set(17),
|
|
|
|
|
dump_ep_register_set(18),
|
|
|
|
|
dump_ep_register_set(19),
|
|
|
|
|
dump_ep_register_set(20),
|
|
|
|
|
dump_ep_register_set(21),
|
|
|
|
|
dump_ep_register_set(22),
|
|
|
|
|
dump_ep_register_set(23),
|
|
|
|
|
dump_ep_register_set(24),
|
|
|
|
|
dump_ep_register_set(25),
|
|
|
|
|
dump_ep_register_set(26),
|
|
|
|
|
dump_ep_register_set(27),
|
|
|
|
|
dump_ep_register_set(28),
|
|
|
|
|
dump_ep_register_set(29),
|
|
|
|
|
dump_ep_register_set(30),
|
|
|
|
|
dump_ep_register_set(31),
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
|
|
|
|
|
dump_register(OCFG),
|
|
|
|
|
dump_register(OCTL),
|
2013-03-14 11:35:24 +01:00
|
|
|
dump_register(OEVT),
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
dump_register(OEVTEN),
|
|
|
|
|
dump_register(OSTS),
|
|
|
|
|
};
|
|
|
|
|
|
2011-10-17 07:50:39 +02:00
|
|
|
static int dwc3_mode_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
switch (DWC3_GCTL_PRTCAP(reg)) {
|
|
|
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
|
|
|
|
seq_printf(s, "host\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
|
|
|
|
seq_printf(s, "device\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_GCTL_PRTCAP_OTG:
|
|
|
|
|
seq_printf(s, "OTG\n");
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
seq_printf(s, "UNKNOWN %08x\n", DWC3_GCTL_PRTCAP(reg));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_mode_open(struct inode *inode, struct file *file)
|
|
|
|
|
{
|
|
|
|
|
return single_open(file, dwc3_mode_show, inode->i_private);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ssize_t dwc3_mode_write(struct file *file,
|
|
|
|
|
const char __user *ubuf, size_t count, loff_t *ppos)
|
|
|
|
|
{
|
|
|
|
|
struct seq_file *s = file->private_data;
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
2011-10-31 22:25:40 +01:00
|
|
|
u32 mode = 0;
|
2011-10-17 07:50:39 +02:00
|
|
|
char buf[32];
|
|
|
|
|
|
|
|
|
|
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
|
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
|
|
if (!strncmp(buf, "host", 4))
|
2011-10-31 22:25:40 +01:00
|
|
|
mode |= DWC3_GCTL_PRTCAP_HOST;
|
2011-10-17 07:50:39 +02:00
|
|
|
|
|
|
|
|
if (!strncmp(buf, "device", 6))
|
2011-10-31 22:25:40 +01:00
|
|
|
mode |= DWC3_GCTL_PRTCAP_DEVICE;
|
2011-10-17 07:50:39 +02:00
|
|
|
|
|
|
|
|
if (!strncmp(buf, "otg", 3))
|
2011-10-31 22:25:40 +01:00
|
|
|
mode |= DWC3_GCTL_PRTCAP_OTG;
|
2011-10-17 07:50:39 +02:00
|
|
|
|
2011-10-31 22:25:40 +01:00
|
|
|
if (mode) {
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
dwc3_set_mode(dwc, mode);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
}
|
2011-10-17 07:50:39 +02:00
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct file_operations dwc3_mode_fops = {
|
|
|
|
|
.open = dwc3_mode_open,
|
|
|
|
|
.write = dwc3_mode_write,
|
|
|
|
|
.read = seq_read,
|
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
|
.release = single_release,
|
|
|
|
|
};
|
|
|
|
|
|
2012-01-02 17:38:30 +01:00
|
|
|
static int dwc3_testmode_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
|
reg &= DWC3_DCTL_TSTCTRL_MASK;
|
|
|
|
|
reg >>= 1;
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
|
case 0:
|
|
|
|
|
seq_printf(s, "no test\n");
|
|
|
|
|
break;
|
|
|
|
|
case TEST_J:
|
|
|
|
|
seq_printf(s, "test_j\n");
|
|
|
|
|
break;
|
|
|
|
|
case TEST_K:
|
|
|
|
|
seq_printf(s, "test_k\n");
|
|
|
|
|
break;
|
|
|
|
|
case TEST_SE0_NAK:
|
|
|
|
|
seq_printf(s, "test_se0_nak\n");
|
|
|
|
|
break;
|
|
|
|
|
case TEST_PACKET:
|
|
|
|
|
seq_printf(s, "test_packet\n");
|
|
|
|
|
break;
|
|
|
|
|
case TEST_FORCE_EN:
|
|
|
|
|
seq_printf(s, "test_force_enable\n");
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
seq_printf(s, "UNKNOWN %d\n", reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_testmode_open(struct inode *inode, struct file *file)
|
|
|
|
|
{
|
|
|
|
|
return single_open(file, dwc3_testmode_show, inode->i_private);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ssize_t dwc3_testmode_write(struct file *file,
|
|
|
|
|
const char __user *ubuf, size_t count, loff_t *ppos)
|
|
|
|
|
{
|
|
|
|
|
struct seq_file *s = file->private_data;
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 testmode = 0;
|
|
|
|
|
char buf[32];
|
|
|
|
|
|
|
|
|
|
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
|
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
|
|
if (!strncmp(buf, "test_j", 6))
|
|
|
|
|
testmode = TEST_J;
|
|
|
|
|
else if (!strncmp(buf, "test_k", 6))
|
|
|
|
|
testmode = TEST_K;
|
2012-02-10 11:14:53 +01:00
|
|
|
else if (!strncmp(buf, "test_se0_nak", 12))
|
2012-01-02 17:38:30 +01:00
|
|
|
testmode = TEST_SE0_NAK;
|
2012-02-10 11:14:53 +01:00
|
|
|
else if (!strncmp(buf, "test_packet", 11))
|
2012-01-02 17:38:30 +01:00
|
|
|
testmode = TEST_PACKET;
|
2012-02-10 11:14:53 +01:00
|
|
|
else if (!strncmp(buf, "test_force_enable", 17))
|
2012-01-02 17:38:30 +01:00
|
|
|
testmode = TEST_FORCE_EN;
|
|
|
|
|
else
|
|
|
|
|
testmode = 0;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
dwc3_gadget_set_test_mode(dwc, testmode);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct file_operations dwc3_testmode_fops = {
|
|
|
|
|
.open = dwc3_testmode_open,
|
|
|
|
|
.write = dwc3_testmode_write,
|
|
|
|
|
.read = seq_read,
|
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
|
.release = single_release,
|
|
|
|
|
};
|
|
|
|
|
|
2012-01-02 18:25:16 +01:00
|
|
|
static int dwc3_link_state_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
enum dwc3_link_state state;
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
|
state = DWC3_DSTS_USBLNKST(reg);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
|
case DWC3_LINK_STATE_U0:
|
|
|
|
|
seq_printf(s, "U0\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_U1:
|
|
|
|
|
seq_printf(s, "U1\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_U2:
|
|
|
|
|
seq_printf(s, "U2\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_U3:
|
|
|
|
|
seq_printf(s, "U3\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_SS_DIS:
|
|
|
|
|
seq_printf(s, "SS.Disabled\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_RX_DET:
|
|
|
|
|
seq_printf(s, "Rx.Detect\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_SS_INACT:
|
|
|
|
|
seq_printf(s, "SS.Inactive\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_POLL:
|
|
|
|
|
seq_printf(s, "Poll\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_RECOV:
|
|
|
|
|
seq_printf(s, "Recovery\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_HRESET:
|
|
|
|
|
seq_printf(s, "HRESET\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_CMPLY:
|
|
|
|
|
seq_printf(s, "Compliance\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_LPBK:
|
|
|
|
|
seq_printf(s, "Loopback\n");
|
|
|
|
|
break;
|
2013-02-22 13:28:54 +01:00
|
|
|
case DWC3_LINK_STATE_RESET:
|
|
|
|
|
seq_printf(s, "Reset\n");
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_LINK_STATE_RESUME:
|
|
|
|
|
seq_printf(s, "Resume\n");
|
|
|
|
|
break;
|
2012-01-02 18:25:16 +01:00
|
|
|
default:
|
2013-02-22 13:29:39 +01:00
|
|
|
seq_printf(s, "UNKNOWN %d\n", state);
|
2012-01-02 18:25:16 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_link_state_open(struct inode *inode, struct file *file)
|
|
|
|
|
{
|
|
|
|
|
return single_open(file, dwc3_link_state_show, inode->i_private);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ssize_t dwc3_link_state_write(struct file *file,
|
|
|
|
|
const char __user *ubuf, size_t count, loff_t *ppos)
|
|
|
|
|
{
|
|
|
|
|
struct seq_file *s = file->private_data;
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
enum dwc3_link_state state = 0;
|
|
|
|
|
char buf[32];
|
|
|
|
|
|
|
|
|
|
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
|
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
|
|
if (!strncmp(buf, "SS.Disabled", 11))
|
|
|
|
|
state = DWC3_LINK_STATE_SS_DIS;
|
|
|
|
|
else if (!strncmp(buf, "Rx.Detect", 9))
|
|
|
|
|
state = DWC3_LINK_STATE_RX_DET;
|
|
|
|
|
else if (!strncmp(buf, "SS.Inactive", 11))
|
|
|
|
|
state = DWC3_LINK_STATE_SS_INACT;
|
|
|
|
|
else if (!strncmp(buf, "Recovery", 8))
|
|
|
|
|
state = DWC3_LINK_STATE_RECOV;
|
|
|
|
|
else if (!strncmp(buf, "Compliance", 10))
|
|
|
|
|
state = DWC3_LINK_STATE_CMPLY;
|
|
|
|
|
else if (!strncmp(buf, "Loopback", 8))
|
|
|
|
|
state = DWC3_LINK_STATE_LPBK;
|
|
|
|
|
else
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
dwc3_gadget_set_link_state(dwc, state);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct file_operations dwc3_link_state_fops = {
|
|
|
|
|
.open = dwc3_link_state_open,
|
|
|
|
|
.write = dwc3_link_state_write,
|
|
|
|
|
.read = seq_read,
|
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
|
.release = single_release,
|
|
|
|
|
};
|
|
|
|
|
|
2016-04-14 13:53:44 +02:00
|
|
|
struct dwc3_ep_file_map {
|
|
|
|
|
char name[25];
|
|
|
|
|
int (*show)(struct seq_file *s, void *unused);
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int dwc3_tx_fifo_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_TXFIFOQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_rx_fifo_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_RXFIFOQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_tx_request_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_TXREQQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_rx_request_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_RXREQQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_rx_info_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_RXINFOQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_descriptor_fetch_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_DESCFETCHQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_event_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_EVENTQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_ep_transfer_type_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED) ||
|
|
|
|
|
!dep->endpoint.desc) {
|
|
|
|
|
seq_printf(s, "--\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (usb_endpoint_type(dep->endpoint.desc)) {
|
|
|
|
|
case USB_ENDPOINT_XFER_CONTROL:
|
|
|
|
|
seq_printf(s, "control\n");
|
|
|
|
|
break;
|
|
|
|
|
case USB_ENDPOINT_XFER_ISOC:
|
|
|
|
|
seq_printf(s, "isochronous\n");
|
|
|
|
|
break;
|
|
|
|
|
case USB_ENDPOINT_XFER_BULK:
|
|
|
|
|
seq_printf(s, "bulk\n");
|
|
|
|
|
break;
|
|
|
|
|
case USB_ENDPOINT_XFER_INT:
|
|
|
|
|
seq_printf(s, "interrupt\n");
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
seq_printf(s, "--\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline const char *dwc3_trb_type_string(struct dwc3_trb *trb)
|
|
|
|
|
{
|
|
|
|
|
switch (DWC3_TRBCTL_TYPE(trb->ctrl)) {
|
|
|
|
|
case DWC3_TRBCTL_NORMAL:
|
|
|
|
|
return "normal";
|
|
|
|
|
case DWC3_TRBCTL_CONTROL_SETUP:
|
|
|
|
|
return "control-setup";
|
|
|
|
|
case DWC3_TRBCTL_CONTROL_STATUS2:
|
|
|
|
|
return "control-status2";
|
|
|
|
|
case DWC3_TRBCTL_CONTROL_STATUS3:
|
|
|
|
|
return "control-status3";
|
|
|
|
|
case DWC3_TRBCTL_CONTROL_DATA:
|
|
|
|
|
return "control-data";
|
|
|
|
|
case DWC3_TRBCTL_ISOCHRONOUS_FIRST:
|
|
|
|
|
return "isoc-first";
|
|
|
|
|
case DWC3_TRBCTL_ISOCHRONOUS:
|
|
|
|
|
return "isoc";
|
|
|
|
|
case DWC3_TRBCTL_LINK_TRB:
|
|
|
|
|
return "link";
|
|
|
|
|
default:
|
|
|
|
|
return "UNKNOWN";
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_ep_trb_ring_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
if (dep->number <= 1) {
|
|
|
|
|
seq_printf(s, "--\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
seq_printf(s, "enqueue pointer %d\n", dep->trb_enqueue);
|
|
|
|
|
seq_printf(s, "dequeue pointer %d\n", dep->trb_dequeue);
|
|
|
|
|
seq_printf(s, "\n--------------------------------------------------\n\n");
|
|
|
|
|
seq_printf(s, "buffer_addr,size,type,ioc,isp_imi,csp,chn,lst,hwo\n");
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < DWC3_TRB_NUM; i++) {
|
|
|
|
|
struct dwc3_trb *trb = &dep->trb_pool[i];
|
|
|
|
|
|
|
|
|
|
seq_printf(s, "%08x%08x,%d,%s,%d,%d,%d,%d,%d,%d\n",
|
|
|
|
|
trb->bph, trb->bpl, trb->size,
|
|
|
|
|
dwc3_trb_type_string(trb),
|
|
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_IOC),
|
|
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_ISP_IMI),
|
|
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_CSP),
|
|
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_CHN),
|
|
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_LST),
|
|
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_HWO));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct dwc3_ep_file_map map[] = {
|
|
|
|
|
{ "tx_fifo_queue", dwc3_tx_fifo_queue_show, },
|
|
|
|
|
{ "rx_fifo_queue", dwc3_rx_fifo_queue_show, },
|
|
|
|
|
{ "tx_request_queue", dwc3_tx_request_queue_show, },
|
|
|
|
|
{ "rx_request_queue", dwc3_rx_request_queue_show, },
|
|
|
|
|
{ "rx_info_queue", dwc3_rx_info_queue_show, },
|
|
|
|
|
{ "descriptor_fetch_queue", dwc3_descriptor_fetch_queue_show, },
|
|
|
|
|
{ "event_queue", dwc3_event_queue_show, },
|
|
|
|
|
{ "transfer_type", dwc3_ep_transfer_type_show, },
|
|
|
|
|
{ "trb_ring", dwc3_ep_trb_ring_show, },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int dwc3_endpoint_open(struct inode *inode, struct file *file)
|
|
|
|
|
{
|
|
|
|
|
const char *file_name = file_dentry(file)->d_iname;
|
|
|
|
|
struct dwc3_ep_file_map *f_map;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(map); i++) {
|
|
|
|
|
f_map = &map[i];
|
|
|
|
|
|
|
|
|
|
if (strcmp(f_map->name, file_name) == 0)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return single_open(file, f_map->show, inode->i_private);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct file_operations dwc3_endpoint_fops = {
|
|
|
|
|
.open = dwc3_endpoint_open,
|
|
|
|
|
.read = seq_read,
|
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
|
.release = single_release,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void dwc3_debugfs_create_endpoint_file(struct dwc3_ep *dep,
|
|
|
|
|
struct dentry *parent, int type)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
{
|
|
|
|
|
struct dentry *file;
|
2016-04-14 13:53:44 +02:00
|
|
|
struct dwc3_ep_file_map *ep_file = &map[type];
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
|
2016-04-14 13:53:44 +02:00
|
|
|
file = debugfs_create_file(ep_file->name, S_IRUGO, parent, dep,
|
|
|
|
|
&dwc3_endpoint_fops);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dwc3_debugfs_create_endpoint_files(struct dwc3_ep *dep,
|
|
|
|
|
struct dentry *parent)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(map); i++)
|
|
|
|
|
dwc3_debugfs_create_endpoint_file(dep, parent, i);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dwc3_debugfs_create_endpoint_dir(struct dwc3_ep *dep,
|
|
|
|
|
struct dentry *parent)
|
|
|
|
|
{
|
|
|
|
|
struct dentry *dir;
|
|
|
|
|
|
|
|
|
|
dir = debugfs_create_dir(dep->name, parent);
|
|
|
|
|
if (IS_ERR_OR_NULL(dir))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
dwc3_debugfs_create_endpoint_files(dep, dir);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dwc3_debugfs_create_endpoint_dirs(struct dwc3 *dwc,
|
|
|
|
|
struct dentry *parent)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < dwc->num_in_eps; i++) {
|
|
|
|
|
u8 epnum = (i << 1) | 1;
|
|
|
|
|
struct dwc3_ep *dep = dwc->eps[epnum];
|
|
|
|
|
|
|
|
|
|
if (!dep)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
dwc3_debugfs_create_endpoint_dir(dep, parent);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < dwc->num_out_eps; i++) {
|
|
|
|
|
u8 epnum = (i << 1);
|
|
|
|
|
struct dwc3_ep *dep = dwc->eps[epnum];
|
|
|
|
|
|
|
|
|
|
if (!dep)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
dwc3_debugfs_create_endpoint_dir(dep, parent);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
}
|
2016-04-14 13:53:44 +02:00
|
|
|
}
|
|
|
|
|
|
2016-04-12 13:10:18 +02:00
|
|
|
void dwc3_debugfs_init(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
{
|
|
|
|
|
struct dentry *root;
|
2016-04-12 13:10:18 +02:00
|
|
|
struct dentry *file;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
|
|
|
|
|
root = debugfs_create_dir(dev_name(dwc->dev), NULL);
|
2016-04-12 13:10:18 +02:00
|
|
|
if (IS_ERR_OR_NULL(root)) {
|
|
|
|
|
if (!root)
|
|
|
|
|
dev_err(dwc->dev, "Can't create debugfs root\n");
|
|
|
|
|
return;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
}
|
|
|
|
|
dwc->root = root;
|
|
|
|
|
|
2013-01-18 09:21:34 +01:00
|
|
|
dwc->regset = kzalloc(sizeof(*dwc->regset), GFP_KERNEL);
|
|
|
|
|
if (!dwc->regset) {
|
2016-04-12 13:10:18 +02:00
|
|
|
debugfs_remove_recursive(root);
|
|
|
|
|
return;
|
2013-01-18 09:21:34 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dwc->regset->regs = dwc3_regs;
|
|
|
|
|
dwc->regset->nregs = ARRAY_SIZE(dwc3_regs);
|
2016-04-12 15:53:39 +02:00
|
|
|
dwc->regset->base = dwc->regs - DWC3_GLOBALS_REGS_START;
|
2013-01-18 09:21:34 +01:00
|
|
|
|
|
|
|
|
file = debugfs_create_regset32("regdump", S_IRUGO, root, dwc->regset);
|
2016-04-12 13:10:18 +02:00
|
|
|
if (!file)
|
|
|
|
|
dev_dbg(dwc->dev, "Can't create debugfs regdump\n");
|
2011-10-17 07:50:39 +02:00
|
|
|
|
2013-02-22 15:24:49 +01:00
|
|
|
if (IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)) {
|
|
|
|
|
file = debugfs_create_file("mode", S_IRUGO | S_IWUSR, root,
|
|
|
|
|
dwc, &dwc3_mode_fops);
|
2016-04-12 13:10:18 +02:00
|
|
|
if (!file)
|
|
|
|
|
dev_dbg(dwc->dev, "Can't create debugfs mode\n");
|
2011-10-17 07:50:39 +02:00
|
|
|
}
|
|
|
|
|
|
2013-02-22 15:24:49 +01:00
|
|
|
if (IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) ||
|
|
|
|
|
IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
|
|
|
|
|
file = debugfs_create_file("testmode", S_IRUGO | S_IWUSR, root,
|
|
|
|
|
dwc, &dwc3_testmode_fops);
|
2016-04-12 13:10:18 +02:00
|
|
|
if (!file)
|
|
|
|
|
dev_dbg(dwc->dev, "Can't create debugfs testmode\n");
|
2012-01-02 18:25:16 +01:00
|
|
|
|
2016-04-12 13:10:18 +02:00
|
|
|
file = debugfs_create_file("link_state", S_IRUGO | S_IWUSR,
|
|
|
|
|
root, dwc, &dwc3_link_state_fops);
|
|
|
|
|
if (!file)
|
|
|
|
|
dev_dbg(dwc->dev, "Can't create debugfs link_state\n");
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
|
2016-04-14 13:53:44 +02:00
|
|
|
dwc3_debugfs_create_endpoint_dirs(dwc, root);
|
2016-04-12 13:10:18 +02:00
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
}
|
|
|
|
|
|
2012-11-19 19:26:20 +01:00
|
|
|
void dwc3_debugfs_exit(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
|
|
|
{
|
|
|
|
|
debugfs_remove_recursive(dwc->root);
|
2016-04-12 10:24:34 +02:00
|
|
|
kfree(dwc->regset);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 17:10:58 +02:00
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}
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