[media] IR: add driver for Nuvoton w836x7hg integrated CIR
This is a new ir-core pnp driver for the Nuvoton w836x7hg integrated CIR
function. The chip is found on at least the ASRock ION 330HT boxes and
apparently, on a number of Intel DP55-series motherboards:
http://www.asrock.com/nettop/overview.asp?Model=ION%20330HT
http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17685&lang=eng
This driver was made possible by a hardware donation from Nuvoton, along
with sample code (in the form of an lirc driver) and datasheet, so huge
thanks to them for supporting this effort. Note that this driver
constitutes a massive rewrite, porting from the lirc interfaces to the
ir-core interfaces, and restructuring the driver to look more like Maxim
Levitsky's ene_ir driver (as well as generally making it look more like
kernel code).
There's some work left to be done on this driver, to fully support the
range of functionality possible, but receive and IR power-on/wake are
both functional (may require setting wake key under another OS atm). The
hardware I've got (one of the ASRock boxes) only supports RX, so TX is
completely untested as of yet. Certain RX parameters, like sample
resolution and RX IRQ sample length trigger level could possibly stand
to be made tweakable via modparams or sysfs nodes, but the current
values work well enough for me w/an MCE RC6A remote.
The original lirc driver carried support for the Windows MCE IR
keyboard/mouse device, which I plan to add back generically, in a way
that should be usable by any raw IR receiver (or at least by this driver
and the mceusb driver).
Suspend and resume have also been tested, the power button on my remote
can be used to wake the machine, and CIR functionality resumes just
fine. Module unload/reload has also been tested, though not extensively
or repetitively. Also tested to work with the lirc bridge plugin for
userspace decoding.
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-10-07 22:50:34 +02:00
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/*
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* Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
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*
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* Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
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* Copyright (C) 2009 Nuvoton PS Team
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*
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* Special thanks to Nuvoton for providing hardware, spec sheets and
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* sample code upon which portions of this driver are based. Indirect
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* thanks also to Maxim Levitsky, whose ene_ir driver this driver is
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* modeled after.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pnp.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/input.h>
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#include <media/ir-core.h>
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#include <linux/pci_ids.h>
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#include "nuvoton-cir.h"
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static char *chip_id = "w836x7hg";
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/* write val to config reg */
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static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
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{
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outb(reg, nvt->cr_efir);
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outb(val, nvt->cr_efdr);
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}
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/* read val from config reg */
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static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
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{
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outb(reg, nvt->cr_efir);
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return inb(nvt->cr_efdr);
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}
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/* update config register bit without changing other bits */
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static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
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{
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u8 tmp = nvt_cr_read(nvt, reg) | val;
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nvt_cr_write(nvt, tmp, reg);
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}
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/* clear config register bit without changing other bits */
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static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
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{
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u8 tmp = nvt_cr_read(nvt, reg) & ~val;
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nvt_cr_write(nvt, tmp, reg);
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}
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/* enter extended function mode */
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static inline void nvt_efm_enable(struct nvt_dev *nvt)
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{
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/* Enabling Extended Function Mode explicitly requires writing 2x */
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outb(EFER_EFM_ENABLE, nvt->cr_efir);
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outb(EFER_EFM_ENABLE, nvt->cr_efir);
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}
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/* exit extended function mode */
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static inline void nvt_efm_disable(struct nvt_dev *nvt)
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{
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outb(EFER_EFM_DISABLE, nvt->cr_efir);
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}
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/*
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* When you want to address a specific logical device, write its logical
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* device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
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* 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
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*/
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static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
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{
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outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
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outb(ldev, nvt->cr_efdr);
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}
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/* write val to cir config register */
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static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
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{
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outb(val, nvt->cir_addr + offset);
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}
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/* read val from cir config register */
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static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
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{
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u8 val;
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val = inb(nvt->cir_addr + offset);
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return val;
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}
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/* write val to cir wake register */
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static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
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u8 val, u8 offset)
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{
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outb(val, nvt->cir_wake_addr + offset);
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}
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/* read val from cir wake config register */
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static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
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{
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u8 val;
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val = inb(nvt->cir_wake_addr + offset);
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return val;
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}
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/* dump current cir register contents */
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static void cir_dump_regs(struct nvt_dev *nvt)
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{
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nvt_efm_enable(nvt);
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nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
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printk("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
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printk(" * CR CIR ACTIVE : 0x%x\n",
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nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
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printk(" * CR CIR BASE ADDR: 0x%x\n",
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(nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
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nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
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printk(" * CR CIR IRQ NUM: 0x%x\n",
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nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
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nvt_efm_disable(nvt);
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printk("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
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printk(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
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printk(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
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printk(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
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printk(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
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printk(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
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printk(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
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printk(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
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printk(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
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printk(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
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printk(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
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printk(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
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printk(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
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printk(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
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printk(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
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printk(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
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printk(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
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}
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/* dump current cir wake register contents */
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static void cir_wake_dump_regs(struct nvt_dev *nvt)
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{
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u8 i, fifo_len;
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nvt_efm_enable(nvt);
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nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
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printk("%s: Dump CIR WAKE logical device registers:\n",
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NVT_DRIVER_NAME);
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printk(" * CR CIR WAKE ACTIVE : 0x%x\n",
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nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
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printk(" * CR CIR WAKE BASE ADDR: 0x%x\n",
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(nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
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nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
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printk(" * CR CIR WAKE IRQ NUM: 0x%x\n",
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nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
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nvt_efm_disable(nvt);
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printk("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
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printk(" * IRCON: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
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printk(" * IRSTS: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
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printk(" * IREN: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
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printk(" * FIFO CMP DEEP: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
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printk(" * FIFO CMP TOL: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
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printk(" * FIFO COUNT: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
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printk(" * SLCH: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
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printk(" * SLCL: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
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printk(" * FIFOCON: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
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printk(" * SRXFSTS: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
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printk(" * SAMPLE RX FIFO: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
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printk(" * WR FIFO DATA: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
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printk(" * RD FIFO ONLY: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
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printk(" * RD FIFO ONLY IDX: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
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printk(" * FIFO IGNORE: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
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printk(" * IRFSM: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
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fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
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printk("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
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printk("* Contents = ");
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for (i = 0; i < fifo_len; i++)
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printk("%02x ",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
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printk("\n");
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}
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/* detect hardware features */
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static int nvt_hw_detect(struct nvt_dev *nvt)
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{
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unsigned long flags;
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u8 chip_major, chip_minor;
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int ret = 0;
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nvt_efm_enable(nvt);
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/* Check if we're wired for the alternate EFER setup */
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chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
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if (chip_major == 0xff) {
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nvt->cr_efir = CR_EFIR2;
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nvt->cr_efdr = CR_EFDR2;
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nvt_efm_enable(nvt);
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chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
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}
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chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
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nvt_dbg("%s: chip id: 0x%02x 0x%02x", chip_id, chip_major, chip_minor);
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if (chip_major != CHIP_ID_HIGH &&
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(chip_minor != CHIP_ID_LOW || chip_minor != CHIP_ID_LOW2))
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ret = -ENODEV;
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nvt_efm_disable(nvt);
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spin_lock_irqsave(&nvt->nvt_lock, flags);
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nvt->chip_major = chip_major;
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nvt->chip_minor = chip_minor;
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spin_unlock_irqrestore(&nvt->nvt_lock, flags);
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return ret;
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}
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static void nvt_cir_ldev_init(struct nvt_dev *nvt)
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{
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u8 val;
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/* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */
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val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL);
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val &= OUTPUT_PIN_SEL_MASK;
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val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB);
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nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL);
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/* Select CIR logical device and enable */
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nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
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nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
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nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
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nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
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nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
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nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
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nvt->cir_addr, nvt->cir_irq);
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}
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static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
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{
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/* Select ACPI logical device, enable it and CIR Wake */
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nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
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nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
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|
|
|
|
|
|
/* Enable CIR Wake via PSOUT# (Pin60) */
|
|
|
|
nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
|
|
|
|
|
|
|
|
/* enable cir interrupt of mouse/keyboard IRQ event */
|
|
|
|
nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
|
|
|
|
|
|
|
|
/* enable pme interrupt of cir wakeup event */
|
|
|
|
nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
|
|
|
|
|
|
|
|
/* Select CIR Wake logical device and enable */
|
|
|
|
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
|
|
|
|
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
|
|
|
|
|
|
|
|
nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
|
|
|
|
nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
|
|
|
|
|
|
|
|
nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
|
|
|
|
|
|
|
|
nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
|
|
|
|
nvt->cir_wake_addr, nvt->cir_wake_irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clear out the hardware's cir rx fifo */
|
|
|
|
static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
u8 val;
|
|
|
|
|
|
|
|
val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
|
|
|
|
nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clear out the hardware's cir wake rx fifo */
|
|
|
|
static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
u8 val;
|
|
|
|
|
|
|
|
val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
|
|
|
|
nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
|
|
|
|
CIR_WAKE_FIFOCON);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clear out the hardware's cir tx fifo */
|
|
|
|
static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
u8 val;
|
|
|
|
|
|
|
|
val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
|
|
|
|
nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
|
|
|
|
}
|
|
|
|
|
2010-10-08 21:16:23 +02:00
|
|
|
/* enable RX Trigger Level Reach and Packet End interrupts */
|
|
|
|
static void nvt_set_cir_iren(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
u8 iren;
|
|
|
|
|
|
|
|
iren = CIR_IREN_RTR | CIR_IREN_PE;
|
|
|
|
nvt_cir_reg_write(nvt, iren, CIR_IREN);
|
|
|
|
}
|
|
|
|
|
[media] IR: add driver for Nuvoton w836x7hg integrated CIR
This is a new ir-core pnp driver for the Nuvoton w836x7hg integrated CIR
function. The chip is found on at least the ASRock ION 330HT boxes and
apparently, on a number of Intel DP55-series motherboards:
http://www.asrock.com/nettop/overview.asp?Model=ION%20330HT
http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17685&lang=eng
This driver was made possible by a hardware donation from Nuvoton, along
with sample code (in the form of an lirc driver) and datasheet, so huge
thanks to them for supporting this effort. Note that this driver
constitutes a massive rewrite, porting from the lirc interfaces to the
ir-core interfaces, and restructuring the driver to look more like Maxim
Levitsky's ene_ir driver (as well as generally making it look more like
kernel code).
There's some work left to be done on this driver, to fully support the
range of functionality possible, but receive and IR power-on/wake are
both functional (may require setting wake key under another OS atm). The
hardware I've got (one of the ASRock boxes) only supports RX, so TX is
completely untested as of yet. Certain RX parameters, like sample
resolution and RX IRQ sample length trigger level could possibly stand
to be made tweakable via modparams or sysfs nodes, but the current
values work well enough for me w/an MCE RC6A remote.
The original lirc driver carried support for the Windows MCE IR
keyboard/mouse device, which I plan to add back generically, in a way
that should be usable by any raw IR receiver (or at least by this driver
and the mceusb driver).
Suspend and resume have also been tested, the power button on my remote
can be used to wake the machine, and CIR functionality resumes just
fine. Module unload/reload has also been tested, though not extensively
or repetitively. Also tested to work with the lirc bridge plugin for
userspace decoding.
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-10-07 22:50:34 +02:00
|
|
|
static void nvt_cir_regs_init(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
/* set sample limit count (PE interrupt raised when reached) */
|
|
|
|
nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
|
|
|
|
nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
|
|
|
|
|
|
|
|
/* set fifo irq trigger levels */
|
|
|
|
nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
|
|
|
|
CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable TX and RX, specify carrier on = low, off = high, and set
|
|
|
|
* sample period (currently 50us)
|
|
|
|
*/
|
|
|
|
nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN | CIR_IRCON_RXINV |
|
|
|
|
CIR_IRCON_SAMPLE_PERIOD_SEL, CIR_IRCON);
|
|
|
|
|
|
|
|
/* clear hardware rx and tx fifos */
|
|
|
|
nvt_clear_cir_fifo(nvt);
|
|
|
|
nvt_clear_tx_fifo(nvt);
|
|
|
|
|
|
|
|
/* clear any and all stray interrupts */
|
|
|
|
nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
|
|
|
|
|
2010-10-08 21:16:23 +02:00
|
|
|
/* and finally, enable interrupts */
|
|
|
|
nvt_set_cir_iren(nvt);
|
[media] IR: add driver for Nuvoton w836x7hg integrated CIR
This is a new ir-core pnp driver for the Nuvoton w836x7hg integrated CIR
function. The chip is found on at least the ASRock ION 330HT boxes and
apparently, on a number of Intel DP55-series motherboards:
http://www.asrock.com/nettop/overview.asp?Model=ION%20330HT
http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17685&lang=eng
This driver was made possible by a hardware donation from Nuvoton, along
with sample code (in the form of an lirc driver) and datasheet, so huge
thanks to them for supporting this effort. Note that this driver
constitutes a massive rewrite, porting from the lirc interfaces to the
ir-core interfaces, and restructuring the driver to look more like Maxim
Levitsky's ene_ir driver (as well as generally making it look more like
kernel code).
There's some work left to be done on this driver, to fully support the
range of functionality possible, but receive and IR power-on/wake are
both functional (may require setting wake key under another OS atm). The
hardware I've got (one of the ASRock boxes) only supports RX, so TX is
completely untested as of yet. Certain RX parameters, like sample
resolution and RX IRQ sample length trigger level could possibly stand
to be made tweakable via modparams or sysfs nodes, but the current
values work well enough for me w/an MCE RC6A remote.
The original lirc driver carried support for the Windows MCE IR
keyboard/mouse device, which I plan to add back generically, in a way
that should be usable by any raw IR receiver (or at least by this driver
and the mceusb driver).
Suspend and resume have also been tested, the power button on my remote
can be used to wake the machine, and CIR functionality resumes just
fine. Module unload/reload has also been tested, though not extensively
or repetitively. Also tested to work with the lirc bridge plugin for
userspace decoding.
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-10-07 22:50:34 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
/* set number of bytes needed for wake key comparison (default 67) */
|
|
|
|
nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_LEN, CIR_WAKE_FIFO_CMP_DEEP);
|
|
|
|
|
|
|
|
/* set tolerance/variance allowed per byte during wake compare */
|
|
|
|
nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
|
|
|
|
CIR_WAKE_FIFO_CMP_TOL);
|
|
|
|
|
|
|
|
/* set sample limit count (PE interrupt raised when reached) */
|
|
|
|
nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
|
|
|
|
nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
|
|
|
|
|
|
|
|
/* set cir wake fifo rx trigger level (currently 67) */
|
|
|
|
nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
|
|
|
|
CIR_WAKE_FIFOCON);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable TX and RX, specific carrier on = low, off = high, and set
|
|
|
|
* sample period (currently 50us)
|
|
|
|
*/
|
|
|
|
nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
|
|
|
|
CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
|
|
|
|
CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
|
|
|
|
CIR_WAKE_IRCON);
|
|
|
|
|
|
|
|
/* clear cir wake rx fifo */
|
|
|
|
nvt_clear_cir_wake_fifo(nvt);
|
|
|
|
|
|
|
|
/* clear any and all stray interrupts */
|
|
|
|
nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void nvt_enable_wake(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
nvt_efm_enable(nvt);
|
|
|
|
|
|
|
|
nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
|
|
|
|
nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
|
|
|
|
nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
|
|
|
|
nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
|
|
|
|
|
|
|
|
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
|
|
|
|
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
|
|
|
|
|
|
|
|
nvt_efm_disable(nvt);
|
|
|
|
|
|
|
|
nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
|
|
|
|
CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
|
|
|
|
CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, CIR_WAKE_IRCON);
|
|
|
|
nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
|
|
|
|
nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
|
|
|
|
static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
u32 count, carrier, duration = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
count = nvt_cir_reg_read(nvt, CIR_FCCL) |
|
|
|
|
nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
|
|
|
|
|
|
|
|
for (i = 0; i < nvt->pkts; i++) {
|
|
|
|
if (nvt->buf[i] & BUF_PULSE_BIT)
|
|
|
|
duration += nvt->buf[i] & BUF_LEN_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
duration *= SAMPLE_PERIOD;
|
|
|
|
|
|
|
|
if (!count || !duration) {
|
|
|
|
nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
|
|
|
|
count, duration);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
carrier = (count * 1000000) / duration;
|
|
|
|
|
|
|
|
if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
|
|
|
|
nvt_dbg("WTF? Carrier frequency out of range!");
|
|
|
|
|
|
|
|
nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
|
|
|
|
carrier, count, duration);
|
|
|
|
|
|
|
|
return carrier;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* set carrier frequency
|
|
|
|
*
|
|
|
|
* set carrier on 2 registers: CP & CC
|
|
|
|
* always set CP as 0x81
|
|
|
|
* set CC by SPEC, CC = 3MHz/carrier - 1
|
|
|
|
*/
|
|
|
|
static int nvt_set_tx_carrier(void *data, u32 carrier)
|
|
|
|
{
|
|
|
|
struct nvt_dev *nvt = data;
|
|
|
|
u16 val;
|
|
|
|
|
|
|
|
nvt_cir_reg_write(nvt, 1, CIR_CP);
|
|
|
|
val = 3000000 / (carrier) - 1;
|
|
|
|
nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
|
|
|
|
|
|
|
|
nvt_dbg("cp: 0x%x cc: 0x%x\n",
|
|
|
|
nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* nvt_tx_ir
|
|
|
|
*
|
|
|
|
* 1) clean TX fifo first (handled by AP)
|
|
|
|
* 2) copy data from user space
|
|
|
|
* 3) disable RX interrupts, enable TX interrupts: TTR & TFU
|
|
|
|
* 4) send 9 packets to TX FIFO to open TTR
|
|
|
|
* in interrupt_handler:
|
|
|
|
* 5) send all data out
|
|
|
|
* go back to write():
|
|
|
|
* 6) disable TX interrupts, re-enable RX interupts
|
|
|
|
*
|
|
|
|
* The key problem of this function is user space data may larger than
|
|
|
|
* driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
|
|
|
|
* buf, and keep current copied data buf num in cur_buf_num. But driver's buf
|
|
|
|
* number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
|
|
|
|
* set TXFCONT as 0xff, until buf_count less than 0xff.
|
|
|
|
*/
|
|
|
|
static int nvt_tx_ir(void *priv, int *txbuf, u32 n)
|
|
|
|
{
|
|
|
|
struct nvt_dev *nvt = priv;
|
|
|
|
unsigned long flags;
|
|
|
|
size_t cur_count;
|
|
|
|
unsigned int i;
|
|
|
|
u8 iren;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&nvt->tx.lock, flags);
|
|
|
|
|
|
|
|
if (n >= TX_BUF_LEN) {
|
|
|
|
nvt->tx.buf_count = cur_count = TX_BUF_LEN;
|
|
|
|
ret = TX_BUF_LEN;
|
|
|
|
} else {
|
|
|
|
nvt->tx.buf_count = cur_count = n;
|
|
|
|
ret = n;
|
|
|
|
}
|
|
|
|
|
|
|
|
memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
|
|
|
|
|
|
|
|
nvt->tx.cur_buf_num = 0;
|
|
|
|
|
|
|
|
/* save currently enabled interrupts */
|
|
|
|
iren = nvt_cir_reg_read(nvt, CIR_IREN);
|
|
|
|
|
|
|
|
/* now disable all interrupts, save TFU & TTR */
|
|
|
|
nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
|
|
|
|
|
|
|
|
nvt->tx.tx_state = ST_TX_REPLY;
|
|
|
|
|
|
|
|
nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
|
|
|
|
CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
|
|
|
|
|
|
|
|
/* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
|
|
|
|
for (i = 0; i < 9; i++)
|
|
|
|
nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&nvt->tx.lock, flags);
|
|
|
|
|
|
|
|
wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&nvt->tx.lock, flags);
|
|
|
|
nvt->tx.tx_state = ST_TX_NONE;
|
|
|
|
spin_unlock_irqrestore(&nvt->tx.lock, flags);
|
|
|
|
|
|
|
|
/* restore enabled interrupts to prior state */
|
|
|
|
nvt_cir_reg_write(nvt, iren, CIR_IREN);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* dump contents of the last rx buffer we got from the hw rx fifo */
|
|
|
|
static void nvt_dump_rx_buf(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
printk("%s (len %d): ", __func__, nvt->pkts);
|
|
|
|
for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
|
|
|
|
printk("0x%02x ", nvt->buf[i]);
|
|
|
|
printk("\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Process raw data in rx driver buffer, store it in raw IR event kfifo,
|
|
|
|
* trigger decode when appropriate.
|
|
|
|
*
|
|
|
|
* We get IR data samples one byte at a time. If the msb is set, its a pulse,
|
|
|
|
* otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
|
|
|
|
* (default 50us) intervals for that pulse/space. A discrete signal is
|
|
|
|
* followed by a series of 0x7f packets, then either 0x7<something> or 0x80
|
|
|
|
* to signal more IR coming (repeats) or end of IR, respectively. We store
|
|
|
|
* sample data in the raw event kfifo until we see 0x7<something> (except f)
|
|
|
|
* or 0x80, at which time, we trigger a decode operation.
|
|
|
|
*/
|
|
|
|
static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
struct ir_raw_event rawir = { .pulse = false, .duration = 0 };
|
|
|
|
unsigned int count;
|
|
|
|
u32 carrier;
|
|
|
|
u8 sample;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
nvt_dbg_verbose("%s firing", __func__);
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
nvt_dump_rx_buf(nvt);
|
|
|
|
|
|
|
|
if (nvt->carrier_detect_enabled)
|
|
|
|
carrier = nvt_rx_carrier_detect(nvt);
|
|
|
|
|
|
|
|
count = nvt->pkts;
|
|
|
|
nvt_dbg_verbose("Processing buffer of len %d", count);
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
nvt->pkts--;
|
|
|
|
sample = nvt->buf[i];
|
|
|
|
|
|
|
|
rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
|
|
|
|
rawir.duration = (sample & BUF_LEN_MASK)
|
|
|
|
* SAMPLE_PERIOD * 1000;
|
|
|
|
|
|
|
|
if ((sample & BUF_LEN_MASK) == BUF_LEN_MASK) {
|
|
|
|
if (nvt->rawir.pulse == rawir.pulse)
|
|
|
|
nvt->rawir.duration += rawir.duration;
|
|
|
|
else {
|
|
|
|
nvt->rawir.duration = rawir.duration;
|
|
|
|
nvt->rawir.pulse = rawir.pulse;
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
rawir.duration += nvt->rawir.duration;
|
|
|
|
nvt->rawir.duration = 0;
|
|
|
|
nvt->rawir.pulse = rawir.pulse;
|
|
|
|
|
|
|
|
if (sample == BUF_PULSE_BIT)
|
|
|
|
rawir.pulse = false;
|
|
|
|
|
|
|
|
if (rawir.duration) {
|
|
|
|
nvt_dbg("Storing %s with duration %d",
|
|
|
|
rawir.pulse ? "pulse" : "space",
|
|
|
|
rawir.duration);
|
|
|
|
|
|
|
|
ir_raw_event_store(nvt->rdev, &rawir);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
|
|
|
|
* indicates end of IR signal, but new data incoming. In both
|
|
|
|
* cases, it means we're ready to call ir_raw_event_handle
|
|
|
|
*/
|
|
|
|
if (sample == BUF_PULSE_BIT || ((sample != BUF_LEN_MASK) &&
|
|
|
|
(sample & BUF_REPEAT_MASK) == BUF_REPEAT_BYTE))
|
|
|
|
ir_raw_event_handle(nvt->rdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (nvt->pkts) {
|
|
|
|
nvt_dbg("Odd, pkts should be 0 now... (its %u)", nvt->pkts);
|
|
|
|
nvt->pkts = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
nvt_dbg_verbose("%s done", __func__);
|
|
|
|
}
|
|
|
|
|
2010-10-08 21:16:23 +02:00
|
|
|
static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
|
|
|
|
|
|
|
|
nvt->pkts = 0;
|
|
|
|
nvt_clear_cir_fifo(nvt);
|
|
|
|
ir_raw_event_reset(nvt->rdev);
|
|
|
|
}
|
|
|
|
|
[media] IR: add driver for Nuvoton w836x7hg integrated CIR
This is a new ir-core pnp driver for the Nuvoton w836x7hg integrated CIR
function. The chip is found on at least the ASRock ION 330HT boxes and
apparently, on a number of Intel DP55-series motherboards:
http://www.asrock.com/nettop/overview.asp?Model=ION%20330HT
http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17685&lang=eng
This driver was made possible by a hardware donation from Nuvoton, along
with sample code (in the form of an lirc driver) and datasheet, so huge
thanks to them for supporting this effort. Note that this driver
constitutes a massive rewrite, porting from the lirc interfaces to the
ir-core interfaces, and restructuring the driver to look more like Maxim
Levitsky's ene_ir driver (as well as generally making it look more like
kernel code).
There's some work left to be done on this driver, to fully support the
range of functionality possible, but receive and IR power-on/wake are
both functional (may require setting wake key under another OS atm). The
hardware I've got (one of the ASRock boxes) only supports RX, so TX is
completely untested as of yet. Certain RX parameters, like sample
resolution and RX IRQ sample length trigger level could possibly stand
to be made tweakable via modparams or sysfs nodes, but the current
values work well enough for me w/an MCE RC6A remote.
The original lirc driver carried support for the Windows MCE IR
keyboard/mouse device, which I plan to add back generically, in a way
that should be usable by any raw IR receiver (or at least by this driver
and the mceusb driver).
Suspend and resume have also been tested, the power button on my remote
can be used to wake the machine, and CIR functionality resumes just
fine. Module unload/reload has also been tested, though not extensively
or repetitively. Also tested to work with the lirc bridge plugin for
userspace decoding.
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-10-07 22:50:34 +02:00
|
|
|
/* copy data from hardware rx fifo into driver buffer */
|
|
|
|
static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
u8 fifocount, val;
|
|
|
|
unsigned int b_idx;
|
2010-10-08 21:16:23 +02:00
|
|
|
bool overrun = false;
|
[media] IR: add driver for Nuvoton w836x7hg integrated CIR
This is a new ir-core pnp driver for the Nuvoton w836x7hg integrated CIR
function. The chip is found on at least the ASRock ION 330HT boxes and
apparently, on a number of Intel DP55-series motherboards:
http://www.asrock.com/nettop/overview.asp?Model=ION%20330HT
http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17685&lang=eng
This driver was made possible by a hardware donation from Nuvoton, along
with sample code (in the form of an lirc driver) and datasheet, so huge
thanks to them for supporting this effort. Note that this driver
constitutes a massive rewrite, porting from the lirc interfaces to the
ir-core interfaces, and restructuring the driver to look more like Maxim
Levitsky's ene_ir driver (as well as generally making it look more like
kernel code).
There's some work left to be done on this driver, to fully support the
range of functionality possible, but receive and IR power-on/wake are
both functional (may require setting wake key under another OS atm). The
hardware I've got (one of the ASRock boxes) only supports RX, so TX is
completely untested as of yet. Certain RX parameters, like sample
resolution and RX IRQ sample length trigger level could possibly stand
to be made tweakable via modparams or sysfs nodes, but the current
values work well enough for me w/an MCE RC6A remote.
The original lirc driver carried support for the Windows MCE IR
keyboard/mouse device, which I plan to add back generically, in a way
that should be usable by any raw IR receiver (or at least by this driver
and the mceusb driver).
Suspend and resume have also been tested, the power button on my remote
can be used to wake the machine, and CIR functionality resumes just
fine. Module unload/reload has also been tested, though not extensively
or repetitively. Also tested to work with the lirc bridge plugin for
userspace decoding.
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-10-07 22:50:34 +02:00
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Get count of how many bytes to read from RX FIFO */
|
|
|
|
fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
|
|
|
|
/* if we get 0xff, probably means the logical dev is disabled */
|
|
|
|
if (fifocount == 0xff)
|
|
|
|
return;
|
2010-10-08 21:16:23 +02:00
|
|
|
/* watch out for a fifo overrun condition */
|
[media] IR: add driver for Nuvoton w836x7hg integrated CIR
This is a new ir-core pnp driver for the Nuvoton w836x7hg integrated CIR
function. The chip is found on at least the ASRock ION 330HT boxes and
apparently, on a number of Intel DP55-series motherboards:
http://www.asrock.com/nettop/overview.asp?Model=ION%20330HT
http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17685&lang=eng
This driver was made possible by a hardware donation from Nuvoton, along
with sample code (in the form of an lirc driver) and datasheet, so huge
thanks to them for supporting this effort. Note that this driver
constitutes a massive rewrite, porting from the lirc interfaces to the
ir-core interfaces, and restructuring the driver to look more like Maxim
Levitsky's ene_ir driver (as well as generally making it look more like
kernel code).
There's some work left to be done on this driver, to fully support the
range of functionality possible, but receive and IR power-on/wake are
both functional (may require setting wake key under another OS atm). The
hardware I've got (one of the ASRock boxes) only supports RX, so TX is
completely untested as of yet. Certain RX parameters, like sample
resolution and RX IRQ sample length trigger level could possibly stand
to be made tweakable via modparams or sysfs nodes, but the current
values work well enough for me w/an MCE RC6A remote.
The original lirc driver carried support for the Windows MCE IR
keyboard/mouse device, which I plan to add back generically, in a way
that should be usable by any raw IR receiver (or at least by this driver
and the mceusb driver).
Suspend and resume have also been tested, the power button on my remote
can be used to wake the machine, and CIR functionality resumes just
fine. Module unload/reload has also been tested, though not extensively
or repetitively. Also tested to work with the lirc bridge plugin for
userspace decoding.
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-10-07 22:50:34 +02:00
|
|
|
else if (fifocount > RX_BUF_LEN) {
|
2010-10-08 21:16:23 +02:00
|
|
|
overrun = true;
|
|
|
|
fifocount = RX_BUF_LEN;
|
[media] IR: add driver for Nuvoton w836x7hg integrated CIR
This is a new ir-core pnp driver for the Nuvoton w836x7hg integrated CIR
function. The chip is found on at least the ASRock ION 330HT boxes and
apparently, on a number of Intel DP55-series motherboards:
http://www.asrock.com/nettop/overview.asp?Model=ION%20330HT
http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17685&lang=eng
This driver was made possible by a hardware donation from Nuvoton, along
with sample code (in the form of an lirc driver) and datasheet, so huge
thanks to them for supporting this effort. Note that this driver
constitutes a massive rewrite, porting from the lirc interfaces to the
ir-core interfaces, and restructuring the driver to look more like Maxim
Levitsky's ene_ir driver (as well as generally making it look more like
kernel code).
There's some work left to be done on this driver, to fully support the
range of functionality possible, but receive and IR power-on/wake are
both functional (may require setting wake key under another OS atm). The
hardware I've got (one of the ASRock boxes) only supports RX, so TX is
completely untested as of yet. Certain RX parameters, like sample
resolution and RX IRQ sample length trigger level could possibly stand
to be made tweakable via modparams or sysfs nodes, but the current
values work well enough for me w/an MCE RC6A remote.
The original lirc driver carried support for the Windows MCE IR
keyboard/mouse device, which I plan to add back generically, in a way
that should be usable by any raw IR receiver (or at least by this driver
and the mceusb driver).
Suspend and resume have also been tested, the power button on my remote
can be used to wake the machine, and CIR functionality resumes just
fine. Module unload/reload has also been tested, though not extensively
or repetitively. Also tested to work with the lirc bridge plugin for
userspace decoding.
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-10-07 22:50:34 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&nvt->nvt_lock, flags);
|
|
|
|
|
|
|
|
b_idx = nvt->pkts;
|
|
|
|
|
|
|
|
/* This should never happen, but lets check anyway... */
|
|
|
|
if (b_idx + fifocount > RX_BUF_LEN) {
|
|
|
|
nvt_process_rx_ir_data(nvt);
|
|
|
|
b_idx = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read fifocount bytes from CIR Sample RX FIFO register */
|
|
|
|
for (i = 0; i < fifocount; i++) {
|
|
|
|
val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
|
|
|
|
nvt->buf[b_idx + i] = val;
|
|
|
|
}
|
|
|
|
|
|
|
|
nvt->pkts += fifocount;
|
|
|
|
nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
|
|
|
|
|
|
|
|
nvt_process_rx_ir_data(nvt);
|
|
|
|
|
2010-10-08 21:16:23 +02:00
|
|
|
if (overrun)
|
|
|
|
nvt_handle_rx_fifo_overrun(nvt);
|
|
|
|
|
[media] IR: add driver for Nuvoton w836x7hg integrated CIR
This is a new ir-core pnp driver for the Nuvoton w836x7hg integrated CIR
function. The chip is found on at least the ASRock ION 330HT boxes and
apparently, on a number of Intel DP55-series motherboards:
http://www.asrock.com/nettop/overview.asp?Model=ION%20330HT
http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17685&lang=eng
This driver was made possible by a hardware donation from Nuvoton, along
with sample code (in the form of an lirc driver) and datasheet, so huge
thanks to them for supporting this effort. Note that this driver
constitutes a massive rewrite, porting from the lirc interfaces to the
ir-core interfaces, and restructuring the driver to look more like Maxim
Levitsky's ene_ir driver (as well as generally making it look more like
kernel code).
There's some work left to be done on this driver, to fully support the
range of functionality possible, but receive and IR power-on/wake are
both functional (may require setting wake key under another OS atm). The
hardware I've got (one of the ASRock boxes) only supports RX, so TX is
completely untested as of yet. Certain RX parameters, like sample
resolution and RX IRQ sample length trigger level could possibly stand
to be made tweakable via modparams or sysfs nodes, but the current
values work well enough for me w/an MCE RC6A remote.
The original lirc driver carried support for the Windows MCE IR
keyboard/mouse device, which I plan to add back generically, in a way
that should be usable by any raw IR receiver (or at least by this driver
and the mceusb driver).
Suspend and resume have also been tested, the power button on my remote
can be used to wake the machine, and CIR functionality resumes just
fine. Module unload/reload has also been tested, though not extensively
or repetitively. Also tested to work with the lirc bridge plugin for
userspace decoding.
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-10-07 22:50:34 +02:00
|
|
|
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void nvt_cir_log_irqs(u8 status, u8 iren)
|
|
|
|
{
|
|
|
|
nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
|
|
|
|
status, iren,
|
|
|
|
status & CIR_IRSTS_RDR ? " RDR" : "",
|
|
|
|
status & CIR_IRSTS_RTR ? " RTR" : "",
|
|
|
|
status & CIR_IRSTS_PE ? " PE" : "",
|
|
|
|
status & CIR_IRSTS_RFO ? " RFO" : "",
|
|
|
|
status & CIR_IRSTS_TE ? " TE" : "",
|
|
|
|
status & CIR_IRSTS_TTR ? " TTR" : "",
|
|
|
|
status & CIR_IRSTS_TFU ? " TFU" : "",
|
|
|
|
status & CIR_IRSTS_GH ? " GH" : "",
|
|
|
|
status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
|
|
|
|
CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
|
|
|
|
CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
bool tx_inactive;
|
|
|
|
u8 tx_state;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&nvt->tx.lock, flags);
|
|
|
|
tx_state = nvt->tx.tx_state;
|
|
|
|
spin_unlock_irqrestore(&nvt->tx.lock, flags);
|
|
|
|
|
|
|
|
tx_inactive = (tx_state == ST_TX_NONE);
|
|
|
|
|
|
|
|
return tx_inactive;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* interrupt service routine for incoming and outgoing CIR data */
|
|
|
|
static irqreturn_t nvt_cir_isr(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct nvt_dev *nvt = data;
|
|
|
|
u8 status, iren, cur_state;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
nvt_dbg_verbose("%s firing", __func__);
|
|
|
|
|
|
|
|
nvt_efm_enable(nvt);
|
|
|
|
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
|
|
|
|
nvt_efm_disable(nvt);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Get IR Status register contents. Write 1 to ack/clear
|
|
|
|
*
|
|
|
|
* bit: reg name - description
|
|
|
|
* 7: CIR_IRSTS_RDR - RX Data Ready
|
|
|
|
* 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
|
|
|
|
* 5: CIR_IRSTS_PE - Packet End
|
|
|
|
* 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
|
|
|
|
* 3: CIR_IRSTS_TE - TX FIFO Empty
|
|
|
|
* 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
|
|
|
|
* 1: CIR_IRSTS_TFU - TX FIFO Underrun
|
|
|
|
* 0: CIR_IRSTS_GH - Min Length Detected
|
|
|
|
*/
|
|
|
|
status = nvt_cir_reg_read(nvt, CIR_IRSTS);
|
|
|
|
if (!status) {
|
|
|
|
nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
|
|
|
|
nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
|
|
|
|
return IRQ_RETVAL(IRQ_NONE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ack/clear all irq flags we've got */
|
|
|
|
nvt_cir_reg_write(nvt, status, CIR_IRSTS);
|
|
|
|
nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
|
|
|
|
|
|
|
|
/* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
|
|
|
|
iren = nvt_cir_reg_read(nvt, CIR_IREN);
|
|
|
|
if (!iren) {
|
|
|
|
nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
|
|
|
|
return IRQ_RETVAL(IRQ_NONE);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
nvt_cir_log_irqs(status, iren);
|
|
|
|
|
|
|
|
if (status & CIR_IRSTS_RTR) {
|
|
|
|
/* FIXME: add code for study/learn mode */
|
|
|
|
/* We only do rx if not tx'ing */
|
|
|
|
if (nvt_cir_tx_inactive(nvt))
|
|
|
|
nvt_get_rx_ir_data(nvt);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & CIR_IRSTS_PE) {
|
|
|
|
if (nvt_cir_tx_inactive(nvt))
|
|
|
|
nvt_get_rx_ir_data(nvt);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&nvt->nvt_lock, flags);
|
|
|
|
|
|
|
|
cur_state = nvt->study_state;
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
|
|
|
|
|
|
|
|
if (cur_state == ST_STUDY_NONE)
|
|
|
|
nvt_clear_cir_fifo(nvt);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & CIR_IRSTS_TE)
|
|
|
|
nvt_clear_tx_fifo(nvt);
|
|
|
|
|
|
|
|
if (status & CIR_IRSTS_TTR) {
|
|
|
|
unsigned int pos, count;
|
|
|
|
u8 tmp;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&nvt->tx.lock, flags);
|
|
|
|
|
|
|
|
pos = nvt->tx.cur_buf_num;
|
|
|
|
count = nvt->tx.buf_count;
|
|
|
|
|
|
|
|
/* Write data into the hardware tx fifo while pos < count */
|
|
|
|
if (pos < count) {
|
|
|
|
nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
|
|
|
|
nvt->tx.cur_buf_num++;
|
|
|
|
/* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
|
|
|
|
} else {
|
|
|
|
tmp = nvt_cir_reg_read(nvt, CIR_IREN);
|
|
|
|
nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&nvt->tx.lock, flags);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & CIR_IRSTS_TFU) {
|
|
|
|
spin_lock_irqsave(&nvt->tx.lock, flags);
|
|
|
|
if (nvt->tx.tx_state == ST_TX_REPLY) {
|
|
|
|
nvt->tx.tx_state = ST_TX_REQUEST;
|
|
|
|
wake_up(&nvt->tx.queue);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&nvt->tx.lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
nvt_dbg_verbose("%s done", __func__);
|
|
|
|
return IRQ_RETVAL(IRQ_HANDLED);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Interrupt service routine for CIR Wake */
|
|
|
|
static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
|
|
|
|
{
|
|
|
|
u8 status, iren, val;
|
|
|
|
struct nvt_dev *nvt = data;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
nvt_dbg_wake("%s firing", __func__);
|
|
|
|
|
|
|
|
status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
|
|
|
|
if (!status)
|
|
|
|
return IRQ_RETVAL(IRQ_NONE);
|
|
|
|
|
|
|
|
if (status & CIR_WAKE_IRSTS_IR_PENDING)
|
|
|
|
nvt_clear_cir_wake_fifo(nvt);
|
|
|
|
|
|
|
|
nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
|
|
|
|
nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
|
|
|
|
|
|
|
|
/* Interrupt may be shared with CIR, bail if Wake not enabled */
|
|
|
|
iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
|
|
|
|
if (!iren) {
|
|
|
|
nvt_dbg_wake("%s exiting, wake not enabled", __func__);
|
|
|
|
return IRQ_RETVAL(IRQ_HANDLED);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((status & CIR_WAKE_IRSTS_PE) &&
|
|
|
|
(nvt->wake_state == ST_WAKE_START)) {
|
|
|
|
while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
|
|
|
|
val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
|
|
|
|
nvt_dbg("setting wake up key: 0x%x", val);
|
|
|
|
}
|
|
|
|
|
|
|
|
nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
|
|
|
|
spin_lock_irqsave(&nvt->nvt_lock, flags);
|
|
|
|
nvt->wake_state = ST_WAKE_FINISH;
|
|
|
|
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
nvt_dbg_wake("%s done", __func__);
|
|
|
|
return IRQ_RETVAL(IRQ_HANDLED);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void nvt_enable_cir(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
/* set function enable flags */
|
|
|
|
nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
|
|
|
|
CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
|
|
|
|
CIR_IRCON);
|
|
|
|
|
|
|
|
nvt_efm_enable(nvt);
|
|
|
|
|
|
|
|
/* enable the CIR logical device */
|
|
|
|
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
|
|
|
|
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
|
|
|
|
|
|
|
|
nvt_efm_disable(nvt);
|
|
|
|
|
|
|
|
/* clear all pending interrupts */
|
|
|
|
nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
|
|
|
|
|
|
|
|
/* enable interrupts */
|
2010-10-08 21:16:23 +02:00
|
|
|
nvt_set_cir_iren(nvt);
|
[media] IR: add driver for Nuvoton w836x7hg integrated CIR
This is a new ir-core pnp driver for the Nuvoton w836x7hg integrated CIR
function. The chip is found on at least the ASRock ION 330HT boxes and
apparently, on a number of Intel DP55-series motherboards:
http://www.asrock.com/nettop/overview.asp?Model=ION%20330HT
http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17685&lang=eng
This driver was made possible by a hardware donation from Nuvoton, along
with sample code (in the form of an lirc driver) and datasheet, so huge
thanks to them for supporting this effort. Note that this driver
constitutes a massive rewrite, porting from the lirc interfaces to the
ir-core interfaces, and restructuring the driver to look more like Maxim
Levitsky's ene_ir driver (as well as generally making it look more like
kernel code).
There's some work left to be done on this driver, to fully support the
range of functionality possible, but receive and IR power-on/wake are
both functional (may require setting wake key under another OS atm). The
hardware I've got (one of the ASRock boxes) only supports RX, so TX is
completely untested as of yet. Certain RX parameters, like sample
resolution and RX IRQ sample length trigger level could possibly stand
to be made tweakable via modparams or sysfs nodes, but the current
values work well enough for me w/an MCE RC6A remote.
The original lirc driver carried support for the Windows MCE IR
keyboard/mouse device, which I plan to add back generically, in a way
that should be usable by any raw IR receiver (or at least by this driver
and the mceusb driver).
Suspend and resume have also been tested, the power button on my remote
can be used to wake the machine, and CIR functionality resumes just
fine. Module unload/reload has also been tested, though not extensively
or repetitively. Also tested to work with the lirc bridge plugin for
userspace decoding.
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-10-07 22:50:34 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void nvt_disable_cir(struct nvt_dev *nvt)
|
|
|
|
{
|
|
|
|
/* disable CIR interrupts */
|
|
|
|
nvt_cir_reg_write(nvt, 0, CIR_IREN);
|
|
|
|
|
|
|
|
/* clear any and all pending interrupts */
|
|
|
|
nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
|
|
|
|
|
|
|
|
/* clear all function enable flags */
|
|
|
|
nvt_cir_reg_write(nvt, 0, CIR_IRCON);
|
|
|
|
|
|
|
|
/* clear hardware rx and tx fifos */
|
|
|
|
nvt_clear_cir_fifo(nvt);
|
|
|
|
nvt_clear_tx_fifo(nvt);
|
|
|
|
|
|
|
|
nvt_efm_enable(nvt);
|
|
|
|
|
|
|
|
/* disable the CIR logical device */
|
|
|
|
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
|
|
|
|
nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
|
|
|
|
|
|
|
|
nvt_efm_disable(nvt);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int nvt_open(void *data)
|
|
|
|
{
|
|
|
|
struct nvt_dev *nvt = (struct nvt_dev *)data;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&nvt->nvt_lock, flags);
|
|
|
|
nvt->in_use = true;
|
|
|
|
nvt_enable_cir(nvt);
|
|
|
|
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void nvt_close(void *data)
|
|
|
|
{
|
|
|
|
struct nvt_dev *nvt = (struct nvt_dev *)data;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&nvt->nvt_lock, flags);
|
|
|
|
nvt->in_use = false;
|
|
|
|
nvt_disable_cir(nvt);
|
|
|
|
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Allocate memory, probe hardware, and initialize everything */
|
|
|
|
static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
|
|
|
|
{
|
|
|
|
struct nvt_dev *nvt = NULL;
|
|
|
|
struct input_dev *rdev = NULL;
|
|
|
|
struct ir_dev_props *props = NULL;
|
|
|
|
int ret = -ENOMEM;
|
|
|
|
|
|
|
|
nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
|
|
|
|
if (!nvt)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
props = kzalloc(sizeof(struct ir_dev_props), GFP_KERNEL);
|
|
|
|
if (!props)
|
|
|
|
goto failure;
|
|
|
|
|
|
|
|
/* input device for IR remote (and tx) */
|
|
|
|
rdev = input_allocate_device();
|
|
|
|
if (!rdev)
|
|
|
|
goto failure;
|
|
|
|
|
|
|
|
ret = -ENODEV;
|
|
|
|
/* validate pnp resources */
|
|
|
|
if (!pnp_port_valid(pdev, 0) ||
|
|
|
|
pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
|
|
|
|
dev_err(&pdev->dev, "IR PNP Port not valid!\n");
|
|
|
|
goto failure;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!pnp_irq_valid(pdev, 0)) {
|
|
|
|
dev_err(&pdev->dev, "PNP IRQ not valid!\n");
|
|
|
|
goto failure;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!pnp_port_valid(pdev, 1) ||
|
|
|
|
pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
|
|
|
|
dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
|
|
|
|
goto failure;
|
|
|
|
}
|
|
|
|
|
|
|
|
nvt->cir_addr = pnp_port_start(pdev, 0);
|
|
|
|
nvt->cir_irq = pnp_irq(pdev, 0);
|
|
|
|
|
|
|
|
nvt->cir_wake_addr = pnp_port_start(pdev, 1);
|
|
|
|
/* irq is always shared between cir and cir wake */
|
|
|
|
nvt->cir_wake_irq = nvt->cir_irq;
|
|
|
|
|
|
|
|
nvt->cr_efir = CR_EFIR;
|
|
|
|
nvt->cr_efdr = CR_EFDR;
|
|
|
|
|
|
|
|
spin_lock_init(&nvt->nvt_lock);
|
|
|
|
spin_lock_init(&nvt->tx.lock);
|
|
|
|
|
|
|
|
ret = -EBUSY;
|
|
|
|
/* now claim resources */
|
|
|
|
if (!request_region(nvt->cir_addr,
|
|
|
|
CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
|
|
|
|
goto failure;
|
|
|
|
|
|
|
|
if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
|
|
|
|
NVT_DRIVER_NAME, (void *)nvt))
|
|
|
|
goto failure;
|
|
|
|
|
|
|
|
if (!request_region(nvt->cir_wake_addr,
|
|
|
|
CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
|
|
|
|
goto failure;
|
|
|
|
|
|
|
|
if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
|
|
|
|
NVT_DRIVER_NAME, (void *)nvt))
|
|
|
|
goto failure;
|
|
|
|
|
|
|
|
pnp_set_drvdata(pdev, nvt);
|
|
|
|
nvt->pdev = pdev;
|
|
|
|
|
|
|
|
init_waitqueue_head(&nvt->tx.queue);
|
|
|
|
|
|
|
|
ret = nvt_hw_detect(nvt);
|
|
|
|
if (ret)
|
|
|
|
goto failure;
|
|
|
|
|
|
|
|
/* Initialize CIR & CIR Wake Logical Devices */
|
|
|
|
nvt_efm_enable(nvt);
|
|
|
|
nvt_cir_ldev_init(nvt);
|
|
|
|
nvt_cir_wake_ldev_init(nvt);
|
|
|
|
nvt_efm_disable(nvt);
|
|
|
|
|
|
|
|
/* Initialize CIR & CIR Wake Config Registers */
|
|
|
|
nvt_cir_regs_init(nvt);
|
|
|
|
nvt_cir_wake_regs_init(nvt);
|
|
|
|
|
|
|
|
/* Set up ir-core props */
|
|
|
|
props->priv = nvt;
|
|
|
|
props->driver_type = RC_DRIVER_IR_RAW;
|
|
|
|
props->allowed_protos = IR_TYPE_ALL;
|
|
|
|
props->open = nvt_open;
|
|
|
|
props->close = nvt_close;
|
|
|
|
#if 0
|
|
|
|
props->min_timeout = XYZ;
|
|
|
|
props->max_timeout = XYZ;
|
|
|
|
props->timeout = XYZ;
|
|
|
|
/* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
|
|
|
|
props->rx_resolution = XYZ;
|
|
|
|
|
|
|
|
/* tx bits */
|
|
|
|
props->tx_resolution = XYZ;
|
|
|
|
#endif
|
|
|
|
props->tx_ir = nvt_tx_ir;
|
|
|
|
props->s_tx_carrier = nvt_set_tx_carrier;
|
|
|
|
|
|
|
|
rdev->name = "Nuvoton w836x7hg Infrared Remote Transceiver";
|
|
|
|
rdev->id.bustype = BUS_HOST;
|
|
|
|
rdev->id.vendor = PCI_VENDOR_ID_WINBOND2;
|
|
|
|
rdev->id.product = nvt->chip_major;
|
|
|
|
rdev->id.version = nvt->chip_minor;
|
|
|
|
|
|
|
|
nvt->props = props;
|
|
|
|
nvt->rdev = rdev;
|
|
|
|
|
|
|
|
device_set_wakeup_capable(&pdev->dev, 1);
|
|
|
|
device_set_wakeup_enable(&pdev->dev, 1);
|
|
|
|
|
|
|
|
ret = ir_input_register(rdev, RC_MAP_RC6_MCE, props, NVT_DRIVER_NAME);
|
|
|
|
if (ret)
|
|
|
|
goto failure;
|
|
|
|
|
|
|
|
nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
|
|
|
|
if (debug) {
|
|
|
|
cir_dump_regs(nvt);
|
|
|
|
cir_wake_dump_regs(nvt);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
failure:
|
|
|
|
if (nvt->cir_irq)
|
|
|
|
free_irq(nvt->cir_irq, nvt);
|
|
|
|
if (nvt->cir_addr)
|
|
|
|
release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
|
|
|
|
|
|
|
|
if (nvt->cir_wake_irq)
|
|
|
|
free_irq(nvt->cir_wake_irq, nvt);
|
|
|
|
if (nvt->cir_wake_addr)
|
|
|
|
release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
|
|
|
|
|
|
|
|
input_free_device(rdev);
|
|
|
|
kfree(props);
|
|
|
|
kfree(nvt);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __devexit nvt_remove(struct pnp_dev *pdev)
|
|
|
|
{
|
|
|
|
struct nvt_dev *nvt = pnp_get_drvdata(pdev);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&nvt->nvt_lock, flags);
|
|
|
|
/* disable CIR */
|
|
|
|
nvt_cir_reg_write(nvt, 0, CIR_IREN);
|
|
|
|
nvt_disable_cir(nvt);
|
|
|
|
/* enable CIR Wake (for IR power-on) */
|
|
|
|
nvt_enable_wake(nvt);
|
|
|
|
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
|
|
|
|
|
|
|
|
/* free resources */
|
|
|
|
free_irq(nvt->cir_irq, nvt);
|
|
|
|
free_irq(nvt->cir_wake_irq, nvt);
|
|
|
|
release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
|
|
|
|
release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
|
|
|
|
|
|
|
|
ir_input_unregister(nvt->rdev);
|
|
|
|
|
|
|
|
kfree(nvt->props);
|
|
|
|
kfree(nvt);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
|
|
|
|
{
|
|
|
|
struct nvt_dev *nvt = pnp_get_drvdata(pdev);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
nvt_dbg("%s called", __func__);
|
|
|
|
|
|
|
|
/* zero out misc state tracking */
|
|
|
|
spin_lock_irqsave(&nvt->nvt_lock, flags);
|
|
|
|
nvt->study_state = ST_STUDY_NONE;
|
|
|
|
nvt->wake_state = ST_WAKE_NONE;
|
|
|
|
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&nvt->tx.lock, flags);
|
|
|
|
nvt->tx.tx_state = ST_TX_NONE;
|
|
|
|
spin_unlock_irqrestore(&nvt->tx.lock, flags);
|
|
|
|
|
|
|
|
/* disable all CIR interrupts */
|
|
|
|
nvt_cir_reg_write(nvt, 0, CIR_IREN);
|
|
|
|
|
|
|
|
nvt_efm_enable(nvt);
|
|
|
|
|
|
|
|
/* disable cir logical dev */
|
|
|
|
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
|
|
|
|
nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
|
|
|
|
|
|
|
|
nvt_efm_disable(nvt);
|
|
|
|
|
|
|
|
/* make sure wake is enabled */
|
|
|
|
nvt_enable_wake(nvt);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int nvt_resume(struct pnp_dev *pdev)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
struct nvt_dev *nvt = pnp_get_drvdata(pdev);
|
|
|
|
|
|
|
|
nvt_dbg("%s called", __func__);
|
|
|
|
|
|
|
|
/* open interrupt */
|
2010-10-08 21:16:23 +02:00
|
|
|
nvt_set_cir_iren(nvt);
|
[media] IR: add driver for Nuvoton w836x7hg integrated CIR
This is a new ir-core pnp driver for the Nuvoton w836x7hg integrated CIR
function. The chip is found on at least the ASRock ION 330HT boxes and
apparently, on a number of Intel DP55-series motherboards:
http://www.asrock.com/nettop/overview.asp?Model=ION%20330HT
http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17685&lang=eng
This driver was made possible by a hardware donation from Nuvoton, along
with sample code (in the form of an lirc driver) and datasheet, so huge
thanks to them for supporting this effort. Note that this driver
constitutes a massive rewrite, porting from the lirc interfaces to the
ir-core interfaces, and restructuring the driver to look more like Maxim
Levitsky's ene_ir driver (as well as generally making it look more like
kernel code).
There's some work left to be done on this driver, to fully support the
range of functionality possible, but receive and IR power-on/wake are
both functional (may require setting wake key under another OS atm). The
hardware I've got (one of the ASRock boxes) only supports RX, so TX is
completely untested as of yet. Certain RX parameters, like sample
resolution and RX IRQ sample length trigger level could possibly stand
to be made tweakable via modparams or sysfs nodes, but the current
values work well enough for me w/an MCE RC6A remote.
The original lirc driver carried support for the Windows MCE IR
keyboard/mouse device, which I plan to add back generically, in a way
that should be usable by any raw IR receiver (or at least by this driver
and the mceusb driver).
Suspend and resume have also been tested, the power button on my remote
can be used to wake the machine, and CIR functionality resumes just
fine. Module unload/reload has also been tested, though not extensively
or repetitively. Also tested to work with the lirc bridge plugin for
userspace decoding.
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-10-07 22:50:34 +02:00
|
|
|
|
|
|
|
/* Enable CIR logical device */
|
|
|
|
nvt_efm_enable(nvt);
|
|
|
|
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
|
|
|
|
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
|
|
|
|
|
|
|
|
nvt_efm_disable(nvt);
|
|
|
|
|
|
|
|
nvt_cir_regs_init(nvt);
|
|
|
|
nvt_cir_wake_regs_init(nvt);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void nvt_shutdown(struct pnp_dev *pdev)
|
|
|
|
{
|
|
|
|
struct nvt_dev *nvt = pnp_get_drvdata(pdev);
|
|
|
|
nvt_enable_wake(nvt);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct pnp_device_id nvt_ids[] = {
|
|
|
|
{ "WEC0530", 0 }, /* CIR */
|
|
|
|
{ "NTN0530", 0 }, /* CIR for new chip's pnp id*/
|
|
|
|
{ "", 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pnp_driver nvt_driver = {
|
|
|
|
.name = NVT_DRIVER_NAME,
|
|
|
|
.id_table = nvt_ids,
|
|
|
|
.flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
|
|
|
|
.probe = nvt_probe,
|
|
|
|
.remove = __devexit_p(nvt_remove),
|
|
|
|
.suspend = nvt_suspend,
|
|
|
|
.resume = nvt_resume,
|
|
|
|
.shutdown = nvt_shutdown,
|
|
|
|
};
|
|
|
|
|
|
|
|
int nvt_init(void)
|
|
|
|
{
|
|
|
|
return pnp_register_driver(&nvt_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
void nvt_exit(void)
|
|
|
|
{
|
|
|
|
pnp_unregister_driver(&nvt_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_param(debug, int, S_IRUGO | S_IWUSR);
|
|
|
|
MODULE_PARM_DESC(debug, "Enable debugging output");
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(pnp, nvt_ids);
|
|
|
|
MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
|
|
|
module_init(nvt_init);
|
|
|
|
module_exit(nvt_exit);
|