2014-01-15 11:31:53 +01:00
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <asm/cacheflush.h>
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#include <asm/gic.h>
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#include <asm/mips-cm.h>
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#include <asm/mips-cpc.h>
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#include <asm/mips_mt.h>
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#include <asm/mipsregs.h>
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#include <asm/smp-cps.h>
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#include <asm/time.h>
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#include <asm/uasm.h>
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static DECLARE_BITMAP(core_power, NR_CPUS);
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2014-04-14 13:04:27 +02:00
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struct core_boot_config *mips_cps_core_bootcfg;
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2014-01-15 11:31:53 +01:00
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2014-04-14 13:04:27 +02:00
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static unsigned core_vpe_count(unsigned core)
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2014-01-15 11:31:53 +01:00
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{
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2014-04-14 13:04:27 +02:00
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unsigned cfg;
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2014-01-15 11:31:53 +01:00
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2014-04-14 13:04:27 +02:00
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if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
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return 1;
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2014-01-15 11:31:53 +01:00
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2014-04-14 13:04:27 +02:00
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write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
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cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
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return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
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2014-01-15 11:31:53 +01:00
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}
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static void __init cps_smp_setup(void)
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{
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unsigned int ncores, nvpes, core_vpes;
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int c, v;
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/* Detect & record VPE topology */
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ncores = mips_cm_numcores();
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pr_info("VPE topology ");
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for (c = nvpes = 0; c < ncores; c++) {
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2014-04-14 13:04:27 +02:00
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core_vpes = core_vpe_count(c);
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2014-01-15 11:31:53 +01:00
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pr_cont("%c%u", c ? ',' : '{', core_vpes);
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2014-04-14 13:04:27 +02:00
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/* Use the number of VPEs in core 0 for smp_num_siblings */
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if (!c)
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smp_num_siblings = core_vpes;
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2014-01-15 11:31:53 +01:00
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for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
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cpu_data[nvpes + v].core = c;
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#ifdef CONFIG_MIPS_MT_SMP
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cpu_data[nvpes + v].vpe_id = v;
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#endif
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}
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nvpes += core_vpes;
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}
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pr_cont("} total %u\n", nvpes);
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/* Indicate present CPUs (CPU being synonymous with VPE) */
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for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
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set_cpu_possible(v, true);
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set_cpu_present(v, true);
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__cpu_number_map[v] = v;
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__cpu_logical_map[v] = v;
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}
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/* Core 0 is powered up (we're running on it) */
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bitmap_set(core_power, 0, 1);
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/* Initialise core 0 */
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2014-04-14 13:04:27 +02:00
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mips_cps_core_init();
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2014-01-15 11:31:53 +01:00
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/* Make core 0 coherent with everything */
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write_gcr_cl_coherence(0xff);
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}
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static void __init cps_prepare_cpus(unsigned int max_cpus)
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{
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2014-04-14 13:04:27 +02:00
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unsigned ncores, core_vpes, c;
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2014-04-14 13:21:49 +02:00
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u32 *entry_code;
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2014-04-14 13:04:27 +02:00
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2014-01-15 11:31:53 +01:00
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mips_mt_set_cpuoptions();
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2014-04-14 13:04:27 +02:00
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2014-04-14 13:21:49 +02:00
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/* Patch the start of mips_cps_core_entry to provide the CM base */
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entry_code = (u32 *)&mips_cps_core_entry;
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UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
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dma_cache_wback_inv((unsigned long)&mips_cps_core_entry,
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(void *)entry_code - (void *)&mips_cps_core_entry);
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2014-04-14 13:04:27 +02:00
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/* Allocate core boot configuration structs */
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ncores = mips_cm_numcores();
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mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
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GFP_KERNEL);
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if (!mips_cps_core_bootcfg) {
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pr_err("Failed to allocate boot config for %u cores\n", ncores);
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goto err_out;
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}
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/* Allocate VPE boot configuration structs */
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for (c = 0; c < ncores; c++) {
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core_vpes = core_vpe_count(c);
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mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
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sizeof(*mips_cps_core_bootcfg[c].vpe_config),
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GFP_KERNEL);
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if (!mips_cps_core_bootcfg[c].vpe_config) {
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pr_err("Failed to allocate %u VPE boot configs\n",
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core_vpes);
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goto err_out;
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}
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}
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/* Mark this CPU as booted */
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atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
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1 << cpu_vpe_id(¤t_cpu_data));
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return;
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err_out:
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/* Clean up allocations */
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if (mips_cps_core_bootcfg) {
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for (c = 0; c < ncores; c++)
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kfree(mips_cps_core_bootcfg[c].vpe_config);
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kfree(mips_cps_core_bootcfg);
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mips_cps_core_bootcfg = NULL;
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}
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/* Effectively disable SMP by declaring CPUs not present */
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for_each_possible_cpu(c) {
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if (c == 0)
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continue;
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set_cpu_present(c, false);
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}
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2014-01-15 11:31:53 +01:00
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}
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2014-04-14 13:04:27 +02:00
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static void boot_core(unsigned core)
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2014-01-15 11:31:53 +01:00
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{
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u32 access;
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/* Select the appropriate core */
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2014-04-14 13:04:27 +02:00
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write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
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2014-01-15 11:31:53 +01:00
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/* Set its reset vector */
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write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
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/* Ensure its coherency is disabled */
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write_gcr_co_coherence(0);
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/* Ensure the core can access the GCRs */
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access = read_gcr_access();
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2014-04-14 13:04:27 +02:00
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access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
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2014-01-15 11:31:53 +01:00
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write_gcr_access(access);
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if (mips_cpc_present()) {
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/* Select the appropriate core */
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2014-04-14 13:04:27 +02:00
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write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF);
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2014-01-15 11:31:53 +01:00
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/* Reset the core */
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write_cpc_co_cmd(CPC_Cx_CMD_RESET);
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} else {
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/* Take the core out of reset */
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write_gcr_co_reset_release(0);
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}
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/* The core is now powered up */
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2014-04-14 13:04:27 +02:00
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bitmap_set(core_power, core, 1);
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2014-01-15 11:31:53 +01:00
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}
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2014-04-14 13:04:27 +02:00
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static void remote_vpe_boot(void *dummy)
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2014-01-15 11:31:53 +01:00
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{
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2014-04-14 13:04:27 +02:00
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mips_cps_boot_vpes();
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2014-01-15 11:31:53 +01:00
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}
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static void cps_boot_secondary(int cpu, struct task_struct *idle)
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{
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2014-04-14 13:04:27 +02:00
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unsigned core = cpu_data[cpu].core;
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unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
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struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
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struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
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2014-01-15 11:31:53 +01:00
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unsigned int remote;
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int err;
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2014-04-14 13:04:27 +02:00
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vpe_cfg->pc = (unsigned long)&smp_bootstrap;
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vpe_cfg->sp = __KSTK_TOS(idle);
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vpe_cfg->gp = (unsigned long)task_thread_info(idle);
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2014-01-15 11:31:53 +01:00
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2014-04-14 13:04:27 +02:00
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atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
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if (!test_bit(core, core_power)) {
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2014-01-15 11:31:53 +01:00
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/* Boot a VPE on a powered down core */
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2014-04-14 13:04:27 +02:00
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boot_core(core);
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2014-01-15 11:31:53 +01:00
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return;
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}
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2014-04-14 13:04:27 +02:00
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if (core != current_cpu_data.core) {
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2014-01-15 11:31:53 +01:00
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/* Boot a VPE on another powered up core */
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for (remote = 0; remote < NR_CPUS; remote++) {
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2014-04-14 13:04:27 +02:00
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if (cpu_data[remote].core != core)
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2014-01-15 11:31:53 +01:00
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continue;
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if (cpu_online(remote))
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break;
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}
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BUG_ON(remote >= NR_CPUS);
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2014-04-14 13:04:27 +02:00
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err = smp_call_function_single(remote, remote_vpe_boot,
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NULL, 1);
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2014-01-15 11:31:53 +01:00
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if (err)
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panic("Failed to call remote CPU\n");
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return;
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}
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BUG_ON(!cpu_has_mipsmt);
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/* Boot a VPE on this core */
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2014-04-14 13:04:27 +02:00
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mips_cps_boot_vpes();
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2014-01-15 11:31:53 +01:00
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}
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static void cps_init_secondary(void)
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{
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/* Disable MT - we only want to run 1 TC per VPE */
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if (cpu_has_mipsmt)
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dmt();
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change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
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STATUSF_IP6 | STATUSF_IP7);
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}
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static void cps_smp_finish(void)
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{
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write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* If we have an FPU, enroll ourselves in the FPU-full mask */
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if (cpu_has_fpu)
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cpu_set(smp_processor_id(), mt_fpu_cpumask);
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#endif /* CONFIG_MIPS_MT_FPAFF */
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local_irq_enable();
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}
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static void cps_cpus_done(void)
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{
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}
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static struct plat_smp_ops cps_smp_ops = {
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.smp_setup = cps_smp_setup,
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.prepare_cpus = cps_prepare_cpus,
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.boot_secondary = cps_boot_secondary,
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.init_secondary = cps_init_secondary,
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.smp_finish = cps_smp_finish,
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.send_ipi_single = gic_send_ipi_single,
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.send_ipi_mask = gic_send_ipi_mask,
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.cpus_done = cps_cpus_done,
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};
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2014-03-14 17:06:16 +01:00
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bool mips_cps_smp_in_use(void)
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{
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extern struct plat_smp_ops *mp_ops;
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return mp_ops == &cps_smp_ops;
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}
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2014-01-15 11:31:53 +01:00
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int register_cps_smp_ops(void)
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{
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if (!mips_cm_present()) {
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pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
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return -ENODEV;
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}
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/* check we have a GIC - we need one for IPIs */
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if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
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pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
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return -ENODEV;
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}
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register_smp_ops(&cps_smp_ops);
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return 0;
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}
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