2005-04-17 00:20:36 +02:00
|
|
|
/*
|
|
|
|
* Architecture-specific setup.
|
|
|
|
*
|
|
|
|
* Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
|
|
|
|
* David Mosberger-Tang <davidm@hpl.hp.com>
|
|
|
|
* Stephane Eranian <eranian@hpl.hp.com>
|
2005-04-25 22:25:06 +02:00
|
|
|
* Copyright (C) 2000, 2004 Intel Corp
|
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|
|
* Rohit Seth <rohit.seth@intel.com>
|
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|
|
* Suresh Siddha <suresh.b.siddha@intel.com>
|
|
|
|
* Gordon Jin <gordon.jin@intel.com>
|
2005-04-17 00:20:36 +02:00
|
|
|
* Copyright (C) 1999 VA Linux Systems
|
|
|
|
* Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
|
|
|
|
*
|
2005-04-25 22:25:06 +02:00
|
|
|
* 12/26/04 S.Siddha, G.Jin, R.Seth
|
|
|
|
* Add multi-threading and multi-core detection
|
2005-04-17 00:20:36 +02:00
|
|
|
* 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
|
|
|
|
* 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
|
|
|
|
* 03/31/00 R.Seth cpu_initialized and current->processor fixes
|
|
|
|
* 02/04/00 D.Mosberger some more get_cpuinfo fixes...
|
|
|
|
* 02/01/00 R.Seth fixed get_cpuinfo for SMP
|
|
|
|
* 01/07/99 S.Eranian added the support for command line argument
|
|
|
|
* 06/24/99 W.Drummond added boot_cpu_data.
|
2005-06-03 14:36:00 +02:00
|
|
|
* 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
|
2005-04-17 00:20:36 +02:00
|
|
|
*/
|
|
|
|
#include <linux/config.h>
|
|
|
|
#include <linux/module.h>
|
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|
|
#include <linux/init.h>
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|
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|
|
#include <linux/acpi.h>
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|
|
#include <linux/bootmem.h>
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|
|
#include <linux/console.h>
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|
|
#include <linux/delay.h>
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|
|
|
#include <linux/kernel.h>
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|
|
#include <linux/reboot.h>
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|
|
#include <linux/sched.h>
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|
|
#include <linux/seq_file.h>
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|
|
|
#include <linux/string.h>
|
|
|
|
#include <linux/threads.h>
|
|
|
|
#include <linux/tty.h>
|
[PATCH] ia64: use i386 dmi_scan.c
Enable DMI table parsing on ia64.
Andi Kleen has a patch in his x86_64 tree which enables the use of i386
dmi_scan.c on x86_64. dmi_scan.c functions are being used by the
drivers/char/ipmi/ipmi_si_intf.c driver for autodetecting the ports or
memory spaces where the IPMI controllers may be found.
This patch adds equivalent changes for ia64 as to what is in the x86_64
tree. In addition, I reworked the DMI detection, such that on EFI-capable
systems, it uses the efi.smbios pointer to find the table, rather than
brute-force searching from 0xF0000. On non-EFI systems, it continues the
brute-force search.
My test system, an Intel S870BN4 'Tiger4', aka Dell PowerEdge 7250, with
latest BIOS, does not list the IPMI controller in the ACPI namespace, nor
does it have an ACPI SPMI table. Also note, currently shipping Dell x8xx
EM64T servers don't have these either, so DMI is the only method for
obtaining the address of the IPMI controller.
Signed-off-by: Matt Domsch <Matt_Domsch@dell.com>
Acked-by: "Luck, Tony" <tony.luck@intel.com>
Cc: Andi Kleen <ak@muc.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-26 11:37:03 +02:00
|
|
|
#include <linux/dmi.h>
|
2005-04-17 00:20:36 +02:00
|
|
|
#include <linux/serial.h>
|
|
|
|
#include <linux/serial_core.h>
|
|
|
|
#include <linux/efi.h>
|
|
|
|
#include <linux/initrd.h>
|
2005-04-19 05:06:47 +02:00
|
|
|
#include <linux/pm.h>
|
2005-12-02 19:43:20 +01:00
|
|
|
#include <linux/cpufreq.h>
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
#include <asm/ia32.h>
|
|
|
|
#include <asm/machvec.h>
|
|
|
|
#include <asm/mca.h>
|
|
|
|
#include <asm/meminit.h>
|
|
|
|
#include <asm/page.h>
|
|
|
|
#include <asm/patch.h>
|
|
|
|
#include <asm/pgtable.h>
|
|
|
|
#include <asm/processor.h>
|
|
|
|
#include <asm/sal.h>
|
|
|
|
#include <asm/sections.h>
|
|
|
|
#include <asm/serial.h>
|
|
|
|
#include <asm/setup.h>
|
|
|
|
#include <asm/smp.h>
|
|
|
|
#include <asm/system.h>
|
|
|
|
#include <asm/unistd.h>
|
2006-01-12 10:05:27 +01:00
|
|
|
#include <asm/system.h>
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
#if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
|
|
|
|
# error "struct cpuinfo_ia64 too big!"
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
unsigned long __per_cpu_offset[NR_CPUS];
|
|
|
|
EXPORT_SYMBOL(__per_cpu_offset);
|
|
|
|
#endif
|
|
|
|
|
2006-02-08 00:25:57 +01:00
|
|
|
extern void ia64_setup_printk_clock(void);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
|
|
|
|
DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
|
|
|
|
DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
|
|
|
|
unsigned long ia64_cycles_per_usec;
|
|
|
|
struct ia64_boot_param *ia64_boot_param;
|
|
|
|
struct screen_info screen_info;
|
2005-04-25 22:51:00 +02:00
|
|
|
unsigned long vga_console_iobase;
|
|
|
|
unsigned long vga_console_membase;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-09-20 00:42:36 +02:00
|
|
|
static struct resource data_resource = {
|
|
|
|
.name = "Kernel data",
|
|
|
|
.flags = IORESOURCE_BUSY | IORESOURCE_MEM
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct resource code_resource = {
|
|
|
|
.name = "Kernel code",
|
|
|
|
.flags = IORESOURCE_BUSY | IORESOURCE_MEM
|
|
|
|
};
|
|
|
|
extern void efi_initialize_iomem_resources(struct resource *,
|
|
|
|
struct resource *);
|
2005-09-29 01:09:46 +02:00
|
|
|
extern char _text[], _end[], _etext[];
|
2005-09-20 00:42:36 +02:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
unsigned long ia64_max_cacheline_size;
|
2005-11-07 09:57:54 +01:00
|
|
|
|
|
|
|
int dma_get_cache_alignment(void)
|
|
|
|
{
|
|
|
|
return ia64_max_cacheline_size;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dma_get_cache_alignment);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
unsigned long ia64_iobase; /* virtual address for I/O accesses */
|
|
|
|
EXPORT_SYMBOL(ia64_iobase);
|
|
|
|
struct io_space io_space[MAX_IO_SPACES];
|
|
|
|
EXPORT_SYMBOL(io_space);
|
|
|
|
unsigned int num_io_spaces;
|
|
|
|
|
2005-06-03 14:36:00 +02:00
|
|
|
/*
|
|
|
|
* "flush_icache_range()" needs to know what processor dependent stride size to use
|
|
|
|
* when it makes i-cache(s) coherent with d-caches.
|
|
|
|
*/
|
|
|
|
#define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
|
|
|
|
unsigned long ia64_i_cache_stride_shift = ~0;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/*
|
|
|
|
* The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
|
|
|
|
* mask specifies a mask of address bits that must be 0 in order for two buffers to be
|
|
|
|
* mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
|
|
|
|
* address of the second buffer must be aligned to (merge_mask+1) in order to be
|
|
|
|
* mergeable). By default, we assume there is no I/O MMU which can merge physically
|
|
|
|
* discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
|
|
|
|
* page-size of 2^64.
|
|
|
|
*/
|
|
|
|
unsigned long ia64_max_iommu_merge_mask = ~0UL;
|
|
|
|
EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We use a special marker for the end of memory and it uses the extra (+1) slot
|
|
|
|
*/
|
2006-03-23 01:54:15 +01:00
|
|
|
struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
|
|
|
|
int num_rsvd_regions __initdata;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Filter incoming memory segments based on the primitive map created from the boot
|
|
|
|
* parameters. Segments contained in the map are removed from the memory ranges. A
|
|
|
|
* caller-specified function is called with the memory ranges that remain after filtering.
|
|
|
|
* This routine does not assume the incoming segments are sorted.
|
|
|
|
*/
|
2006-03-23 01:54:15 +01:00
|
|
|
int __init
|
2005-04-17 00:20:36 +02:00
|
|
|
filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
|
|
|
|
{
|
|
|
|
unsigned long range_start, range_end, prev_start;
|
|
|
|
void (*func)(unsigned long, unsigned long, int);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
#if IGNORE_PFN0
|
|
|
|
if (start == PAGE_OFFSET) {
|
|
|
|
printk(KERN_WARNING "warning: skipping physical page 0\n");
|
|
|
|
start += PAGE_SIZE;
|
|
|
|
if (start >= end) return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
/*
|
|
|
|
* lowest possible address(walker uses virtual)
|
|
|
|
*/
|
|
|
|
prev_start = PAGE_OFFSET;
|
|
|
|
func = arg;
|
|
|
|
|
|
|
|
for (i = 0; i < num_rsvd_regions; ++i) {
|
|
|
|
range_start = max(start, prev_start);
|
|
|
|
range_end = min(end, rsvd_region[i].start);
|
|
|
|
|
|
|
|
if (range_start < range_end)
|
|
|
|
call_pernode_memory(__pa(range_start), range_end - range_start, func);
|
|
|
|
|
|
|
|
/* nothing more available in this segment */
|
|
|
|
if (range_end == end) return 0;
|
|
|
|
|
|
|
|
prev_start = rsvd_region[i].end;
|
|
|
|
}
|
|
|
|
/* end of memory marker allows full processing inside loop body */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-03-23 01:54:15 +01:00
|
|
|
static void __init
|
2005-04-17 00:20:36 +02:00
|
|
|
sort_regions (struct rsvd_region *rsvd_region, int max)
|
|
|
|
{
|
|
|
|
int j;
|
|
|
|
|
|
|
|
/* simple bubble sorting */
|
|
|
|
while (max--) {
|
|
|
|
for (j = 0; j < max; ++j) {
|
|
|
|
if (rsvd_region[j].start > rsvd_region[j+1].start) {
|
|
|
|
struct rsvd_region tmp;
|
|
|
|
tmp = rsvd_region[j];
|
|
|
|
rsvd_region[j] = rsvd_region[j + 1];
|
|
|
|
rsvd_region[j + 1] = tmp;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-09-20 00:42:36 +02:00
|
|
|
/*
|
|
|
|
* Request address space for all standard resources
|
|
|
|
*/
|
|
|
|
static int __init register_memory(void)
|
|
|
|
{
|
|
|
|
code_resource.start = ia64_tpa(_text);
|
|
|
|
code_resource.end = ia64_tpa(_etext) - 1;
|
|
|
|
data_resource.start = ia64_tpa(_etext);
|
2005-09-29 01:09:46 +02:00
|
|
|
data_resource.end = ia64_tpa(_end) - 1;
|
2005-09-20 00:42:36 +02:00
|
|
|
efi_initialize_iomem_resources(&code_resource, &data_resource);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
__initcall(register_memory);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* reserve_memory - setup reserved memory areas
|
|
|
|
*
|
|
|
|
* Setup the reserved memory areas set aside for the boot parameters,
|
|
|
|
* initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
|
|
|
|
* see include/asm-ia64/meminit.h if you need to define more.
|
|
|
|
*/
|
2006-03-23 01:54:15 +01:00
|
|
|
void __init
|
2005-04-17 00:20:36 +02:00
|
|
|
reserve_memory (void)
|
|
|
|
{
|
|
|
|
int n = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* none of the entries in this table overlap
|
|
|
|
*/
|
|
|
|
rsvd_region[n].start = (unsigned long) ia64_boot_param;
|
|
|
|
rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
|
|
|
|
n++;
|
|
|
|
|
|
|
|
rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
|
|
|
|
rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
|
|
|
|
n++;
|
|
|
|
|
|
|
|
rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
|
|
|
|
rsvd_region[n].end = (rsvd_region[n].start
|
|
|
|
+ strlen(__va(ia64_boot_param->command_line)) + 1);
|
|
|
|
n++;
|
|
|
|
|
|
|
|
rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
|
|
|
|
rsvd_region[n].end = (unsigned long) ia64_imva(_end);
|
|
|
|
n++;
|
|
|
|
|
|
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
|
|
|
if (ia64_boot_param->initrd_start) {
|
|
|
|
rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
|
|
|
|
rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
|
|
|
|
n++;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-09-08 21:39:59 +02:00
|
|
|
efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
|
|
|
|
n++;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/* end of memory marker */
|
|
|
|
rsvd_region[n].start = ~0UL;
|
|
|
|
rsvd_region[n].end = ~0UL;
|
|
|
|
n++;
|
|
|
|
|
|
|
|
num_rsvd_regions = n;
|
|
|
|
|
|
|
|
sort_regions(rsvd_region, num_rsvd_regions);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* find_initrd - get initrd parameters from the boot parameter structure
|
|
|
|
*
|
|
|
|
* Grab the initrd start and end from the boot parameter struct given us by
|
|
|
|
* the boot loader.
|
|
|
|
*/
|
2006-03-23 01:54:15 +01:00
|
|
|
void __init
|
2005-04-17 00:20:36 +02:00
|
|
|
find_initrd (void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
|
|
|
if (ia64_boot_param->initrd_start) {
|
|
|
|
initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
|
|
|
|
initrd_end = initrd_start+ia64_boot_param->initrd_size;
|
|
|
|
|
|
|
|
printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
|
|
|
|
initrd_start, ia64_boot_param->initrd_size);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
io_port_init (void)
|
|
|
|
{
|
|
|
|
unsigned long phys_iobase;
|
|
|
|
|
|
|
|
/*
|
2005-09-16 19:43:10 +02:00
|
|
|
* Set `iobase' based on the EFI memory map or, failing that, the
|
|
|
|
* value firmware left in ar.k0.
|
2005-04-17 00:20:36 +02:00
|
|
|
*
|
2005-09-16 19:43:10 +02:00
|
|
|
* Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
|
|
|
|
* the port's virtual address, so ia32_load_state() loads it with a
|
|
|
|
* user virtual address. But in ia64 mode, glibc uses the
|
|
|
|
* *physical* address in ar.k0 to mmap the appropriate area from
|
|
|
|
* /dev/mem, and the inX()/outX() interfaces use MMIO. In both
|
|
|
|
* cases, user-mode can only use the legacy 0-64K I/O port space.
|
|
|
|
*
|
|
|
|
* ar.k0 is not involved in kernel I/O port accesses, which can use
|
|
|
|
* any of the I/O port spaces and are done via MMIO using the
|
|
|
|
* virtual mmio_base from the appropriate io_space[].
|
2005-04-17 00:20:36 +02:00
|
|
|
*/
|
|
|
|
phys_iobase = efi_get_iobase();
|
2005-09-16 19:43:10 +02:00
|
|
|
if (!phys_iobase) {
|
2005-04-17 00:20:36 +02:00
|
|
|
phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
|
2005-09-16 19:43:10 +02:00
|
|
|
printk(KERN_INFO "No I/O port range found in EFI memory map, "
|
|
|
|
"falling back to AR.KR0 (0x%lx)\n", phys_iobase);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
|
2005-09-16 19:43:10 +02:00
|
|
|
ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* setup legacy IO port space */
|
|
|
|
io_space[0].mmio_base = ia64_iobase;
|
|
|
|
io_space[0].sparse = 1;
|
|
|
|
num_io_spaces = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* early_console_setup - setup debugging console
|
|
|
|
*
|
|
|
|
* Consoles started here require little enough setup that we can start using
|
|
|
|
* them very early in the boot process, either right after the machine
|
|
|
|
* vector initialization, or even before if the drivers can detect their hw.
|
|
|
|
*
|
|
|
|
* Returns non-zero if a console couldn't be setup.
|
|
|
|
*/
|
|
|
|
static inline int __init
|
|
|
|
early_console_setup (char *cmdline)
|
|
|
|
{
|
2005-04-25 22:51:00 +02:00
|
|
|
int earlycons = 0;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
#ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
|
|
|
|
{
|
|
|
|
extern int sn_serial_console_early_setup(void);
|
|
|
|
if (!sn_serial_console_early_setup())
|
2005-04-25 22:51:00 +02:00
|
|
|
earlycons++;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_EFI_PCDP
|
|
|
|
if (!efi_setup_pcdp_console(cmdline))
|
2005-04-25 22:51:00 +02:00
|
|
|
earlycons++;
|
2005-04-17 00:20:36 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SERIAL_8250_CONSOLE
|
|
|
|
if (!early_serial_console_init(cmdline))
|
2005-04-25 22:51:00 +02:00
|
|
|
earlycons++;
|
2005-04-17 00:20:36 +02:00
|
|
|
#endif
|
|
|
|
|
2005-04-25 22:51:00 +02:00
|
|
|
return (earlycons) ? 0 : -1;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
mark_bsp_online (void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
/* If we register an early console, allow CPU 0 to printk */
|
|
|
|
cpu_set(smp_processor_id(), cpu_online_map);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2005-04-25 22:25:06 +02:00
|
|
|
#ifdef CONFIG_SMP
|
2006-03-12 18:00:13 +01:00
|
|
|
static void __init
|
2005-04-25 22:25:06 +02:00
|
|
|
check_for_logical_procs (void)
|
|
|
|
{
|
|
|
|
pal_logical_to_physical_t info;
|
|
|
|
s64 status;
|
|
|
|
|
|
|
|
status = ia64_pal_logical_to_phys(0, &info);
|
|
|
|
if (status == -1) {
|
|
|
|
printk(KERN_INFO "No logical to physical processor mapping "
|
|
|
|
"available\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (status) {
|
|
|
|
printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
|
|
|
|
status);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Total number of siblings that BSP has. Though not all of them
|
|
|
|
* may have booted successfully. The correct number of siblings
|
|
|
|
* booted is in info.overview_num_log.
|
|
|
|
*/
|
|
|
|
smp_num_siblings = info.overview_tpc;
|
|
|
|
smp_num_cpucores = info.overview_cpp;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2006-03-23 23:27:12 +01:00
|
|
|
static __initdata int nomca;
|
|
|
|
static __init int setup_nomca(char *s)
|
|
|
|
{
|
|
|
|
nomca = 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
early_param("nomca", setup_nomca);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
void __init
|
|
|
|
setup_arch (char **cmdline_p)
|
|
|
|
{
|
|
|
|
unw_init();
|
|
|
|
|
|
|
|
ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
|
|
|
|
|
|
|
|
*cmdline_p = __va(ia64_boot_param->command_line);
|
|
|
|
strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
|
|
|
|
|
|
|
|
efi_init();
|
|
|
|
io_port_init();
|
|
|
|
|
2006-03-23 23:27:12 +01:00
|
|
|
parse_early_param();
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
#ifdef CONFIG_IA64_GENERIC
|
2006-03-23 23:27:12 +01:00
|
|
|
machvec_init(NULL);
|
2005-04-17 00:20:36 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
if (early_console_setup(*cmdline_p) == 0)
|
|
|
|
mark_bsp_online();
|
|
|
|
|
2005-08-24 18:07:20 +02:00
|
|
|
#ifdef CONFIG_ACPI
|
2005-04-17 00:20:36 +02:00
|
|
|
/* Initialize the ACPI boot-time table parser */
|
|
|
|
acpi_table_init();
|
|
|
|
# ifdef CONFIG_ACPI_NUMA
|
|
|
|
acpi_numa_init();
|
|
|
|
# endif
|
|
|
|
#else
|
|
|
|
# ifdef CONFIG_SMP
|
|
|
|
smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
|
|
|
|
# endif
|
|
|
|
#endif /* CONFIG_APCI_BOOT */
|
|
|
|
|
|
|
|
find_memory();
|
|
|
|
|
|
|
|
/* process SAL system table: */
|
2006-03-26 11:37:08 +02:00
|
|
|
ia64_sal_init(__va(efi.sal_systab));
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-02-08 00:25:57 +01:00
|
|
|
ia64_setup_printk_clock();
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
cpu_physical_id(0) = hard_smp_processor_id();
|
2005-04-25 22:25:06 +02:00
|
|
|
|
|
|
|
cpu_set(0, cpu_sibling_map[0]);
|
|
|
|
cpu_set(0, cpu_core_map[0]);
|
|
|
|
|
|
|
|
check_for_logical_procs();
|
|
|
|
if (smp_num_cpucores > 1)
|
|
|
|
printk(KERN_INFO
|
|
|
|
"cpu package is Multi-Core capable: number of cores=%d\n",
|
|
|
|
smp_num_cpucores);
|
|
|
|
if (smp_num_siblings > 1)
|
|
|
|
printk(KERN_INFO
|
|
|
|
"cpu package is Multi-Threading capable: number of siblings=%d\n",
|
|
|
|
smp_num_siblings);
|
2005-04-17 00:20:36 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
cpu_init(); /* initialize the bootstrap CPU */
|
2005-10-31 22:44:47 +01:00
|
|
|
mmu_context_init(); /* initialize context_id bitmap */
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-08-24 18:07:20 +02:00
|
|
|
#ifdef CONFIG_ACPI
|
2005-04-17 00:20:36 +02:00
|
|
|
acpi_boot_init();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_VT
|
|
|
|
if (!conswitchp) {
|
|
|
|
# if defined(CONFIG_DUMMY_CONSOLE)
|
|
|
|
conswitchp = &dummy_con;
|
|
|
|
# endif
|
|
|
|
# if defined(CONFIG_VGA_CONSOLE)
|
|
|
|
/*
|
|
|
|
* Non-legacy systems may route legacy VGA MMIO range to system
|
|
|
|
* memory. vga_con probes the MMIO hole, so memory looks like
|
|
|
|
* a VGA device to it. The EFI memory map can tell us if it's
|
|
|
|
* memory so we can avoid this problem.
|
|
|
|
*/
|
|
|
|
if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
|
|
|
|
conswitchp = &vga_con;
|
|
|
|
# endif
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* enable IA-64 Machine Check Abort Handling unless disabled */
|
2006-03-23 23:27:12 +01:00
|
|
|
if (!nomca)
|
2005-04-17 00:20:36 +02:00
|
|
|
ia64_mca_init();
|
|
|
|
|
|
|
|
platform_setup(cmdline_p);
|
|
|
|
paging_init();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Display cpu info for all cpu's.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
show_cpuinfo (struct seq_file *m, void *v)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
# define lpj c->loops_per_jiffy
|
|
|
|
# define cpunum c->cpu
|
|
|
|
#else
|
|
|
|
# define lpj loops_per_jiffy
|
|
|
|
# define cpunum 0
|
|
|
|
#endif
|
|
|
|
static struct {
|
|
|
|
unsigned long mask;
|
|
|
|
const char *feature_name;
|
|
|
|
} feature_bits[] = {
|
|
|
|
{ 1UL << 0, "branchlong" },
|
|
|
|
{ 1UL << 1, "spontaneous deferral"},
|
|
|
|
{ 1UL << 2, "16-byte atomic ops" }
|
|
|
|
};
|
|
|
|
char family[32], features[128], *cp, sep;
|
|
|
|
struct cpuinfo_ia64 *c = v;
|
|
|
|
unsigned long mask;
|
2006-01-05 22:30:52 +01:00
|
|
|
unsigned long proc_freq;
|
2005-04-17 00:20:36 +02:00
|
|
|
int i;
|
|
|
|
|
|
|
|
mask = c->features;
|
|
|
|
|
|
|
|
switch (c->family) {
|
|
|
|
case 0x07: memcpy(family, "Itanium", 8); break;
|
|
|
|
case 0x1f: memcpy(family, "Itanium 2", 10); break;
|
|
|
|
default: sprintf(family, "%u", c->family); break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* build the feature string: */
|
|
|
|
memcpy(features, " standard", 10);
|
|
|
|
cp = features;
|
|
|
|
sep = 0;
|
|
|
|
for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
|
|
|
|
if (mask & feature_bits[i].mask) {
|
|
|
|
if (sep)
|
|
|
|
*cp++ = sep;
|
|
|
|
sep = ',';
|
|
|
|
*cp++ = ' ';
|
|
|
|
strcpy(cp, feature_bits[i].feature_name);
|
|
|
|
cp += strlen(feature_bits[i].feature_name);
|
|
|
|
mask &= ~feature_bits[i].mask;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (mask) {
|
|
|
|
/* print unknown features as a hex value: */
|
|
|
|
if (sep)
|
|
|
|
*cp++ = sep;
|
|
|
|
sprintf(cp, " 0x%lx", mask);
|
|
|
|
}
|
|
|
|
|
2005-12-02 19:43:20 +01:00
|
|
|
proc_freq = cpufreq_quick_get(cpunum);
|
|
|
|
if (!proc_freq)
|
|
|
|
proc_freq = c->proc_freq / 1000;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
seq_printf(m,
|
|
|
|
"processor : %d\n"
|
|
|
|
"vendor : %s\n"
|
|
|
|
"arch : IA-64\n"
|
|
|
|
"family : %s\n"
|
|
|
|
"model : %u\n"
|
|
|
|
"revision : %u\n"
|
|
|
|
"archrev : %u\n"
|
|
|
|
"features :%s\n" /* don't change this---it _is_ right! */
|
|
|
|
"cpu number : %lu\n"
|
|
|
|
"cpu regs : %u\n"
|
|
|
|
"cpu MHz : %lu.%06lu\n"
|
|
|
|
"itc MHz : %lu.%06lu\n"
|
2005-04-25 22:25:06 +02:00
|
|
|
"BogoMIPS : %lu.%02lu\n",
|
2005-04-17 00:20:36 +02:00
|
|
|
cpunum, c->vendor, family, c->model, c->revision, c->archrev,
|
|
|
|
features, c->ppn, c->number,
|
2005-12-02 19:43:20 +01:00
|
|
|
proc_freq / 1000, proc_freq % 1000,
|
2005-04-17 00:20:36 +02:00
|
|
|
c->itc_freq / 1000000, c->itc_freq % 1000000,
|
|
|
|
lpj*HZ/500000, (lpj*HZ/5000) % 100);
|
2005-04-25 22:25:06 +02:00
|
|
|
#ifdef CONFIG_SMP
|
2005-10-05 01:35:31 +02:00
|
|
|
seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
|
2005-04-25 22:25:06 +02:00
|
|
|
if (c->threads_per_core > 1 || c->cores_per_socket > 1)
|
|
|
|
seq_printf(m,
|
|
|
|
"physical id: %u\n"
|
|
|
|
"core id : %u\n"
|
|
|
|
"thread id : %u\n",
|
|
|
|
c->socket_id, c->core_id, c->thread_id);
|
|
|
|
#endif
|
|
|
|
seq_printf(m,"\n");
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void *
|
|
|
|
c_start (struct seq_file *m, loff_t *pos)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
|
|
|
|
++*pos;
|
|
|
|
#endif
|
|
|
|
return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void *
|
|
|
|
c_next (struct seq_file *m, void *v, loff_t *pos)
|
|
|
|
{
|
|
|
|
++*pos;
|
|
|
|
return c_start(m, pos);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
c_stop (struct seq_file *m, void *v)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
struct seq_operations cpuinfo_op = {
|
|
|
|
.start = c_start,
|
|
|
|
.next = c_next,
|
|
|
|
.stop = c_stop,
|
|
|
|
.show = show_cpuinfo
|
|
|
|
};
|
|
|
|
|
2006-03-12 18:00:13 +01:00
|
|
|
static void __cpuinit
|
2005-04-17 00:20:36 +02:00
|
|
|
identify_cpu (struct cpuinfo_ia64 *c)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
unsigned long bits[5];
|
|
|
|
struct {
|
|
|
|
/* id 0 & 1: */
|
|
|
|
char vendor[16];
|
|
|
|
|
|
|
|
/* id 2 */
|
|
|
|
u64 ppn; /* processor serial number */
|
|
|
|
|
|
|
|
/* id 3: */
|
|
|
|
unsigned number : 8;
|
|
|
|
unsigned revision : 8;
|
|
|
|
unsigned model : 8;
|
|
|
|
unsigned family : 8;
|
|
|
|
unsigned archrev : 8;
|
|
|
|
unsigned reserved : 24;
|
|
|
|
|
|
|
|
/* id 4: */
|
|
|
|
u64 features;
|
|
|
|
} field;
|
|
|
|
} cpuid;
|
|
|
|
pal_vm_info_1_u_t vm1;
|
|
|
|
pal_vm_info_2_u_t vm2;
|
|
|
|
pal_status_t status;
|
|
|
|
unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 5; ++i)
|
|
|
|
cpuid.bits[i] = ia64_get_cpuid(i);
|
|
|
|
|
|
|
|
memcpy(c->vendor, cpuid.field.vendor, 16);
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
c->cpu = smp_processor_id();
|
2005-04-25 22:25:06 +02:00
|
|
|
|
|
|
|
/* below default values will be overwritten by identify_siblings()
|
|
|
|
* for Multi-Threading/Multi-Core capable cpu's
|
|
|
|
*/
|
|
|
|
c->threads_per_core = c->cores_per_socket = c->num_log = 1;
|
|
|
|
c->socket_id = -1;
|
|
|
|
|
|
|
|
identify_siblings(c);
|
2005-04-17 00:20:36 +02:00
|
|
|
#endif
|
|
|
|
c->ppn = cpuid.field.ppn;
|
|
|
|
c->number = cpuid.field.number;
|
|
|
|
c->revision = cpuid.field.revision;
|
|
|
|
c->model = cpuid.field.model;
|
|
|
|
c->family = cpuid.field.family;
|
|
|
|
c->archrev = cpuid.field.archrev;
|
|
|
|
c->features = cpuid.field.features;
|
|
|
|
|
|
|
|
status = ia64_pal_vm_summary(&vm1, &vm2);
|
|
|
|
if (status == PAL_STATUS_SUCCESS) {
|
|
|
|
impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
|
|
|
|
phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
|
|
|
|
}
|
|
|
|
c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
|
|
|
|
c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
setup_per_cpu_areas (void)
|
|
|
|
{
|
|
|
|
/* start_kernel() requires this... */
|
2006-02-15 00:01:12 +01:00
|
|
|
#ifdef CONFIG_ACPI_HOTPLUG_CPU
|
|
|
|
prefill_possible_map();
|
|
|
|
#endif
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2005-06-03 14:36:00 +02:00
|
|
|
/*
|
|
|
|
* Calculate the max. cache line size.
|
|
|
|
*
|
|
|
|
* In addition, the minimum of the i-cache stride sizes is calculated for
|
|
|
|
* "flush_icache_range()".
|
|
|
|
*/
|
2006-03-12 18:00:13 +01:00
|
|
|
static void __cpuinit
|
2005-04-17 00:20:36 +02:00
|
|
|
get_max_cacheline_size (void)
|
|
|
|
{
|
|
|
|
unsigned long line_size, max = 1;
|
[PATCH] scheduler cache-hot-autodetect
)
From: Ingo Molnar <mingo@elte.hu>
This is the latest version of the scheduler cache-hot-auto-tune patch.
The first problem was that detection time scaled with O(N^2), which is
unacceptable on larger SMP and NUMA systems. To solve this:
- I've added a 'domain distance' function, which is used to cache
measurement results. Each distance is only measured once. This means
that e.g. on NUMA distances of 0, 1 and 2 might be measured, on HT
distances 0 and 1, and on SMP distance 0 is measured. The code walks
the domain tree to determine the distance, so it automatically follows
whatever hierarchy an architecture sets up. This cuts down on the boot
time significantly and removes the O(N^2) limit. The only assumption
is that migration costs can be expressed as a function of domain
distance - this covers the overwhelming majority of existing systems,
and is a good guess even for more assymetric systems.
[ People hacking systems that have assymetries that break this
assumption (e.g. different CPU speeds) should experiment a bit with
the cpu_distance() function. Adding a ->migration_distance factor to
the domain structure would be one possible solution - but lets first
see the problem systems, if they exist at all. Lets not overdesign. ]
Another problem was that only a single cache-size was used for measuring
the cost of migration, and most architectures didnt set that variable
up. Furthermore, a single cache-size does not fit NUMA hierarchies with
L3 caches and does not fit HT setups, where different CPUs will often
have different 'effective cache sizes'. To solve this problem:
- Instead of relying on a single cache-size provided by the platform and
sticking to it, the code now auto-detects the 'effective migration
cost' between two measured CPUs, via iterating through a wide range of
cachesizes. The code searches for the maximum migration cost, which
occurs when the working set of the test-workload falls just below the
'effective cache size'. I.e. real-life optimized search is done for
the maximum migration cost, between two real CPUs.
This, amongst other things, has the positive effect hat if e.g. two
CPUs share a L2/L3 cache, a different (and accurate) migration cost
will be found than between two CPUs on the same system that dont share
any caches.
(The reliable measurement of migration costs is tricky - see the source
for details.)
Furthermore i've added various boot-time options to override/tune
migration behavior.
Firstly, there's a blanket override for autodetection:
migration_cost=1000,2000,3000
will override the depth 0/1/2 values with 1msec/2msec/3msec values.
Secondly, there's a global factor that can be used to increase (or
decrease) the autodetected values:
migration_factor=120
will increase the autodetected values by 20%. This option is useful to
tune things in a workload-dependent way - e.g. if a workload is
cache-insensitive then CPU utilization can be maximized by specifying
migration_factor=0.
I've tested the autodetection code quite extensively on x86, on 3
P3/Xeon/2MB, and the autodetected values look pretty good:
Dual Celeron (128K L2 cache):
---------------------
migration cost matrix (max_cache_size: 131072, cpu: 467 MHz):
---------------------
[00] [01]
[00]: - 1.7(1)
[01]: 1.7(1) -
---------------------
cacheflush times [2]: 0.0 (0) 1.7 (1784008)
---------------------
Here the slow memory subsystem dominates system performance, and even
though caches are small, the migration cost is 1.7 msecs.
Dual HT P4 (512K L2 cache):
---------------------
migration cost matrix (max_cache_size: 524288, cpu: 2379 MHz):
---------------------
[00] [01] [02] [03]
[00]: - 0.4(1) 0.0(0) 0.4(1)
[01]: 0.4(1) - 0.4(1) 0.0(0)
[02]: 0.0(0) 0.4(1) - 0.4(1)
[03]: 0.4(1) 0.0(0) 0.4(1) -
---------------------
cacheflush times [2]: 0.0 (33900) 0.4 (448514)
---------------------
Here it can be seen that there is no migration cost between two HT
siblings (CPU#0/2 and CPU#1/3 are separate physical CPUs). A fast memory
system makes inter-physical-CPU migration pretty cheap: 0.4 msecs.
8-way P3/Xeon [2MB L2 cache]:
---------------------
migration cost matrix (max_cache_size: 2097152, cpu: 700 MHz):
---------------------
[00] [01] [02] [03] [04] [05] [06] [07]
[00]: - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[01]: 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[02]: 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[03]: 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[04]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1)
[05]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1)
[06]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1)
[07]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) -
---------------------
cacheflush times [2]: 0.0 (0) 19.2 (19281756)
---------------------
This one has huge caches and a relatively slow memory subsystem - so the
migration cost is 19 msecs.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Cc: <wilder@us.ibm.com>
Signed-off-by: John Hawkes <hawkes@sgi.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 10:05:30 +01:00
|
|
|
unsigned int cache_size = 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
u64 l, levels, unique_caches;
|
|
|
|
pal_cache_config_info_t cci;
|
|
|
|
s64 status;
|
|
|
|
|
|
|
|
status = ia64_pal_cache_summary(&levels, &unique_caches);
|
|
|
|
if (status != 0) {
|
|
|
|
printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
|
|
|
|
__FUNCTION__, status);
|
|
|
|
max = SMP_CACHE_BYTES;
|
2005-06-03 14:36:00 +02:00
|
|
|
/* Safest setup for "flush_icache_range()" */
|
|
|
|
ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
|
2005-04-17 00:20:36 +02:00
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (l = 0; l < levels; ++l) {
|
|
|
|
status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
|
|
|
|
&cci);
|
|
|
|
if (status != 0) {
|
|
|
|
printk(KERN_ERR
|
2005-06-03 14:36:00 +02:00
|
|
|
"%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
|
2005-04-17 00:20:36 +02:00
|
|
|
__FUNCTION__, l, status);
|
|
|
|
max = SMP_CACHE_BYTES;
|
2005-06-03 14:36:00 +02:00
|
|
|
/* The safest setup for "flush_icache_range()" */
|
|
|
|
cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
|
|
|
|
cci.pcci_unified = 1;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
line_size = 1 << cci.pcci_line_size;
|
|
|
|
if (line_size > max)
|
|
|
|
max = line_size;
|
[PATCH] scheduler cache-hot-autodetect
)
From: Ingo Molnar <mingo@elte.hu>
This is the latest version of the scheduler cache-hot-auto-tune patch.
The first problem was that detection time scaled with O(N^2), which is
unacceptable on larger SMP and NUMA systems. To solve this:
- I've added a 'domain distance' function, which is used to cache
measurement results. Each distance is only measured once. This means
that e.g. on NUMA distances of 0, 1 and 2 might be measured, on HT
distances 0 and 1, and on SMP distance 0 is measured. The code walks
the domain tree to determine the distance, so it automatically follows
whatever hierarchy an architecture sets up. This cuts down on the boot
time significantly and removes the O(N^2) limit. The only assumption
is that migration costs can be expressed as a function of domain
distance - this covers the overwhelming majority of existing systems,
and is a good guess even for more assymetric systems.
[ People hacking systems that have assymetries that break this
assumption (e.g. different CPU speeds) should experiment a bit with
the cpu_distance() function. Adding a ->migration_distance factor to
the domain structure would be one possible solution - but lets first
see the problem systems, if they exist at all. Lets not overdesign. ]
Another problem was that only a single cache-size was used for measuring
the cost of migration, and most architectures didnt set that variable
up. Furthermore, a single cache-size does not fit NUMA hierarchies with
L3 caches and does not fit HT setups, where different CPUs will often
have different 'effective cache sizes'. To solve this problem:
- Instead of relying on a single cache-size provided by the platform and
sticking to it, the code now auto-detects the 'effective migration
cost' between two measured CPUs, via iterating through a wide range of
cachesizes. The code searches for the maximum migration cost, which
occurs when the working set of the test-workload falls just below the
'effective cache size'. I.e. real-life optimized search is done for
the maximum migration cost, between two real CPUs.
This, amongst other things, has the positive effect hat if e.g. two
CPUs share a L2/L3 cache, a different (and accurate) migration cost
will be found than between two CPUs on the same system that dont share
any caches.
(The reliable measurement of migration costs is tricky - see the source
for details.)
Furthermore i've added various boot-time options to override/tune
migration behavior.
Firstly, there's a blanket override for autodetection:
migration_cost=1000,2000,3000
will override the depth 0/1/2 values with 1msec/2msec/3msec values.
Secondly, there's a global factor that can be used to increase (or
decrease) the autodetected values:
migration_factor=120
will increase the autodetected values by 20%. This option is useful to
tune things in a workload-dependent way - e.g. if a workload is
cache-insensitive then CPU utilization can be maximized by specifying
migration_factor=0.
I've tested the autodetection code quite extensively on x86, on 3
P3/Xeon/2MB, and the autodetected values look pretty good:
Dual Celeron (128K L2 cache):
---------------------
migration cost matrix (max_cache_size: 131072, cpu: 467 MHz):
---------------------
[00] [01]
[00]: - 1.7(1)
[01]: 1.7(1) -
---------------------
cacheflush times [2]: 0.0 (0) 1.7 (1784008)
---------------------
Here the slow memory subsystem dominates system performance, and even
though caches are small, the migration cost is 1.7 msecs.
Dual HT P4 (512K L2 cache):
---------------------
migration cost matrix (max_cache_size: 524288, cpu: 2379 MHz):
---------------------
[00] [01] [02] [03]
[00]: - 0.4(1) 0.0(0) 0.4(1)
[01]: 0.4(1) - 0.4(1) 0.0(0)
[02]: 0.0(0) 0.4(1) - 0.4(1)
[03]: 0.4(1) 0.0(0) 0.4(1) -
---------------------
cacheflush times [2]: 0.0 (33900) 0.4 (448514)
---------------------
Here it can be seen that there is no migration cost between two HT
siblings (CPU#0/2 and CPU#1/3 are separate physical CPUs). A fast memory
system makes inter-physical-CPU migration pretty cheap: 0.4 msecs.
8-way P3/Xeon [2MB L2 cache]:
---------------------
migration cost matrix (max_cache_size: 2097152, cpu: 700 MHz):
---------------------
[00] [01] [02] [03] [04] [05] [06] [07]
[00]: - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[01]: 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[02]: 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[03]: 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[04]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1)
[05]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1)
[06]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1)
[07]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) -
---------------------
cacheflush times [2]: 0.0 (0) 19.2 (19281756)
---------------------
This one has huge caches and a relatively slow memory subsystem - so the
migration cost is 19 msecs.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Cc: <wilder@us.ibm.com>
Signed-off-by: John Hawkes <hawkes@sgi.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 10:05:30 +01:00
|
|
|
if (cache_size < cci.pcci_cache_size)
|
|
|
|
cache_size = cci.pcci_cache_size;
|
2005-06-03 14:36:00 +02:00
|
|
|
if (!cci.pcci_unified) {
|
|
|
|
status = ia64_pal_cache_config_info(l,
|
|
|
|
/* cache_type (instruction)= */ 1,
|
|
|
|
&cci);
|
|
|
|
if (status != 0) {
|
|
|
|
printk(KERN_ERR
|
|
|
|
"%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
|
|
|
|
__FUNCTION__, l, status);
|
|
|
|
/* The safest setup for "flush_icache_range()" */
|
|
|
|
cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (cci.pcci_stride < ia64_i_cache_stride_shift)
|
|
|
|
ia64_i_cache_stride_shift = cci.pcci_stride;
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
out:
|
[PATCH] scheduler cache-hot-autodetect
)
From: Ingo Molnar <mingo@elte.hu>
This is the latest version of the scheduler cache-hot-auto-tune patch.
The first problem was that detection time scaled with O(N^2), which is
unacceptable on larger SMP and NUMA systems. To solve this:
- I've added a 'domain distance' function, which is used to cache
measurement results. Each distance is only measured once. This means
that e.g. on NUMA distances of 0, 1 and 2 might be measured, on HT
distances 0 and 1, and on SMP distance 0 is measured. The code walks
the domain tree to determine the distance, so it automatically follows
whatever hierarchy an architecture sets up. This cuts down on the boot
time significantly and removes the O(N^2) limit. The only assumption
is that migration costs can be expressed as a function of domain
distance - this covers the overwhelming majority of existing systems,
and is a good guess even for more assymetric systems.
[ People hacking systems that have assymetries that break this
assumption (e.g. different CPU speeds) should experiment a bit with
the cpu_distance() function. Adding a ->migration_distance factor to
the domain structure would be one possible solution - but lets first
see the problem systems, if they exist at all. Lets not overdesign. ]
Another problem was that only a single cache-size was used for measuring
the cost of migration, and most architectures didnt set that variable
up. Furthermore, a single cache-size does not fit NUMA hierarchies with
L3 caches and does not fit HT setups, where different CPUs will often
have different 'effective cache sizes'. To solve this problem:
- Instead of relying on a single cache-size provided by the platform and
sticking to it, the code now auto-detects the 'effective migration
cost' between two measured CPUs, via iterating through a wide range of
cachesizes. The code searches for the maximum migration cost, which
occurs when the working set of the test-workload falls just below the
'effective cache size'. I.e. real-life optimized search is done for
the maximum migration cost, between two real CPUs.
This, amongst other things, has the positive effect hat if e.g. two
CPUs share a L2/L3 cache, a different (and accurate) migration cost
will be found than between two CPUs on the same system that dont share
any caches.
(The reliable measurement of migration costs is tricky - see the source
for details.)
Furthermore i've added various boot-time options to override/tune
migration behavior.
Firstly, there's a blanket override for autodetection:
migration_cost=1000,2000,3000
will override the depth 0/1/2 values with 1msec/2msec/3msec values.
Secondly, there's a global factor that can be used to increase (or
decrease) the autodetected values:
migration_factor=120
will increase the autodetected values by 20%. This option is useful to
tune things in a workload-dependent way - e.g. if a workload is
cache-insensitive then CPU utilization can be maximized by specifying
migration_factor=0.
I've tested the autodetection code quite extensively on x86, on 3
P3/Xeon/2MB, and the autodetected values look pretty good:
Dual Celeron (128K L2 cache):
---------------------
migration cost matrix (max_cache_size: 131072, cpu: 467 MHz):
---------------------
[00] [01]
[00]: - 1.7(1)
[01]: 1.7(1) -
---------------------
cacheflush times [2]: 0.0 (0) 1.7 (1784008)
---------------------
Here the slow memory subsystem dominates system performance, and even
though caches are small, the migration cost is 1.7 msecs.
Dual HT P4 (512K L2 cache):
---------------------
migration cost matrix (max_cache_size: 524288, cpu: 2379 MHz):
---------------------
[00] [01] [02] [03]
[00]: - 0.4(1) 0.0(0) 0.4(1)
[01]: 0.4(1) - 0.4(1) 0.0(0)
[02]: 0.0(0) 0.4(1) - 0.4(1)
[03]: 0.4(1) 0.0(0) 0.4(1) -
---------------------
cacheflush times [2]: 0.0 (33900) 0.4 (448514)
---------------------
Here it can be seen that there is no migration cost between two HT
siblings (CPU#0/2 and CPU#1/3 are separate physical CPUs). A fast memory
system makes inter-physical-CPU migration pretty cheap: 0.4 msecs.
8-way P3/Xeon [2MB L2 cache]:
---------------------
migration cost matrix (max_cache_size: 2097152, cpu: 700 MHz):
---------------------
[00] [01] [02] [03] [04] [05] [06] [07]
[00]: - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[01]: 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[02]: 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[03]: 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1)
[04]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1)
[05]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1)
[06]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1)
[07]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) -
---------------------
cacheflush times [2]: 0.0 (0) 19.2 (19281756)
---------------------
This one has huge caches and a relatively slow memory subsystem - so the
migration cost is 19 msecs.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Cc: <wilder@us.ibm.com>
Signed-off-by: John Hawkes <hawkes@sgi.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 10:05:30 +01:00
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#ifdef CONFIG_SMP
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max_cache_size = max(max_cache_size, cache_size);
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#endif
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2005-04-17 00:20:36 +02:00
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if (max > ia64_max_cacheline_size)
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ia64_max_cacheline_size = max;
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}
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/*
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* cpu_init() initializes state that is per-CPU. This function acts
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* as a 'CPU state barrier', nothing should get across.
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*/
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2006-03-12 18:00:13 +01:00
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void __cpuinit
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2005-04-17 00:20:36 +02:00
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cpu_init (void)
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{
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2006-03-12 18:00:13 +01:00
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extern void __cpuinit ia64_mmu_init (void *);
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2005-04-17 00:20:36 +02:00
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unsigned long num_phys_stacked;
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pal_vm_info_2_u_t vmi;
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unsigned int max_ctx;
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struct cpuinfo_ia64 *cpu_info;
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void *cpu_data;
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cpu_data = per_cpu_init();
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/*
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* We set ar.k3 so that assembly code in MCA handler can compute
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* physical addresses of per cpu variables with a simple:
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* phys = ar.k3 + &per_cpu_var
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*/
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ia64_set_kr(IA64_KR_PER_CPU_DATA,
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ia64_tpa(cpu_data) - (long) __per_cpu_start);
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get_max_cacheline_size();
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/*
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* We can't pass "local_cpu_data" to identify_cpu() because we haven't called
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* ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
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* depends on the data returned by identify_cpu(). We break the dependency by
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* accessing cpu_data() through the canonical per-CPU address.
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*/
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cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
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identify_cpu(cpu_info);
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#ifdef CONFIG_MCKINLEY
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{
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# define FEATURE_SET 16
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struct ia64_pal_retval iprv;
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if (cpu_info->family == 0x1f) {
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PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
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if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
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PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
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(iprv.v1 | 0x80), FEATURE_SET, 0);
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}
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}
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#endif
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/* Clear the stack memory reserved for pt_regs: */
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2006-01-12 10:06:06 +01:00
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memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
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2005-04-17 00:20:36 +02:00
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ia64_set_kr(IA64_KR_FPU_OWNER, 0);
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/*
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* Initialize the page-table base register to a global
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* directory with all zeroes. This ensure that we can handle
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* TLB-misses to user address-space even before we created the
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* first user address-space. This may happen, e.g., due to
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* aggressive use of lfetch.fault.
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*/
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ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
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/*
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2005-06-08 21:12:48 +02:00
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* Initialize default control register to defer speculative faults except
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* for those arising from TLB misses, which are not deferred. The
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2005-04-17 00:20:36 +02:00
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* kernel MUST NOT depend on a particular setting of these bits (in other words,
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* the kernel must have recovery code for all speculative accesses). Turn on
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* dcr.lc as per recommendation by the architecture team. Most IA-32 apps
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* shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
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* be fine).
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*/
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ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
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| IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
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atomic_inc(&init_mm.mm_count);
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current->active_mm = &init_mm;
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if (current->mm)
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BUG();
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ia64_mmu_init(ia64_imva(cpu_data));
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ia64_mca_cpu_init(ia64_imva(cpu_data));
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#ifdef CONFIG_IA32_SUPPORT
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ia32_cpu_init();
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#endif
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/* Clear ITC to eliminiate sched_clock() overflows in human time. */
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ia64_set_itc(0);
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/* disable all local interrupt sources: */
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ia64_set_itv(1 << 16);
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ia64_set_lrr0(1 << 16);
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ia64_set_lrr1(1 << 16);
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ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
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ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
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/* clear TPR & XTP to enable all interrupt classes: */
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ia64_setreg(_IA64_REG_CR_TPR, 0);
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#ifdef CONFIG_SMP
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normal_xtp();
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#endif
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/* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
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if (ia64_pal_vm_summary(NULL, &vmi) == 0)
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max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
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else {
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printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
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max_ctx = (1U << 15) - 1; /* use architected minimum */
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}
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while (max_ctx < ia64_ctx.max_ctx) {
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unsigned int old = ia64_ctx.max_ctx;
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if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
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break;
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}
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if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
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printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
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"stacked regs\n");
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num_phys_stacked = 96;
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}
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/* size of physical stacked register partition plus 8 bytes: */
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__get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
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platform_cpu_init();
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2005-04-19 05:06:47 +02:00
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pm_idle = default_idle;
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2005-04-17 00:20:36 +02:00
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}
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2006-01-12 10:05:27 +01:00
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible.
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*/
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void sched_cacheflush(void)
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{
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ia64_sal_cache_flush(3);
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}
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2006-03-12 18:00:13 +01:00
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void __init
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2005-04-17 00:20:36 +02:00
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check_bugs (void)
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{
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ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
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(unsigned long) __end___mckinley_e9_bundles);
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}
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[PATCH] ia64: use i386 dmi_scan.c
Enable DMI table parsing on ia64.
Andi Kleen has a patch in his x86_64 tree which enables the use of i386
dmi_scan.c on x86_64. dmi_scan.c functions are being used by the
drivers/char/ipmi/ipmi_si_intf.c driver for autodetecting the ports or
memory spaces where the IPMI controllers may be found.
This patch adds equivalent changes for ia64 as to what is in the x86_64
tree. In addition, I reworked the DMI detection, such that on EFI-capable
systems, it uses the efi.smbios pointer to find the table, rather than
brute-force searching from 0xF0000. On non-EFI systems, it continues the
brute-force search.
My test system, an Intel S870BN4 'Tiger4', aka Dell PowerEdge 7250, with
latest BIOS, does not list the IPMI controller in the ACPI namespace, nor
does it have an ACPI SPMI table. Also note, currently shipping Dell x8xx
EM64T servers don't have these either, so DMI is the only method for
obtaining the address of the IPMI controller.
Signed-off-by: Matt Domsch <Matt_Domsch@dell.com>
Acked-by: "Luck, Tony" <tony.luck@intel.com>
Cc: Andi Kleen <ak@muc.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-26 11:37:03 +02:00
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static int __init run_dmi_scan(void)
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{
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dmi_scan_machine();
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return 0;
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}
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core_initcall(run_dmi_scan);
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