2012-06-13 19:01:28 +02:00
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/*
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* Device Tree support for Armada 370 and XP platforms.
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
|
2013-05-11 03:08:09 +02:00
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#include <linux/clk-provider.h>
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2013-06-05 09:04:59 +02:00
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#include <linux/of_address.h>
|
2014-11-21 17:00:07 +01:00
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#include <linux/of_fdt.h>
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2012-06-13 19:01:28 +02:00
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#include <linux/of_platform.h>
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#include <linux/io.h>
|
2013-08-13 16:43:12 +02:00
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#include <linux/clocksource.h>
|
2012-10-26 14:30:46 +02:00
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#include <linux/dma-mapping.h>
|
2014-11-21 17:00:07 +01:00
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#include <linux/memblock.h>
|
2013-03-21 17:59:15 +01:00
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#include <linux/mbus.h>
|
2014-02-24 21:54:49 +01:00
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#include <linux/signal.h>
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2014-01-07 16:26:01 +01:00
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|
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#include <linux/slab.h>
|
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 17:09:32 +02:00
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|
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#include <linux/irqchip.h>
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2013-04-09 23:26:14 +02:00
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#include <asm/hardware/cache-l2x0.h>
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2012-06-13 19:01:28 +02:00
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
|
2014-04-14 15:47:03 +02:00
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#include <asm/smp_scu.h>
|
2012-09-02 21:57:33 +02:00
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#include "armada-370-xp.h"
|
2012-06-13 19:01:28 +02:00
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#include "common.h"
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2012-11-14 22:51:08 +01:00
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#include "coherency.h"
|
2014-01-07 16:26:01 +01:00
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|
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#include "mvebu-soc-id.h"
|
2012-06-13 19:01:28 +02:00
|
|
|
|
2014-07-23 15:00:46 +02:00
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static void __iomem *scu_base;
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|
2014-04-14 15:47:03 +02:00
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/*
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* Enables the SCU when available. Obviously, this is only useful on
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* Cortex-A based SOCs, not on PJ4B based ones.
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*/
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static void __init mvebu_scu_enable(void)
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|
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{
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struct device_node *np =
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of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (np) {
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scu_base = of_iomap(np, 0);
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scu_enable(scu_base);
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of_node_put(np);
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}
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}
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|
|
2014-07-23 15:00:46 +02:00
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void __iomem *mvebu_get_scu_base(void)
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|
|
|
{
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return scu_base;
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|
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|
}
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|
|
|
2014-11-21 17:00:07 +01:00
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|
|
/*
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* When returning from suspend, the platform goes through the
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* bootloader, which executes its DDR3 training code. This code has
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* the unfortunate idea of using the first 10 KB of each DRAM bank to
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* exercise the RAM and calculate the optimal timings. Therefore, this
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* area of RAM is overwritten, and shouldn't be used by the kernel if
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* suspend/resume is supported.
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*/
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#ifdef CONFIG_SUSPEND
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#define MVEBU_DDR_TRAINING_AREA_SZ (10 * SZ_1K)
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static int __init mvebu_scan_mem(unsigned long node, const char *uname,
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|
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int depth, void *data)
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|
|
{
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const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
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const __be32 *reg, *endp;
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int l;
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if (type == NULL || strcmp(type, "memory"))
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return 0;
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reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
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if (reg == NULL)
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reg = of_get_flat_dt_prop(node, "reg", &l);
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|
if (reg == NULL)
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return 0;
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endp = reg + (l / sizeof(__be32));
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while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
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u64 base, size;
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base = dt_mem_next_cell(dt_root_addr_cells, ®);
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size = dt_mem_next_cell(dt_root_size_cells, ®);
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memblock_reserve(base, MVEBU_DDR_TRAINING_AREA_SZ);
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}
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return 0;
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}
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static void __init mvebu_memblock_reserve(void)
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{
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of_scan_flat_dt(mvebu_scan_mem, NULL);
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}
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#else
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static void __init mvebu_memblock_reserve(void) {}
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#endif
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|
2014-02-17 15:23:24 +01:00
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/*
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* Early versions of Armada 375 SoC have a bug where the BootROM
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* leaves an external data abort pending. The kernel is hit by this
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* data abort as soon as it enters userspace, because it unmasks the
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* data aborts at this moment. We register a custom abort handler
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* below to ignore the first data abort to work around this
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* problem.
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*/
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static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
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struct pt_regs *regs)
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|
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{
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static int ignore_first;
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if (!ignore_first && fsr == 0x1406) {
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ignore_first = 1;
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return 0;
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}
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return 1;
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|
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}
|
|
|
|
|
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 17:09:32 +02:00
|
|
|
static void __init mvebu_init_irq(void)
|
2013-06-05 09:04:59 +02:00
|
|
|
{
|
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 17:09:32 +02:00
|
|
|
irqchip_init();
|
2014-04-14 15:47:03 +02:00
|
|
|
mvebu_scu_enable();
|
2013-06-05 09:04:59 +02:00
|
|
|
coherency_init();
|
2014-04-14 15:47:01 +02:00
|
|
|
BUG_ON(mvebu_mbus_dt_init(coherency_available()));
|
2014-06-12 17:09:31 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __init external_abort_quirk(void)
|
|
|
|
{
|
|
|
|
u32 dev, rev;
|
2014-02-17 15:23:24 +01:00
|
|
|
|
2014-06-12 17:09:31 +02:00
|
|
|
if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
|
|
|
|
return;
|
|
|
|
|
|
|
|
hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
|
|
|
|
"imprecise external abort");
|
2012-10-26 14:30:46 +02:00
|
|
|
}
|
|
|
|
|
2014-01-07 16:26:01 +01:00
|
|
|
static void __init i2c_quirk(void)
|
|
|
|
{
|
|
|
|
struct device_node *np;
|
|
|
|
u32 dev, rev;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Only revisons more recent than A0 support the offload
|
|
|
|
* mechanism. We can exit only if we are sure that we can
|
|
|
|
* get the SoC revision and it is more recent than A0.
|
|
|
|
*/
|
2014-04-19 18:32:50 +02:00
|
|
|
if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > MV78XX0_A0_REV)
|
2014-01-07 16:26:01 +01:00
|
|
|
return;
|
|
|
|
|
|
|
|
for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
|
|
|
|
struct property *new_compat;
|
|
|
|
|
|
|
|
new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);
|
|
|
|
|
|
|
|
new_compat->name = kstrdup("compatible", GFP_KERNEL);
|
|
|
|
new_compat->length = sizeof("marvell,mv78230-a0-i2c");
|
|
|
|
new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
|
|
|
of_update_property(np, new_compat);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-02-17 15:23:19 +01:00
|
|
|
static void __init mvebu_dt_init(void)
|
2012-06-13 19:01:28 +02:00
|
|
|
{
|
2014-07-26 19:20:37 +02:00
|
|
|
if (of_machine_is_compatible("marvell,armadaxp"))
|
2014-01-07 16:26:01 +01:00
|
|
|
i2c_quirk();
|
2014-11-04 17:00:39 +01:00
|
|
|
if (of_machine_is_compatible("marvell,a375-db"))
|
2014-06-12 17:09:31 +02:00
|
|
|
external_abort_quirk();
|
2014-04-24 22:23:22 +02:00
|
|
|
|
2012-06-13 19:01:28 +02:00
|
|
|
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
|
|
|
}
|
|
|
|
|
2015-03-03 15:40:56 +01:00
|
|
|
static const char * const armada_370_xp_dt_compat[] __initconst = {
|
2012-11-09 16:26:26 +01:00
|
|
|
"marvell,armada-370-xp",
|
2012-06-13 19:01:28 +02:00
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
2014-02-17 15:23:20 +01:00
|
|
|
DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
|
2014-04-28 16:44:47 +02:00
|
|
|
.l2c_aux_val = 0,
|
|
|
|
.l2c_aux_mask = ~0,
|
2014-10-30 12:39:41 +01:00
|
|
|
/*
|
|
|
|
* The following field (.smp) is still needed to ensure backward
|
|
|
|
* compatibility with old Device Trees that were not specifying the
|
|
|
|
* cpus enable-method property.
|
|
|
|
*/
|
2012-11-14 22:51:08 +01:00
|
|
|
.smp = smp_ops(armada_xp_smp_ops),
|
2014-02-17 15:23:19 +01:00
|
|
|
.init_machine = mvebu_dt_init,
|
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 17:09:32 +02:00
|
|
|
.init_irq = mvebu_init_irq,
|
2012-06-13 19:01:28 +02:00
|
|
|
.restart = mvebu_restart,
|
2014-11-21 17:00:07 +01:00
|
|
|
.reserve = mvebu_memblock_reserve,
|
2012-11-09 16:26:26 +01:00
|
|
|
.dt_compat = armada_370_xp_dt_compat,
|
2012-06-13 19:01:28 +02:00
|
|
|
MACHINE_END
|
2014-02-17 15:23:23 +01:00
|
|
|
|
2015-03-03 15:40:56 +01:00
|
|
|
static const char * const armada_375_dt_compat[] __initconst = {
|
2014-02-17 15:23:23 +01:00
|
|
|
"marvell,armada375",
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
|
2014-04-28 16:44:47 +02:00
|
|
|
.l2c_aux_val = 0,
|
|
|
|
.l2c_aux_mask = ~0,
|
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 17:09:32 +02:00
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.init_irq = mvebu_init_irq,
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2014-04-24 22:23:22 +02:00
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.init_machine = mvebu_dt_init,
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2014-02-17 15:23:23 +01:00
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.restart = mvebu_restart,
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.dt_compat = armada_375_dt_compat,
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MACHINE_END
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2014-02-17 15:23:27 +01:00
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2015-03-03 15:40:56 +01:00
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static const char * const armada_38x_dt_compat[] __initconst = {
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2014-02-17 15:23:27 +01:00
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"marvell,armada380",
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"marvell,armada385",
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NULL,
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};
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DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
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2014-04-28 16:44:47 +02:00
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 17:09:32 +02:00
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.init_irq = mvebu_init_irq,
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2014-02-17 15:23:27 +01:00
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.restart = mvebu_restart,
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.dt_compat = armada_38x_dt_compat,
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MACHINE_END
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ARM: mvebu: add core support for Armada 39x
This commit adds the core support for Armada 39x, which is quite
simple:
- a new Kconfig option which selects the appropriate clock and
pinctrl drivers as well as other common features (GIC, L2 cache,
SMP, etc.)
- a new DT_MACHINE_START which references the top-level compatible
strings supported for the Marvell Armada 39x.
- a new SMP enable-method. The mechanism to enable CPUs for Armada
39x appears to be the same as Armada 38x. However, we do not want
to use marvell,armada-380-smp in the Device Tree, in the case of
the discovery of a subtle difference in the future, which would
require changing the Device Tree. And the enable-method isn't a
compatible string: you can't specify several values and expect a
fallback on the second string if the first one isn't
supported. Therefore, we simply declare the SMP enable method
"marvell,armada-390-smp" as doing the same thing as the
"marvell,armada-380-smp" one.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-03-03 15:41:11 +01:00
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static const char * const armada_39x_dt_compat[] __initconst = {
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"marvell,armada390",
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"marvell,armada398",
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NULL,
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};
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DT_MACHINE_START(ARMADA_39X_DT, "Marvell Armada 39x (Device Tree)")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_irq = mvebu_init_irq,
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.restart = mvebu_restart,
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.dt_compat = armada_39x_dt_compat,
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MACHINE_END
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