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linux/arch/arm/boot/dts/omap2430-clocks.dtsi

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ARM: dts: omap2 clock data This patch creates a unique node for each clock in the OMAP2 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-02-21 16:05:02 +01:00
/*
* Device Tree Source for OMAP2430 clock data
*
* Copyright (C) 2014 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
ARM: dts: omap24xx: add minimal l4 bus layout with control module support This patch creates an l4 / l4-wkup interconnects for omap2420 / omap2430 SoCs, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the new SCM node as the clock provider. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-02-12 09:38:16 +01:00
&scm_clocks {
ARM: dts: omap2 clock data This patch creates a unique node for each clock in the OMAP2 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-02-21 16:05:02 +01:00
mcbsp3_mux_fck: mcbsp3_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ARM: dts: omap24xx: add minimal l4 bus layout with control module support This patch creates an l4 / l4-wkup interconnects for omap2420 / omap2430 SoCs, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the new SCM node as the clock provider. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-02-12 09:38:16 +01:00
reg = <0x78>;
ARM: dts: omap2 clock data This patch creates a unique node for each clock in the OMAP2 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-02-21 16:05:02 +01:00
};
mcbsp3_fck: mcbsp3_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
};
mcbsp4_mux_fck: mcbsp4_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <2>;
ARM: dts: omap24xx: add minimal l4 bus layout with control module support This patch creates an l4 / l4-wkup interconnects for omap2420 / omap2430 SoCs, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the new SCM node as the clock provider. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-02-12 09:38:16 +01:00
reg = <0x78>;
ARM: dts: omap2 clock data This patch creates a unique node for each clock in the OMAP2 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-02-21 16:05:02 +01:00
};
mcbsp4_fck: mcbsp4_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
};
mcbsp5_mux_fck: mcbsp5_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
ARM: dts: omap24xx: add minimal l4 bus layout with control module support This patch creates an l4 / l4-wkup interconnects for omap2420 / omap2430 SoCs, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the new SCM node as the clock provider. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-02-12 09:38:16 +01:00
reg = <0x78>;
ARM: dts: omap2 clock data This patch creates a unique node for each clock in the OMAP2 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-02-21 16:05:02 +01:00
};
mcbsp5_fck: mcbsp5_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
};
};
&prcm_clocks {
iva2_1_gate_ick: iva2_1_gate_ick {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&dsp_fck>;
ti,bit-shift = <0>;
reg = <0x0800>;
};
iva2_1_div_ick: iva2_1_div_ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&dsp_fck>;
ti,bit-shift = <5>;
ti,max-div = <3>;
reg = <0x0840>;
ti,index-starts-at-one;
};
iva2_1_ick: iva2_1_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
};
mdm_gate_ick: mdm_gate_ick {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&core_ck>;
ti,bit-shift = <0>;
reg = <0x0c10>;
};
mdm_div_ick: mdm_div_ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_ck>;
reg = <0x0c40>;
ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
};
mdm_ick: mdm_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
};
mdm_osc_ck: mdm_osc_ck {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&osc_ck>;
ti,bit-shift = <1>;
reg = <0x0c00>;
};
mcbsp3_ick: mcbsp3_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <3>;
reg = <0x0214>;
};
mcbsp3_gate_fck: mcbsp3_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
ti,bit-shift = <3>;
reg = <0x0204>;
};
mcbsp4_ick: mcbsp4_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <4>;
reg = <0x0214>;
};
mcbsp4_gate_fck: mcbsp4_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x0204>;
};
mcbsp5_ick: mcbsp5_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <5>;
reg = <0x0214>;
};
mcbsp5_gate_fck: mcbsp5_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
ti,bit-shift = <5>;
reg = <0x0204>;
};
mcspi3_ick: mcspi3_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <9>;
reg = <0x0214>;
};
mcspi3_fck: mcspi3_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_48m_ck>;
ti,bit-shift = <9>;
reg = <0x0204>;
};
icr_ick: icr_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
ti,bit-shift = <6>;
reg = <0x0410>;
};
i2chs1_fck: i2chs1_fck {
#clock-cells = <0>;
compatible = "ti,omap2430-interface-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <19>;
reg = <0x0204>;
};
i2chs2_fck: i2chs2_fck {
#clock-cells = <0>;
compatible = "ti,omap2430-interface-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <20>;
reg = <0x0204>;
};
usbhs_ick: usbhs_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l3_ck>;
ti,bit-shift = <6>;
reg = <0x0214>;
};
mmchs1_ick: mmchs1_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <7>;
reg = <0x0214>;
};
mmchs1_fck: mmchs1_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <7>;
reg = <0x0204>;
};
mmchs2_ick: mmchs2_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <8>;
reg = <0x0214>;
};
mmchs2_fck: mmchs2_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <8>;
reg = <0x0204>;
};
gpio5_ick: gpio5_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <10>;
reg = <0x0214>;
};
gpio5_fck: gpio5_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
ti,bit-shift = <10>;
reg = <0x0204>;
};
mdm_intc_ick: mdm_intc_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <11>;
reg = <0x0214>;
};
mmchsdb1_fck: mmchsdb1_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
ti,bit-shift = <16>;
reg = <0x0204>;
};
mmchsdb2_fck: mmchsdb2_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
ti,bit-shift = <17>;
reg = <0x0204>;
};
};
&prcm_clockdomains {
gfx_clkdm: gfx_clkdm {
compatible = "ti,clockdomain";
clocks = <&gfx_ick>;
};
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
};
wkup_clkdm: wkup_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
<&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
<&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
<&icr_ick>;
};
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss_ick>, <&dss_54m_fck>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
<&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
<&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
<&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
<&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
<&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
<&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
<&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
<&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
<&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
<&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
<&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
<&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
<&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
<&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
<&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
<&mmchsdb2_fck>;
};
mdm_clkdm: mdm_clkdm {
compatible = "ti,clockdomain";
clocks = <&mdm_osc_ck>;
};
};
&func_96m_ck {
compatible = "ti,mux-clock";
clocks = <&apll96_ck>, <&alt_ck>;
ti,bit-shift = <4>;
reg = <0x0540>;
};
&dsp_div_fck {
ti,max-div = <4>;
ti,index-starts-at-one;
};
&ssi_ssr_sst_div_fck {
ti,max-div = <5>;
ti,index-starts-at-one;
};
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