linux/drivers/clk/Makefile

# common clock types
obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
				   clk-mux.o clk-divider.o clk-fixed-factor.o
# SoCs specific
obj-$(CONFIG_ARCH_NOMADIK)	+= clk-nomadik.o
obj-$(CONFIG_ARCH_HIGHBANK)	+= clk-highbank.o
obj-$(CONFIG_ARCH_MXS)		+= mxs/
obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
obj-$(CONFIG_PLAT_SPEAR)	+= spear/
obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/

# Chip specific
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
ARM: u300: convert to common clock This converts the U300 clock implementation over to use the common struct clk and moves the implementation down into drivers/clk. Since VCO isn't used in tree it was removed, it's not hard to put it back in if need be. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: trivial Makefile conflict] Signed-off-by: Mike Turquette <mturquette@linaro.org> 2012-06-19 23:44:25 +02:00			`# common clock types`
ARM: 6483/1: arm & sh: factorised duplicated clkdev.c factorise some generic infrastructure to assist looking up struct clks for the ARM & SH architecture. as the code is identical at 99% put the arch specific code for allocation as example in asm/clkdev.h Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2010-11-17 10:04:33 +01:00			`obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o`
clk: basic clock hardware types Many platforms support simple gateable clocks, fixed-rate clocks, adjustable divider clocks and multi-parent multiplexer clocks. This patch introduces basic clock types for the above-mentioned hardware which share some common characteristics. Based on original work by Jeremy Kerr and contribution by Jamie Iles. Dividers and multiplexor clocks originally contributed by Richard Zhao & Sascha Hauer. Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Mike Turquette <mturquette@ti.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Jeremy Kerr <jeremy.kerr@canonical.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Arnd Bergman <arnd.bergmann@linaro.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Jamie Iles <jamie@jamieiles.com> Cc: Richard Zhao <richard.zhao@linaro.org> Cc: Saravana Kannan <skannan@codeaurora.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Amit Kucheria <amit.kucheria@linaro.org> Cc: Deepak Saxena <dsaxena@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Arnd Bergmann <arnd@arndb.de> 2012-03-16 07:11:20 +01:00			`obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \`
clk: add a fixed factor clock Having fixed factors/dividers in hardware is a common pattern, so add a basic clock type doing this. It basically describes a fixed factor clock using a nominator and a denominator. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Viresh Kumar <viresh.kumar@st.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> [mturquette@linaro.org: constify parent_names in static init macro] [mturquette@linaro.org: copy/paste bug from mux in static init macro] [mturquette@linaro.org: fix error handling in clk_register_fixed_factor] [mturquette@linaro.org: improve division accuracy; thanks to Saravana] Signed-off-by: Mike Turquette <mturquette@linaro.org> 2012-05-03 12:06:14 +02:00			`clk-mux.o clk-divider.o clk-fixed-factor.o`
SPEAr: clk: Add VCO-PLL Synthesizer clock All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> 2012-04-10 05:32:35 +02:00			`# SoCs specific`
ARM: nomadik: convert to generic clock Remove more custom stuff by simply converting the Nomadik machine to use generic clocks and move the driver to drivers/clk. Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2012-01-11 13:52:34 +01:00			`obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o`
clk: add highbank clock support This adds real clock support to Calxeda Highbank SOC using the common clock infrastructure. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [mturquette@linaro.org: fixed up invalid writes to const struct member] Signed-off-by: Mike Turquette <mturquette@linaro.org> 2012-03-14 00:19:19 +01:00			`obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o`
ARM: mxs: switch to common clk framework It switches mxs clock support to common clk framework based drivers. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> 2012-04-28 18:02:39 +02:00			`obj-$(CONFIG_ARCH_MXS) += mxs/`
ARM: socfpga: initial support for Altera's SOCFPGA platform Adding core definitions for Altera's SOCFPGA ARM platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> 2012-07-19 00:07:18 +02:00			`obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/`
SPEAr: clk: Add VCO-PLL Synthesizer clock All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> 2012-04-10 05:32:35 +02:00			`obj-$(CONFIG_PLAT_SPEAR) += spear/`
ARM: u300: convert to common clock This converts the U300 clock implementation over to use the common struct clk and moves the implementation down into drivers/clk. Since VCO isn't used in tree it was removed, it's not hard to put it back in if need be. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: trivial Makefile conflict] Signed-off-by: Mike Turquette <mturquette@linaro.org> 2012-06-19 23:44:25 +02:00			`obj-$(CONFIG_ARCH_U300) += clk-u300.o`
clk: add versatile ICST307 driver The ICST307 VCO clock has a shared driver in the ARM architecture. This patch provides a wrapper into the common clock framework so we can use the implementation in the ARM architecture without duplicating the code until all ARM platforms using this VCO are moved over. At that point we can merge the driver from the ARM platform into the generic file altogether. Cc: Russell King <linux@arm.linux.org.uk> Cc: Mike Turquette <mturquette@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: removed versatile Kconfig] Signed-off-by: Mike Turquette <mturquette@linaro.org> 2012-06-11 17:29:54 +02:00			`obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/`
clk: wm831x: Add initial WM831x clock driver The WM831x and WM832x series of PMICs contain a flexible clocking subsystem intended to provide always on and system core clocks. It features: - A 32.768kHz crystal oscillator which can optionally be used to pass through an externally generated clock. - A FLL which can be clocked from either the 32.768kHz oscillator or the CLKIN pin. - A CLKOUT pin which can bring out either the oscillator or the FLL output. - The 32.768kHz clock can also optionally be brought out on the GPIO pins of the device. This driver fully supports the 32.768kHz oscillator and CLKOUT. The FLL is supported only in AUTO mode, the full flexibility of the FLL cannot currently be used. Due to a lack of access to systems where the core SoC has been converted to use the generic clock API this driver has been compile tested only. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2012-05-17 11:04:57 +02:00
			`# Chip specific`
			`obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o`