2017-01-24 23:57:52 +01:00
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/*
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* intel_hdmi_audio.c - Intel HDMI audio driver
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*
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* Copyright (C) 2016 Intel Corp
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* Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
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* Ramesh Babu K V <ramesh.babu@intel.com>
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* Vaibhav Agarwal <vaibhav.agarwal@intel.com>
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* Jerome Anand <jerome.anand@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* ALSA driver for Intel HDMI audio
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*/
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2017-02-02 16:19:03 +01:00
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#include <linux/types.h>
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2017-01-24 23:57:52 +01:00
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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2017-01-31 13:52:22 +01:00
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#include <linux/interrupt.h>
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2017-02-02 16:19:03 +01:00
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#include <linux/pm_runtime.h>
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2017-02-02 22:03:22 +01:00
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#include <linux/dma-mapping.h>
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2017-01-24 23:57:52 +01:00
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#include <asm/cacheflush.h>
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#include <sound/core.h>
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2017-02-02 16:19:03 +01:00
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#include <sound/asoundef.h>
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#include <sound/pcm.h>
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2017-01-24 23:57:52 +01:00
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/control.h>
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2017-02-02 16:19:03 +01:00
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#include <drm/drm_edid.h>
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2017-01-31 13:52:22 +01:00
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#include <drm/intel_lpe_audio.h>
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2017-01-24 23:57:52 +01:00
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#include "intel_hdmi_audio.h"
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/*standard module options for ALSA. This module supports only one card*/
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static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
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static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
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module_param_named(index, hdmi_card_index, int, 0444);
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MODULE_PARM_DESC(index,
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"Index value for INTEL Intel HDMI Audio controller.");
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module_param_named(id, hdmi_card_id, charp, 0444);
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MODULE_PARM_DESC(id,
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"ID string for INTEL Intel HDMI Audio controller.");
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/*
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* ELD SA bits in the CEA Speaker Allocation data block
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*/
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2017-02-01 16:45:38 +01:00
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static const int eld_speaker_allocation_bits[] = {
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2017-01-24 23:57:52 +01:00
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[0] = FL | FR,
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[1] = LFE,
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[2] = FC,
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[3] = RL | RR,
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[4] = RC,
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[5] = FLC | FRC,
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[6] = RLC | RRC,
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/* the following are not defined in ELD yet */
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[7] = 0,
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};
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/*
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* This is an ordered list!
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*
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* The preceding ones have better chances to be selected by
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* hdmi_channel_allocation().
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*/
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static struct cea_channel_speaker_allocation channel_allocations[] = {
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/* channel: 7 6 5 4 3 2 1 0 */
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{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
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/* 2.1 */
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{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
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/* Dolby Surround */
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{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
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/* surround40 */
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{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
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/* surround41 */
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{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
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/* surround50 */
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{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
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/* surround51 */
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{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
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/* 6.1 */
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{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
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/* surround71 */
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{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
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{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
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{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
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{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
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{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
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{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
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{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
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{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
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{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
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{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
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{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
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{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
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{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
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{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
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{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
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{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
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{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
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{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
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{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
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{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
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{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
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{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
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{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
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{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
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};
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2017-02-01 16:45:38 +01:00
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static const struct channel_map_table map_tables[] = {
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2017-01-24 23:57:52 +01:00
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{ SNDRV_CHMAP_FL, 0x00, FL },
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{ SNDRV_CHMAP_FR, 0x01, FR },
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{ SNDRV_CHMAP_RL, 0x04, RL },
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{ SNDRV_CHMAP_RR, 0x05, RR },
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{ SNDRV_CHMAP_LFE, 0x02, LFE },
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{ SNDRV_CHMAP_FC, 0x03, FC },
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{ SNDRV_CHMAP_RLC, 0x06, RLC },
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{ SNDRV_CHMAP_RRC, 0x07, RRC },
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{} /* terminator */
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};
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/* hardware capability structure */
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2017-02-04 22:05:33 +01:00
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static const struct snd_pcm_hardware had_pcm_hardware = {
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2017-01-24 23:57:52 +01:00
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.info = (SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_DOUBLE |
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SNDRV_PCM_INFO_MMAP|
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_BATCH),
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.formats = (SNDRV_PCM_FMTBIT_S24 |
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SNDRV_PCM_FMTBIT_U24),
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.rates = SNDRV_PCM_RATE_32000 |
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SNDRV_PCM_RATE_44100 |
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SNDRV_PCM_RATE_48000 |
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SNDRV_PCM_RATE_88200 |
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SNDRV_PCM_RATE_96000 |
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SNDRV_PCM_RATE_176400 |
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SNDRV_PCM_RATE_192000,
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.rate_min = HAD_MIN_RATE,
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.rate_max = HAD_MAX_RATE,
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.channels_min = HAD_MIN_CHANNEL,
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.channels_max = HAD_MAX_CHANNEL,
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.buffer_bytes_max = HAD_MAX_BUFFER,
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.period_bytes_min = HAD_MIN_PERIOD_BYTES,
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.period_bytes_max = HAD_MAX_PERIOD_BYTES,
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.periods_min = HAD_MIN_PERIODS,
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.periods_max = HAD_MAX_PERIODS,
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.fifo_size = HAD_FIFO_SIZE,
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};
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2017-02-02 13:00:12 +01:00
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/* Get the active PCM substream;
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* Call had_substream_put() for unreferecing.
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* Don't call this inside had_spinlock, as it takes by itself
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*/
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static struct snd_pcm_substream *
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had_substream_get(struct snd_intelhad *intelhaddata)
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{
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struct snd_pcm_substream *substream;
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unsigned long flags;
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spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
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substream = intelhaddata->stream_info.substream;
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if (substream)
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intelhaddata->stream_info.substream_refcount++;
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spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
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return substream;
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}
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/* Unref the active PCM substream;
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* Don't call this inside had_spinlock, as it takes by itself
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*/
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static void had_substream_put(struct snd_intelhad *intelhaddata)
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{
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unsigned long flags;
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spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
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intelhaddata->stream_info.substream_refcount--;
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spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
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}
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2017-01-24 23:57:52 +01:00
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/* Register access functions */
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2017-02-03 08:50:06 +01:00
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static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
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2017-01-24 23:57:52 +01:00
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{
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2017-01-31 13:52:22 +01:00
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*val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg);
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2017-01-24 23:57:52 +01:00
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}
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2017-02-03 08:50:06 +01:00
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static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
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2017-01-24 23:57:52 +01:00
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{
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2017-01-31 13:52:22 +01:00
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iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg);
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2017-01-24 23:57:52 +01:00
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}
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2017-01-31 13:52:22 +01:00
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/*
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2017-02-02 13:00:12 +01:00
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* enable / disable audio configuration
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*
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2017-02-03 08:50:06 +01:00
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* The normal read/modify should not directly be used on VLV2 for
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2017-01-31 13:52:22 +01:00
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* updating AUD_CONFIG register.
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2017-01-24 23:57:52 +01:00
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* This is because:
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* Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
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* HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
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* clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
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* register. This field should be 1xy binary for configuration with 6 or
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* more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
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* causes the "channels" field to be updated as 0xy binary resulting in
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* bad audio. The fix is to always write the AUD_CONFIG[6:4] with
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* appropriate value when doing read-modify of AUD_CONFIG register.
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*/
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2017-02-04 22:05:33 +01:00
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static void had_enable_audio(struct snd_pcm_substream *substream,
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struct snd_intelhad *intelhaddata,
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bool enable)
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2017-01-24 23:57:52 +01:00
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{
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2017-02-02 15:58:35 +01:00
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union aud_cfg cfg_val = {.regval = 0};
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2017-02-03 08:50:06 +01:00
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u8 channels;
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u32 mask, val;
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2017-01-24 23:57:52 +01:00
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/*
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* If substream is NULL, there is no active stream.
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* In this case just set channels to 2
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*/
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2017-02-02 13:00:12 +01:00
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channels = substream ? substream->runtime->channels : 2;
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2017-02-03 08:50:06 +01:00
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dev_dbg(intelhaddata->dev, "enable %d, ch=%d\n", enable, channels);
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2017-01-24 23:57:52 +01:00
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2017-02-03 08:50:06 +01:00
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cfg_val.regx.num_ch = channels - 2;
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2017-02-02 13:00:12 +01:00
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if (enable)
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2017-02-03 08:50:06 +01:00
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cfg_val.regx.aud_en = 1;
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2017-02-02 13:00:12 +01:00
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mask = AUD_CONFIG_CH_MASK | 1;
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2017-01-24 23:57:52 +01:00
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2017-02-03 08:50:06 +01:00
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had_read_register(intelhaddata, AUD_CONFIG, &val);
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val &= ~mask;
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val |= cfg_val.regval;
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had_write_register(intelhaddata, AUD_CONFIG, val);
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2017-01-24 23:57:52 +01:00
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}
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2017-02-02 13:00:12 +01:00
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/* enable / disable the audio interface */
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2017-02-04 22:05:33 +01:00
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static void had_enable_audio_int(struct snd_intelhad *ctx, bool enable)
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2017-01-31 13:52:22 +01:00
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{
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u32 status_reg;
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if (enable) {
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2017-02-03 08:50:06 +01:00
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had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
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2017-01-31 13:52:22 +01:00
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status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
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2017-02-03 08:50:06 +01:00
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had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
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had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
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2017-01-31 13:52:22 +01:00
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}
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}
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2017-02-04 21:39:56 +01:00
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/* Reset buffer pointers */
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static void had_reset_audio(struct snd_intelhad *intelhaddata)
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2017-01-24 23:57:52 +01:00
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{
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2017-02-04 21:39:56 +01:00
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had_write_register(intelhaddata, AUD_HDMI_STATUS, 1);
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had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
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2017-01-24 23:57:52 +01:00
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}
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2017-01-31 17:09:13 +01:00
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/*
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2017-01-24 23:57:52 +01:00
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* initialize audio channel status registers
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* This function is called in the prepare callback
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*/
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static int had_prog_status_reg(struct snd_pcm_substream *substream,
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struct snd_intelhad *intelhaddata)
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{
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2017-02-02 15:58:35 +01:00
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union aud_cfg cfg_val = {.regval = 0};
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union aud_ch_status_0 ch_stat0 = {.regval = 0};
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union aud_ch_status_1 ch_stat1 = {.regval = 0};
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2017-01-24 23:57:52 +01:00
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int format;
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|
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
|
2017-01-31 17:09:13 +01:00
|
|
|
IEC958_AES0_NONAUDIO) >> 1;
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
|
2017-01-31 17:09:13 +01:00
|
|
|
IEC958_AES3_CON_CLOCK) >> 4;
|
2017-02-02 15:58:35 +01:00
|
|
|
cfg_val.regx.val_bit = ch_stat0.regx.lpcm_id;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
switch (substream->runtime->rate) {
|
|
|
|
case AUD_SAMPLE_RATE_32:
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
|
2017-01-24 23:57:52 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_44_1:
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
|
2017-01-24 23:57:52 +01:00
|
|
|
break;
|
|
|
|
case AUD_SAMPLE_RATE_48:
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
|
2017-01-24 23:57:52 +01:00
|
|
|
break;
|
|
|
|
case AUD_SAMPLE_RATE_88_2:
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
|
2017-01-24 23:57:52 +01:00
|
|
|
break;
|
|
|
|
case AUD_SAMPLE_RATE_96:
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
|
2017-01-24 23:57:52 +01:00
|
|
|
break;
|
|
|
|
case AUD_SAMPLE_RATE_176_4:
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
|
2017-01-24 23:57:52 +01:00
|
|
|
break;
|
|
|
|
case AUD_SAMPLE_RATE_192:
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
|
2017-01-24 23:57:52 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
/* control should never come here */
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2017-01-31 17:09:13 +01:00
|
|
|
|
2017-01-30 17:23:39 +01:00
|
|
|
had_write_register(intelhaddata,
|
2017-02-02 15:58:35 +01:00
|
|
|
AUD_CH_STATUS_0, ch_stat0.regval);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
format = substream->runtime->format;
|
|
|
|
|
|
|
|
if (format == SNDRV_PCM_FORMAT_S16_LE) {
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
|
|
|
|
ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
|
2017-01-24 23:57:52 +01:00
|
|
|
} else if (format == SNDRV_PCM_FORMAT_S24_LE) {
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
|
|
|
|
ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
|
2017-01-24 23:57:52 +01:00
|
|
|
} else {
|
2017-02-02 15:58:35 +01:00
|
|
|
ch_stat1.regx.max_wrd_len = 0;
|
|
|
|
ch_stat1.regx.wrd_len = 0;
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
2017-01-31 17:09:13 +01:00
|
|
|
|
2017-01-30 17:23:39 +01:00
|
|
|
had_write_register(intelhaddata,
|
2017-02-02 15:58:35 +01:00
|
|
|
AUD_CH_STATUS_1, ch_stat1.regval);
|
2017-01-24 23:57:52 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-30 16:09:11 +01:00
|
|
|
/*
|
2017-01-24 23:57:52 +01:00
|
|
|
* function to initialize audio
|
|
|
|
* registers and buffer confgiuration registers
|
|
|
|
* This function is called in the prepare callback
|
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_intelhad *intelhaddata)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
2017-02-02 15:58:35 +01:00
|
|
|
union aud_cfg cfg_val = {.regval = 0};
|
|
|
|
union aud_buf_config buf_cfg = {.regval = 0};
|
2017-01-24 23:57:52 +01:00
|
|
|
u8 channels;
|
|
|
|
|
|
|
|
had_prog_status_reg(substream, intelhaddata);
|
|
|
|
|
2017-02-02 15:58:35 +01:00
|
|
|
buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
|
|
|
|
buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
|
|
|
|
buf_cfg.regx.aud_delay = 0;
|
|
|
|
had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
channels = substream->runtime->channels;
|
2017-02-02 15:58:35 +01:00
|
|
|
cfg_val.regx.num_ch = channels - 2;
|
2017-01-24 23:57:52 +01:00
|
|
|
if (channels <= 2)
|
2017-02-02 15:58:35 +01:00
|
|
|
cfg_val.regx.layout = LAYOUT0;
|
2017-01-24 23:57:52 +01:00
|
|
|
else
|
2017-02-02 15:58:35 +01:00
|
|
|
cfg_val.regx.layout = LAYOUT1;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-02 15:58:35 +01:00
|
|
|
cfg_val.regx.val_bit = 1;
|
2017-02-03 08:50:06 +01:00
|
|
|
|
|
|
|
/* fix up the DP bits */
|
|
|
|
if (intelhaddata->dp_output) {
|
|
|
|
cfg_val.regx.dp_modei = 1;
|
|
|
|
cfg_val.regx.set = 1;
|
|
|
|
}
|
|
|
|
|
2017-02-02 15:58:35 +01:00
|
|
|
had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
|
2017-01-24 23:57:52 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Compute derived values in channel_allocations[].
|
|
|
|
*/
|
|
|
|
static void init_channel_allocations(void)
|
|
|
|
{
|
|
|
|
int i, j;
|
|
|
|
struct cea_channel_speaker_allocation *p;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
|
|
|
|
p = channel_allocations + i;
|
|
|
|
p->channels = 0;
|
|
|
|
p->spk_mask = 0;
|
|
|
|
for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
|
|
|
|
if (p->speakers[j]) {
|
|
|
|
p->channels++;
|
|
|
|
p->spk_mask |= p->speakers[j];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The transformation takes two steps:
|
|
|
|
*
|
|
|
|
* eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
|
|
|
|
* spk_mask => (channel_allocations[]) => ai->CA
|
|
|
|
*
|
|
|
|
* TODO: it could select the wrong CA from multiple candidates.
|
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static int had_channel_allocation(struct snd_intelhad *intelhaddata,
|
|
|
|
int channels)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int ca = 0;
|
|
|
|
int spk_mask = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CA defaults to 0 for basic stereo audio
|
|
|
|
*/
|
|
|
|
if (channels <= 2)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* expand ELD's speaker allocation mask
|
|
|
|
*
|
|
|
|
* ELD tells the speaker mask in a compact(paired) form,
|
|
|
|
* expand ELD's notions to match the ones used by Audio InfoFrame.
|
|
|
|
*/
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
|
2017-02-02 15:37:11 +01:00
|
|
|
if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
|
2017-01-24 23:57:52 +01:00
|
|
|
spk_mask |= eld_speaker_allocation_bits[i];
|
|
|
|
}
|
|
|
|
|
|
|
|
/* search for the first working match in the CA table */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
|
|
|
|
if (channels == channel_allocations[i].channels &&
|
|
|
|
(spk_mask & channel_allocations[i].spk_mask) ==
|
|
|
|
channel_allocations[i].spk_mask) {
|
|
|
|
ca = channel_allocations[i].ca_index;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
return ca;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* from speaker bit mask to ALSA API channel position */
|
|
|
|
static int spk_to_chmap(int spk)
|
|
|
|
{
|
2017-02-01 16:45:38 +01:00
|
|
|
const struct channel_map_table *t = map_tables;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
for (; t->map; t++) {
|
|
|
|
if (t->spk_mask == spk)
|
|
|
|
return t->map;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-31 13:57:58 +01:00
|
|
|
static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
2017-01-31 17:09:13 +01:00
|
|
|
int i, c;
|
2017-01-24 23:57:52 +01:00
|
|
|
int spk_mask = 0;
|
|
|
|
struct snd_pcm_chmap_elem *chmap;
|
|
|
|
u8 eld_high, eld_high_mask = 0xF0;
|
|
|
|
u8 high_msb;
|
|
|
|
|
|
|
|
chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
|
2017-01-31 17:09:13 +01:00
|
|
|
if (!chmap) {
|
2017-01-24 23:57:52 +01:00
|
|
|
intelhaddata->chmap->chmap = NULL;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-02-02 15:37:11 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
|
|
|
|
intelhaddata->eld[DRM_ELD_SPEAKER]);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
/* WA: Fix the max channel supported to 8 */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Sink may support more than 8 channels, if eld_high has more than
|
|
|
|
* one bit set. SOC supports max 8 channels.
|
|
|
|
* Refer eld_speaker_allocation_bits, for sink speaker allocation
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
|
2017-02-02 15:37:11 +01:00
|
|
|
eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
|
2017-01-24 23:57:52 +01:00
|
|
|
if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
|
|
|
|
/* eld_high & (eld_high-1): if more than 1 bit set */
|
|
|
|
/* 0x1F: 7 channels */
|
|
|
|
for (i = 1; i < 4; i++) {
|
|
|
|
high_msb = eld_high & (0x80 >> i);
|
|
|
|
if (high_msb) {
|
2017-02-02 15:37:11 +01:00
|
|
|
intelhaddata->eld[DRM_ELD_SPEAKER] &=
|
2017-01-24 23:57:52 +01:00
|
|
|
high_msb | 0xF;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
|
2017-02-02 15:37:11 +01:00
|
|
|
if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
|
2017-01-24 23:57:52 +01:00
|
|
|
spk_mask |= eld_speaker_allocation_bits[i];
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
|
|
|
|
if (spk_mask == channel_allocations[i].spk_mask) {
|
|
|
|
for (c = 0; c < channel_allocations[i].channels; c++) {
|
|
|
|
chmap->map[c] = spk_to_chmap(
|
|
|
|
channel_allocations[i].speakers[
|
2017-01-31 17:09:13 +01:00
|
|
|
(MAX_SPEAKERS - 1) - c]);
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
|
|
|
chmap->channels = channel_allocations[i].channels;
|
|
|
|
intelhaddata->chmap->chmap = chmap;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (i >= ARRAY_SIZE(channel_allocations)) {
|
|
|
|
intelhaddata->chmap->chmap = NULL;
|
|
|
|
kfree(chmap);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ALSA API channel-map control callbacks
|
|
|
|
*/
|
|
|
|
static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
|
|
|
|
struct snd_ctl_elem_info *uinfo)
|
|
|
|
{
|
|
|
|
struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
|
|
|
|
struct snd_intelhad *intelhaddata = info->private_data;
|
|
|
|
|
2017-02-02 17:46:49 +01:00
|
|
|
if (!intelhaddata->connected)
|
2017-01-24 23:57:52 +01:00
|
|
|
return -ENODEV;
|
|
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
|
|
|
|
uinfo->count = HAD_MAX_CHANNEL;
|
|
|
|
uinfo->value.integer.min = 0;
|
|
|
|
uinfo->value.integer.max = SNDRV_CHMAP_LAST;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
|
|
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
|
|
{
|
|
|
|
struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
|
|
|
|
struct snd_intelhad *intelhaddata = info->private_data;
|
2017-01-31 17:09:13 +01:00
|
|
|
int i;
|
2017-01-24 23:57:52 +01:00
|
|
|
const struct snd_pcm_chmap_elem *chmap;
|
|
|
|
|
2017-02-02 17:46:49 +01:00
|
|
|
if (!intelhaddata->connected)
|
2017-01-24 23:57:52 +01:00
|
|
|
return -ENODEV;
|
2017-02-01 17:24:02 +01:00
|
|
|
|
|
|
|
mutex_lock(&intelhaddata->mutex);
|
|
|
|
if (!intelhaddata->chmap->chmap) {
|
|
|
|
mutex_unlock(&intelhaddata->mutex);
|
2017-01-24 23:57:52 +01:00
|
|
|
return -ENODATA;
|
2017-02-01 17:24:02 +01:00
|
|
|
}
|
|
|
|
|
2017-01-24 23:57:52 +01:00
|
|
|
chmap = intelhaddata->chmap->chmap;
|
2017-01-31 15:49:15 +01:00
|
|
|
for (i = 0; i < chmap->channels; i++)
|
2017-01-24 23:57:52 +01:00
|
|
|
ucontrol->value.integer.value[i] = chmap->map[i];
|
2017-02-01 17:24:02 +01:00
|
|
|
mutex_unlock(&intelhaddata->mutex);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
|
|
|
|
struct snd_pcm *pcm)
|
|
|
|
{
|
2017-01-31 17:09:13 +01:00
|
|
|
int err;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
|
|
|
|
NULL, 0, (unsigned long)intelhaddata,
|
|
|
|
&intelhaddata->chmap);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
intelhaddata->chmap->private_data = intelhaddata;
|
2017-01-31 16:11:27 +01:00
|
|
|
intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
|
|
|
|
intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
|
2017-01-24 23:57:52 +01:00
|
|
|
intelhaddata->chmap->chmap = NULL;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-30 16:09:11 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* Initialize Data Island Packets registers
|
2017-01-24 23:57:52 +01:00
|
|
|
* This function is called in the prepare callback
|
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static void had_prog_dip(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_intelhad *intelhaddata)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
int i;
|
2017-02-02 15:58:35 +01:00
|
|
|
union aud_ctrl_st ctrl_state = {.regval = 0};
|
|
|
|
union aud_info_frame2 frame2 = {.regval = 0};
|
|
|
|
union aud_info_frame3 frame3 = {.regval = 0};
|
2017-01-24 23:57:52 +01:00
|
|
|
u8 checksum = 0;
|
2017-01-31 21:16:52 +01:00
|
|
|
u32 info_frame;
|
2017-01-24 23:57:52 +01:00
|
|
|
int channels;
|
2017-02-02 17:06:38 +01:00
|
|
|
int ca;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
channels = substream->runtime->channels;
|
|
|
|
|
2017-02-02 15:58:35 +01:00
|
|
|
had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-04 22:05:33 +01:00
|
|
|
ca = had_channel_allocation(intelhaddata, channels);
|
2017-01-31 21:16:52 +01:00
|
|
|
if (intelhaddata->dp_output) {
|
|
|
|
info_frame = DP_INFO_FRAME_WORD1;
|
2017-02-02 17:06:38 +01:00
|
|
|
frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
|
2017-01-31 21:16:52 +01:00
|
|
|
} else {
|
|
|
|
info_frame = HDMI_INFO_FRAME_WORD1;
|
2017-02-02 15:58:35 +01:00
|
|
|
frame2.regx.chnl_cnt = substream->runtime->channels - 1;
|
2017-02-02 17:06:38 +01:00
|
|
|
frame3.regx.chnl_alloc = ca;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/* Calculte the byte wide checksum for all valid DIP words */
|
2017-01-31 21:16:52 +01:00
|
|
|
for (i = 0; i < BYTES_PER_WORD; i++)
|
2017-02-02 15:58:35 +01:00
|
|
|
checksum += (info_frame >> (i * 8)) & 0xff;
|
2017-01-31 21:16:52 +01:00
|
|
|
for (i = 0; i < BYTES_PER_WORD; i++)
|
2017-02-02 15:58:35 +01:00
|
|
|
checksum += (frame2.regval >> (i * 8)) & 0xff;
|
2017-01-31 21:16:52 +01:00
|
|
|
for (i = 0; i < BYTES_PER_WORD; i++)
|
2017-02-02 15:58:35 +01:00
|
|
|
checksum += (frame3.regval >> (i * 8)) & 0xff;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-02 15:58:35 +01:00
|
|
|
frame2.regx.chksum = -(checksum);
|
2017-01-31 21:16:52 +01:00
|
|
|
}
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-01-31 18:14:15 +01:00
|
|
|
had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
|
2017-02-02 15:58:35 +01:00
|
|
|
had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
|
|
|
|
had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
/* program remaining DIP words with zero */
|
|
|
|
for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
|
2017-01-31 18:14:15 +01:00
|
|
|
had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-02 15:58:35 +01:00
|
|
|
ctrl_state.regx.dip_freq = 1;
|
|
|
|
ctrl_state.regx.dip_en_sta = 1;
|
|
|
|
had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* Programs buffer address and length registers
|
2017-01-24 23:57:52 +01:00
|
|
|
* This function programs ring buffer address and length into registers.
|
|
|
|
*/
|
2017-02-02 13:00:12 +01:00
|
|
|
static int snd_intelhad_prog_buffer(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_intelhad *intelhaddata,
|
|
|
|
int start, int end)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
u32 ring_buf_addr, ring_buf_size, period_bytes;
|
|
|
|
u8 i, num_periods;
|
|
|
|
|
|
|
|
ring_buf_addr = substream->runtime->dma_addr;
|
|
|
|
ring_buf_size = snd_pcm_lib_buffer_bytes(substream);
|
|
|
|
intelhaddata->stream_info.ring_buf_size = ring_buf_size;
|
|
|
|
period_bytes = frames_to_bytes(substream->runtime,
|
|
|
|
substream->runtime->period_size);
|
|
|
|
num_periods = substream->runtime->periods;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* buffer addr should be 64 byte aligned, period bytes
|
|
|
|
* will be used to calculate addr offset
|
|
|
|
*/
|
|
|
|
period_bytes &= ~0x3F;
|
|
|
|
|
|
|
|
/* Hardware supports MAX_PERIODS buffers */
|
|
|
|
if (end >= HAD_MAX_PERIODS)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
for (i = start; i <= end; i++) {
|
|
|
|
/* Program the buf registers with addr and len */
|
|
|
|
intelhaddata->buf_info[i].buf_addr = ring_buf_addr +
|
|
|
|
(i * period_bytes);
|
|
|
|
if (i < num_periods-1)
|
|
|
|
intelhaddata->buf_info[i].buf_size = period_bytes;
|
|
|
|
else
|
|
|
|
intelhaddata->buf_info[i].buf_size = ring_buf_size -
|
2017-01-31 17:09:13 +01:00
|
|
|
(i * period_bytes);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-01-30 17:23:39 +01:00
|
|
|
had_write_register(intelhaddata,
|
|
|
|
AUD_BUF_A_ADDR + (i * HAD_REG_WIDTH),
|
2017-01-24 23:57:52 +01:00
|
|
|
intelhaddata->buf_info[i].buf_addr |
|
|
|
|
BIT(0) | BIT(1));
|
2017-01-30 17:23:39 +01:00
|
|
|
had_write_register(intelhaddata,
|
|
|
|
AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
|
2017-01-24 23:57:52 +01:00
|
|
|
period_bytes);
|
|
|
|
intelhaddata->buf_info[i].is_valid = true;
|
|
|
|
}
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "%s:buf[%d-%d] addr=%#x and size=%d\n",
|
|
|
|
__func__, start, end,
|
|
|
|
intelhaddata->buf_info[start].buf_addr,
|
|
|
|
intelhaddata->buf_info[start].buf_size);
|
2017-01-24 23:57:52 +01:00
|
|
|
intelhaddata->valid_buf_cnt = num_periods;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-31 13:57:58 +01:00
|
|
|
static int snd_intelhad_read_len(struct snd_intelhad *intelhaddata)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
int i, retval = 0;
|
|
|
|
u32 len[4];
|
|
|
|
|
|
|
|
for (i = 0; i < 4 ; i++) {
|
2017-01-30 17:23:39 +01:00
|
|
|
had_read_register(intelhaddata,
|
|
|
|
AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
|
|
|
|
&len[i]);
|
2017-01-24 23:57:52 +01:00
|
|
|
if (!len[i])
|
|
|
|
retval++;
|
|
|
|
}
|
|
|
|
if (retval != 1) {
|
|
|
|
for (i = 0; i < 4 ; i++)
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "buf[%d] size=%d\n",
|
|
|
|
i, len[i]);
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2017-01-31 21:16:52 +01:00
|
|
|
static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
|
|
|
|
{
|
|
|
|
u32 maud_val;
|
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/* Select maud according to DP 1.2 spec */
|
2017-01-31 21:16:52 +01:00
|
|
|
if (link_rate == DP_2_7_GHZ) {
|
|
|
|
switch (aud_samp_freq) {
|
|
|
|
case AUD_SAMPLE_RATE_32:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_44_1:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_48:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_88_2:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_96:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_176_4:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HAD_MAX_RATE:
|
|
|
|
maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
maud_val = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (link_rate == DP_1_62_GHZ) {
|
|
|
|
switch (aud_samp_freq) {
|
|
|
|
case AUD_SAMPLE_RATE_32:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_44_1:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_48:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_88_2:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_96:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_176_4:
|
|
|
|
maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HAD_MAX_RATE:
|
|
|
|
maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
maud_val = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
maud_val = -EINVAL;
|
|
|
|
|
|
|
|
return maud_val;
|
|
|
|
}
|
|
|
|
|
2017-01-30 16:09:11 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* Program HDMI audio CTS value
|
2017-01-24 23:57:52 +01:00
|
|
|
*
|
|
|
|
* @aud_samp_freq: sampling frequency of audio data
|
|
|
|
* @tmds: sampling frequency of the display data
|
2017-02-04 22:05:33 +01:00
|
|
|
* @link_rate: DP link rate
|
2017-01-24 23:57:52 +01:00
|
|
|
* @n_param: N value, depends on aud_samp_freq
|
2017-02-04 22:05:33 +01:00
|
|
|
* @intelhaddata: substream private data
|
2017-01-24 23:57:52 +01:00
|
|
|
*
|
|
|
|
* Program CTS register based on the audio and display sampling frequency
|
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
|
|
|
|
u32 n_param, struct snd_intelhad *intelhaddata)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
u32 cts_val;
|
|
|
|
u64 dividend, divisor;
|
|
|
|
|
2017-01-31 21:16:52 +01:00
|
|
|
if (intelhaddata->dp_output) {
|
|
|
|
/* Substitute cts_val with Maud according to DP 1.2 spec*/
|
|
|
|
cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
|
|
|
|
} else {
|
|
|
|
/* Calculate CTS according to HDMI 1.3a spec*/
|
|
|
|
dividend = (u64)tmds * n_param*1000;
|
|
|
|
divisor = 128 * aud_samp_freq;
|
|
|
|
cts_val = div64_u64(dividend, divisor);
|
|
|
|
}
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
|
2017-01-31 21:16:52 +01:00
|
|
|
tmds, n_param, cts_val);
|
2017-01-30 17:23:39 +01:00
|
|
|
had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static int had_calculate_n_value(u32 aud_samp_freq)
|
|
|
|
{
|
2017-01-31 17:09:13 +01:00
|
|
|
int n_val;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
/* Select N according to HDMI 1.3a spec*/
|
|
|
|
switch (aud_samp_freq) {
|
|
|
|
case AUD_SAMPLE_RATE_32:
|
|
|
|
n_val = 4096;
|
2017-01-31 17:09:13 +01:00
|
|
|
break;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_44_1:
|
|
|
|
n_val = 6272;
|
2017-01-31 17:09:13 +01:00
|
|
|
break;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_48:
|
|
|
|
n_val = 6144;
|
2017-01-31 17:09:13 +01:00
|
|
|
break;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_88_2:
|
|
|
|
n_val = 12544;
|
2017-01-31 17:09:13 +01:00
|
|
|
break;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_96:
|
|
|
|
n_val = 12288;
|
2017-01-31 17:09:13 +01:00
|
|
|
break;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
case AUD_SAMPLE_RATE_176_4:
|
|
|
|
n_val = 25088;
|
2017-01-31 17:09:13 +01:00
|
|
|
break;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
case HAD_MAX_RATE:
|
|
|
|
n_val = 24576;
|
2017-01-31 17:09:13 +01:00
|
|
|
break;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
default:
|
|
|
|
n_val = -EINVAL;
|
2017-01-31 17:09:13 +01:00
|
|
|
break;
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
|
|
|
return n_val;
|
|
|
|
}
|
|
|
|
|
2017-01-30 16:09:11 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* Program HDMI audio N value
|
2017-01-24 23:57:52 +01:00
|
|
|
*
|
|
|
|
* @aud_samp_freq: sampling frequency of audio data
|
|
|
|
* @n_param: N value, depends on aud_samp_freq
|
2017-02-04 22:05:33 +01:00
|
|
|
* @intelhaddata: substream private data
|
2017-01-24 23:57:52 +01:00
|
|
|
*
|
|
|
|
* This function is called in the prepare callback.
|
|
|
|
* It programs based on the audio and display sampling frequency
|
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
|
|
|
|
struct snd_intelhad *intelhaddata)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
2017-01-31 17:09:13 +01:00
|
|
|
int n_val;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-01-31 21:16:52 +01:00
|
|
|
if (intelhaddata->dp_output) {
|
|
|
|
/*
|
|
|
|
* According to DP specs, Maud and Naud values hold
|
|
|
|
* a relationship, which is stated as:
|
|
|
|
* Maud/Naud = 512 * fs / f_LS_Clk
|
|
|
|
* where, fs is the sampling frequency of the audio stream
|
|
|
|
* and Naud is 32768 for Async clock.
|
|
|
|
*/
|
|
|
|
|
|
|
|
n_val = DP_NAUD_VAL;
|
|
|
|
} else
|
|
|
|
n_val = had_calculate_n_value(aud_samp_freq);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
if (n_val < 0)
|
|
|
|
return n_val;
|
|
|
|
|
2017-01-30 17:23:39 +01:00
|
|
|
had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
|
2017-01-24 23:57:52 +01:00
|
|
|
*n_param = n_val;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-02-02 16:19:03 +01:00
|
|
|
#define MAX_CNT 0xFF
|
|
|
|
|
2017-01-31 13:57:58 +01:00
|
|
|
static void snd_intelhad_handle_underrun(struct snd_intelhad *intelhaddata)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
2017-01-31 16:46:44 +01:00
|
|
|
u32 hdmi_status = 0, i = 0;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
/* Handle Underrun interrupt within Audio Unit */
|
2017-01-30 17:23:39 +01:00
|
|
|
had_write_register(intelhaddata, AUD_CONFIG, 0);
|
2017-01-24 23:57:52 +01:00
|
|
|
/* Reset buffer pointers */
|
2017-02-04 21:39:56 +01:00
|
|
|
had_reset_audio(intelhaddata);
|
2017-01-31 17:09:13 +01:00
|
|
|
/*
|
2017-01-24 23:57:52 +01:00
|
|
|
* The interrupt status 'sticky' bits might not be cleared by
|
|
|
|
* setting '1' to that bit once...
|
|
|
|
*/
|
|
|
|
do { /* clear bit30, 31 AUD_HDMI_STATUS */
|
2017-01-31 18:14:15 +01:00
|
|
|
had_read_register(intelhaddata, AUD_HDMI_STATUS,
|
2017-01-30 17:23:39 +01:00
|
|
|
&hdmi_status);
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "HDMI status =0x%x\n", hdmi_status);
|
2017-01-24 23:57:52 +01:00
|
|
|
if (hdmi_status & AUD_CONFIG_MASK_UNDERRUN) {
|
|
|
|
i++;
|
2017-01-30 17:23:39 +01:00
|
|
|
had_write_register(intelhaddata,
|
2017-01-31 18:14:15 +01:00
|
|
|
AUD_HDMI_STATUS, hdmi_status);
|
2017-01-24 23:57:52 +01:00
|
|
|
} else
|
|
|
|
break;
|
|
|
|
} while (i < MAX_CNT);
|
|
|
|
if (i >= MAX_CNT)
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* ALSA PCM open callback
|
2017-01-24 23:57:52 +01:00
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static int had_pcm_open(struct snd_pcm_substream *substream)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
struct snd_intelhad *intelhaddata;
|
|
|
|
struct snd_pcm_runtime *runtime;
|
|
|
|
int retval;
|
|
|
|
|
|
|
|
intelhaddata = snd_pcm_substream_chip(substream);
|
|
|
|
runtime = substream->runtime;
|
|
|
|
|
2017-02-02 14:43:39 +01:00
|
|
|
pm_runtime_get_sync(intelhaddata->dev);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-02 17:46:49 +01:00
|
|
|
if (!intelhaddata->connected) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
|
|
|
|
__func__);
|
2017-01-24 23:57:52 +01:00
|
|
|
retval = -ENODEV;
|
2017-02-01 22:03:26 +01:00
|
|
|
goto error;
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* set the runtime hw parameter with local snd_pcm_hardware struct */
|
2017-02-04 22:05:33 +01:00
|
|
|
runtime->hw = had_pcm_hardware;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
retval = snd_pcm_hw_constraint_integer(runtime,
|
|
|
|
SNDRV_PCM_HW_PARAM_PERIODS);
|
|
|
|
if (retval < 0)
|
2017-02-01 22:03:26 +01:00
|
|
|
goto error;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
/* Make sure, that the period size is always aligned
|
|
|
|
* 64byte boundary
|
|
|
|
*/
|
|
|
|
retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
|
|
|
|
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
|
2017-02-02 17:38:50 +01:00
|
|
|
if (retval < 0)
|
2017-02-01 22:03:26 +01:00
|
|
|
goto error;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-02 17:38:50 +01:00
|
|
|
/* expose PCM substream */
|
2017-02-02 13:00:12 +01:00
|
|
|
spin_lock_irq(&intelhaddata->had_spinlock);
|
|
|
|
intelhaddata->stream_info.substream = substream;
|
|
|
|
intelhaddata->stream_info.substream_refcount++;
|
|
|
|
spin_unlock_irq(&intelhaddata->had_spinlock);
|
|
|
|
|
2017-02-02 17:38:50 +01:00
|
|
|
/* these are cleared in prepare callback, but just to be sure */
|
|
|
|
intelhaddata->curr_buf = 0;
|
|
|
|
intelhaddata->underrun_count = 0;
|
|
|
|
intelhaddata->stream_info.buffer_rendered = 0;
|
|
|
|
|
2017-01-24 23:57:52 +01:00
|
|
|
return retval;
|
2017-02-01 22:03:26 +01:00
|
|
|
error:
|
2017-01-24 23:57:52 +01:00
|
|
|
pm_runtime_put(intelhaddata->dev);
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* ALSA PCM close callback
|
2017-01-24 23:57:52 +01:00
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static int had_pcm_close(struct snd_pcm_substream *substream)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
struct snd_intelhad *intelhaddata;
|
|
|
|
|
|
|
|
intelhaddata = snd_pcm_substream_chip(substream);
|
|
|
|
|
2017-02-02 17:38:50 +01:00
|
|
|
/* unreference and sync with the pending PCM accesses */
|
2017-02-02 13:00:12 +01:00
|
|
|
spin_lock_irq(&intelhaddata->had_spinlock);
|
|
|
|
intelhaddata->stream_info.substream = NULL;
|
|
|
|
intelhaddata->stream_info.substream_refcount--;
|
|
|
|
while (intelhaddata->stream_info.substream_refcount > 0) {
|
|
|
|
spin_unlock_irq(&intelhaddata->had_spinlock);
|
|
|
|
cpu_relax();
|
|
|
|
spin_lock_irq(&intelhaddata->had_spinlock);
|
|
|
|
}
|
|
|
|
spin_unlock_irq(&intelhaddata->had_spinlock);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
pm_runtime_put(intelhaddata->dev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* ALSA PCM hw_params callback
|
2017-01-24 23:57:52 +01:00
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static int had_pcm_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_pcm_hw_params *hw_params)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
2017-01-31 15:49:15 +01:00
|
|
|
struct snd_intelhad *intelhaddata;
|
2017-01-24 23:57:52 +01:00
|
|
|
unsigned long addr;
|
|
|
|
int pages, buf_size, retval;
|
|
|
|
|
2017-01-31 15:49:15 +01:00
|
|
|
intelhaddata = snd_pcm_substream_chip(substream);
|
2017-01-24 23:57:52 +01:00
|
|
|
buf_size = params_buffer_bytes(hw_params);
|
|
|
|
retval = snd_pcm_lib_malloc_pages(substream, buf_size);
|
|
|
|
if (retval < 0)
|
|
|
|
return retval;
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
|
|
|
|
__func__, buf_size);
|
2017-01-24 23:57:52 +01:00
|
|
|
/* mark the pages as uncached region */
|
|
|
|
addr = (unsigned long) substream->runtime->dma_area;
|
|
|
|
pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
|
|
|
|
retval = set_memory_uc(addr, pages);
|
|
|
|
if (retval) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n",
|
|
|
|
retval);
|
2017-01-24 23:57:52 +01:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
memset(substream->runtime->dma_area, 0, buf_size);
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* ALSA PCM hw_free callback
|
2017-01-24 23:57:52 +01:00
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static int had_pcm_hw_free(struct snd_pcm_substream *substream)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
unsigned long addr;
|
|
|
|
u32 pages;
|
|
|
|
|
|
|
|
/* mark back the pages as cached/writeback region before the free */
|
|
|
|
if (substream->runtime->dma_area != NULL) {
|
|
|
|
addr = (unsigned long) substream->runtime->dma_area;
|
|
|
|
pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
|
|
|
|
PAGE_SIZE;
|
|
|
|
set_memory_wb(addr, pages);
|
|
|
|
return snd_pcm_lib_free_pages(substream);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* ALSA PCM trigger callback
|
2017-01-24 23:57:52 +01:00
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
2017-01-31 13:52:22 +01:00
|
|
|
int retval = 0;
|
2017-01-24 23:57:52 +01:00
|
|
|
struct snd_intelhad *intelhaddata;
|
|
|
|
|
|
|
|
intelhaddata = snd_pcm_substream_chip(substream);
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
2017-02-02 14:43:39 +01:00
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
2017-01-24 23:57:52 +01:00
|
|
|
/* Disable local INTRs till register prgmng is done */
|
2017-02-02 17:46:49 +01:00
|
|
|
if (!intelhaddata->connected) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev,
|
|
|
|
"_START: HDMI cable plugged-out\n");
|
2017-01-24 23:57:52 +01:00
|
|
|
retval = -ENODEV;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-02-02 14:57:22 +01:00
|
|
|
intelhaddata->stream_info.running = true;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
/* Enable Audio */
|
2017-02-04 22:05:33 +01:00
|
|
|
had_enable_audio_int(intelhaddata, true);
|
|
|
|
had_enable_audio(substream, intelhaddata, true);
|
2017-01-24 23:57:52 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
2017-02-02 14:43:39 +01:00
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_lock(&intelhaddata->had_spinlock);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-01-31 15:49:15 +01:00
|
|
|
/* Stop reporting BUFFER_DONE/UNDERRUN to above layers */
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-02 14:57:22 +01:00
|
|
|
intelhaddata->stream_info.running = false;
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_unlock(&intelhaddata->had_spinlock);
|
2017-01-24 23:57:52 +01:00
|
|
|
/* Disable Audio */
|
2017-02-04 22:05:33 +01:00
|
|
|
had_enable_audio_int(intelhaddata, false);
|
|
|
|
had_enable_audio(substream, intelhaddata, false);
|
2017-01-24 23:57:52 +01:00
|
|
|
/* Reset buffer pointers */
|
2017-02-04 21:39:56 +01:00
|
|
|
had_reset_audio(intelhaddata);
|
2017-02-04 22:05:33 +01:00
|
|
|
had_enable_audio_int(intelhaddata, false);
|
2017-01-24 23:57:52 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
retval = -EINVAL;
|
|
|
|
}
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* ALSA PCM prepare callback
|
2017-01-24 23:57:52 +01:00
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static int had_pcm_prepare(struct snd_pcm_substream *substream)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
int retval;
|
|
|
|
u32 disp_samp_freq, n_param;
|
2017-01-31 21:16:52 +01:00
|
|
|
u32 link_rate = 0;
|
2017-01-24 23:57:52 +01:00
|
|
|
struct snd_intelhad *intelhaddata;
|
|
|
|
struct snd_pcm_runtime *runtime;
|
|
|
|
|
|
|
|
intelhaddata = snd_pcm_substream_chip(substream);
|
|
|
|
runtime = substream->runtime;
|
|
|
|
|
2017-02-02 17:46:49 +01:00
|
|
|
if (!intelhaddata->connected) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
|
|
|
|
__func__);
|
2017-01-24 23:57:52 +01:00
|
|
|
retval = -ENODEV;
|
|
|
|
goto prep_end;
|
|
|
|
}
|
|
|
|
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "period_size=%d\n",
|
2017-01-24 23:57:52 +01:00
|
|
|
(int)frames_to_bytes(runtime, runtime->period_size));
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
|
|
|
|
dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
|
|
|
|
(int)snd_pcm_lib_buffer_bytes(substream));
|
|
|
|
dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
|
|
|
|
dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-02 17:38:50 +01:00
|
|
|
intelhaddata->curr_buf = 0;
|
|
|
|
intelhaddata->underrun_count = 0;
|
2017-01-31 17:09:13 +01:00
|
|
|
intelhaddata->stream_info.buffer_rendered = 0;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
/* Get N value in KHz */
|
2017-01-31 13:52:22 +01:00
|
|
|
disp_samp_freq = intelhaddata->tmds_clock_speed;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-04 22:05:33 +01:00
|
|
|
retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
|
2017-01-24 23:57:52 +01:00
|
|
|
if (retval) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_err(intelhaddata->dev,
|
|
|
|
"programming N value failed %#x\n", retval);
|
2017-01-24 23:57:52 +01:00
|
|
|
goto prep_end;
|
|
|
|
}
|
2017-01-31 21:16:52 +01:00
|
|
|
|
|
|
|
if (intelhaddata->dp_output)
|
2017-01-31 13:52:22 +01:00
|
|
|
link_rate = intelhaddata->link_rate;
|
2017-01-31 21:16:52 +01:00
|
|
|
|
2017-02-04 22:05:33 +01:00
|
|
|
had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
|
|
|
|
n_param, intelhaddata);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-04 22:05:33 +01:00
|
|
|
had_prog_dip(substream, intelhaddata);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-04 22:05:33 +01:00
|
|
|
retval = had_init_audio_ctrl(substream, intelhaddata);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
/* Prog buffer address */
|
2017-02-02 13:00:12 +01:00
|
|
|
retval = snd_intelhad_prog_buffer(substream, intelhaddata,
|
2017-01-24 23:57:52 +01:00
|
|
|
HAD_BUF_TYPE_A, HAD_BUF_TYPE_D);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Program channel mapping in following order:
|
|
|
|
* FL, FR, C, LFE, RL, RR
|
|
|
|
*/
|
|
|
|
|
2017-01-30 17:23:39 +01:00
|
|
|
had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
prep_end:
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* ALSA PCM pointer callback
|
2017-01-24 23:57:52 +01:00
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
struct snd_intelhad *intelhaddata;
|
|
|
|
u32 bytes_rendered = 0;
|
|
|
|
u32 t;
|
|
|
|
int buf_id;
|
|
|
|
|
|
|
|
intelhaddata = snd_pcm_substream_chip(substream);
|
|
|
|
|
2017-02-02 17:46:49 +01:00
|
|
|
if (!intelhaddata->connected)
|
2017-01-31 16:46:44 +01:00
|
|
|
return SNDRV_PCM_POS_XRUN;
|
|
|
|
|
2017-01-24 23:57:52 +01:00
|
|
|
/* Use a hw register to calculate sub-period position reports.
|
|
|
|
* This makes PulseAudio happier.
|
|
|
|
*/
|
|
|
|
|
|
|
|
buf_id = intelhaddata->curr_buf % 4;
|
2017-01-30 17:23:39 +01:00
|
|
|
had_read_register(intelhaddata,
|
|
|
|
AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH), &t);
|
2017-01-24 23:57:53 +01:00
|
|
|
|
|
|
|
if ((t == 0) || (t == ((u32)-1L))) {
|
2017-01-30 18:17:44 +01:00
|
|
|
intelhaddata->underrun_count++;
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev,
|
|
|
|
"discovered buffer done for buf %d, count = %d\n",
|
2017-01-30 18:17:44 +01:00
|
|
|
buf_id, intelhaddata->underrun_count);
|
2017-01-24 23:57:53 +01:00
|
|
|
|
2017-01-30 18:17:44 +01:00
|
|
|
if (intelhaddata->underrun_count > (HAD_MIN_PERIODS/2)) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev,
|
|
|
|
"assume audio_codec_reset, underrun = %d - do xrun\n",
|
2017-01-30 18:17:44 +01:00
|
|
|
intelhaddata->underrun_count);
|
2017-01-24 23:57:53 +01:00
|
|
|
return SNDRV_PCM_POS_XRUN;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* Reset Counter */
|
2017-01-30 18:17:44 +01:00
|
|
|
intelhaddata->underrun_count = 0;
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
2017-01-24 23:57:53 +01:00
|
|
|
|
2017-01-24 23:57:52 +01:00
|
|
|
t = intelhaddata->buf_info[buf_id].buf_size - t;
|
|
|
|
|
|
|
|
if (intelhaddata->stream_info.buffer_rendered)
|
|
|
|
div_u64_rem(intelhaddata->stream_info.buffer_rendered,
|
|
|
|
intelhaddata->stream_info.ring_buf_size,
|
|
|
|
&(bytes_rendered));
|
|
|
|
|
2017-02-01 22:25:58 +01:00
|
|
|
return bytes_to_frames(substream->runtime, bytes_rendered + t);
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/*
|
2017-02-02 17:27:40 +01:00
|
|
|
* ALSA PCM mmap callback
|
2017-01-24 23:57:52 +01:00
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static int had_pcm_mmap(struct snd_pcm_substream *substream,
|
|
|
|
struct vm_area_struct *vma)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
|
|
|
return remap_pfn_range(vma, vma->vm_start,
|
|
|
|
substream->dma_buffer.addr >> PAGE_SHIFT,
|
|
|
|
vma->vm_end - vma->vm_start, vma->vm_page_prot);
|
|
|
|
}
|
|
|
|
|
2017-02-02 17:38:50 +01:00
|
|
|
/*
|
|
|
|
* ALSA PCM ops
|
|
|
|
*/
|
2017-02-04 22:05:33 +01:00
|
|
|
static const struct snd_pcm_ops had_pcm_ops = {
|
|
|
|
.open = had_pcm_open,
|
|
|
|
.close = had_pcm_close,
|
2017-02-02 17:38:50 +01:00
|
|
|
.ioctl = snd_pcm_lib_ioctl,
|
2017-02-04 22:05:33 +01:00
|
|
|
.hw_params = had_pcm_hw_params,
|
|
|
|
.hw_free = had_pcm_hw_free,
|
|
|
|
.prepare = had_pcm_prepare,
|
|
|
|
.trigger = had_pcm_trigger,
|
|
|
|
.pointer = had_pcm_pointer,
|
|
|
|
.mmap = had_pcm_mmap,
|
2017-02-02 17:38:50 +01:00
|
|
|
};
|
|
|
|
|
2017-02-01 17:24:02 +01:00
|
|
|
/* process mode change of the running stream; called in mutex */
|
2017-02-04 22:05:33 +01:00
|
|
|
static int had_process_mode_change(struct snd_intelhad *intelhaddata)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
2017-01-31 13:52:22 +01:00
|
|
|
struct snd_pcm_substream *substream;
|
2017-01-24 23:57:52 +01:00
|
|
|
int retval = 0;
|
|
|
|
u32 disp_samp_freq, n_param;
|
2017-01-31 21:16:52 +01:00
|
|
|
u32 link_rate = 0;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-02 13:00:12 +01:00
|
|
|
substream = had_substream_get(intelhaddata);
|
|
|
|
if (!substream)
|
2017-01-31 13:52:22 +01:00
|
|
|
return 0;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
/* Disable Audio */
|
2017-02-04 22:05:33 +01:00
|
|
|
had_enable_audio(substream, intelhaddata, false);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
/* Update CTS value */
|
2017-01-31 13:52:22 +01:00
|
|
|
disp_samp_freq = intelhaddata->tmds_clock_speed;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-04 22:05:33 +01:00
|
|
|
retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
|
2017-01-24 23:57:52 +01:00
|
|
|
if (retval) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_err(intelhaddata->dev,
|
|
|
|
"programming N value failed %#x\n", retval);
|
2017-01-24 23:57:52 +01:00
|
|
|
goto out;
|
|
|
|
}
|
2017-01-31 21:16:52 +01:00
|
|
|
|
|
|
|
if (intelhaddata->dp_output)
|
2017-01-31 13:52:22 +01:00
|
|
|
link_rate = intelhaddata->link_rate;
|
2017-01-31 21:16:52 +01:00
|
|
|
|
2017-02-04 22:05:33 +01:00
|
|
|
had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
|
|
|
|
n_param, intelhaddata);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
/* Enable Audio */
|
2017-02-04 22:05:33 +01:00
|
|
|
had_enable_audio(substream, intelhaddata, true);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
out:
|
2017-02-02 13:00:12 +01:00
|
|
|
had_substream_put(intelhaddata);
|
2017-01-24 23:57:52 +01:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2017-01-31 13:57:58 +01:00
|
|
|
static inline int had_chk_intrmiss(struct snd_intelhad *intelhaddata,
|
|
|
|
enum intel_had_aud_buf_type buf_id)
|
|
|
|
{
|
|
|
|
int i, intr_count = 0;
|
|
|
|
enum intel_had_aud_buf_type buff_done;
|
|
|
|
u32 buf_size, buf_addr;
|
|
|
|
|
|
|
|
buff_done = buf_id;
|
|
|
|
|
|
|
|
intr_count = snd_intelhad_read_len(intelhaddata);
|
|
|
|
if (intr_count > 1) {
|
|
|
|
/* In case of active playback */
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_err(intelhaddata->dev,
|
|
|
|
"Driver detected %d missed buffer done interrupt(s)\n",
|
|
|
|
(intr_count - 1));
|
2017-01-31 13:57:58 +01:00
|
|
|
if (intr_count > 3)
|
|
|
|
return intr_count;
|
|
|
|
|
|
|
|
buf_id += (intr_count - 1);
|
|
|
|
/* Reprogram registers*/
|
|
|
|
for (i = buff_done; i < buf_id; i++) {
|
|
|
|
int j = i % 4;
|
|
|
|
|
|
|
|
buf_size = intelhaddata->buf_info[j].buf_size;
|
|
|
|
buf_addr = intelhaddata->buf_info[j].buf_addr;
|
|
|
|
had_write_register(intelhaddata,
|
|
|
|
AUD_BUF_A_LENGTH +
|
|
|
|
(j * HAD_REG_WIDTH), buf_size);
|
|
|
|
had_write_register(intelhaddata,
|
|
|
|
AUD_BUF_A_ADDR+(j * HAD_REG_WIDTH),
|
|
|
|
(buf_addr | BIT(0) | BIT(1)));
|
|
|
|
}
|
|
|
|
buf_id = buf_id % 4;
|
|
|
|
intelhaddata->buff_done = buf_id;
|
|
|
|
}
|
|
|
|
|
|
|
|
return intr_count;
|
|
|
|
}
|
|
|
|
|
2017-02-01 17:18:20 +01:00
|
|
|
/* called from irq handler */
|
2017-01-31 13:57:58 +01:00
|
|
|
static int had_process_buffer_done(struct snd_intelhad *intelhaddata)
|
|
|
|
{
|
|
|
|
u32 len = 1;
|
|
|
|
enum intel_had_aud_buf_type buf_id;
|
|
|
|
enum intel_had_aud_buf_type buff_done;
|
|
|
|
struct pcm_stream_info *stream;
|
2017-02-02 13:00:12 +01:00
|
|
|
struct snd_pcm_substream *substream;
|
2017-01-31 13:57:58 +01:00
|
|
|
u32 buf_size;
|
|
|
|
int intr_count;
|
2017-02-01 17:18:20 +01:00
|
|
|
unsigned long flags;
|
2017-01-31 13:57:58 +01:00
|
|
|
|
|
|
|
stream = &intelhaddata->stream_info;
|
|
|
|
intr_count = 1;
|
|
|
|
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
|
2017-02-02 17:46:49 +01:00
|
|
|
if (!intelhaddata->connected) {
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev,
|
|
|
|
"%s:Device already disconnected\n", __func__);
|
2017-01-31 13:57:58 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
buf_id = intelhaddata->curr_buf;
|
|
|
|
intelhaddata->buff_done = buf_id;
|
|
|
|
buff_done = intelhaddata->buff_done;
|
|
|
|
buf_size = intelhaddata->buf_info[buf_id].buf_size;
|
|
|
|
|
|
|
|
/* Every debug statement has an implication
|
|
|
|
* of ~5msec. Thus, avoid having >3 debug statements
|
|
|
|
* for each buffer_done handling.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Check for any intr_miss in case of active playback */
|
2017-02-02 14:57:22 +01:00
|
|
|
if (stream->running) {
|
2017-01-31 13:57:58 +01:00
|
|
|
intr_count = had_chk_intrmiss(intelhaddata, buf_id);
|
|
|
|
if (!intr_count || (intr_count > 3)) {
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_unlock_irqrestore(&intelhaddata->had_spinlock,
|
|
|
|
flags);
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_err(intelhaddata->dev,
|
|
|
|
"HAD SW state in non-recoverable mode\n");
|
2017-01-31 13:57:58 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
buf_id += (intr_count - 1);
|
|
|
|
buf_id = buf_id % 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
intelhaddata->buf_info[buf_id].is_valid = true;
|
|
|
|
if (intelhaddata->valid_buf_cnt-1 == buf_id) {
|
2017-02-02 14:57:22 +01:00
|
|
|
if (stream->running)
|
2017-01-31 13:57:58 +01:00
|
|
|
intelhaddata->curr_buf = HAD_BUF_TYPE_A;
|
|
|
|
} else
|
|
|
|
intelhaddata->curr_buf = buf_id + 1;
|
|
|
|
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
|
2017-01-31 13:57:58 +01:00
|
|
|
|
2017-02-02 17:46:49 +01:00
|
|
|
if (!intelhaddata->connected) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "HDMI cable plugged-out\n");
|
2017-01-31 13:57:58 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-31 17:09:13 +01:00
|
|
|
/* Reprogram the registers with addr and length */
|
2017-01-31 13:57:58 +01:00
|
|
|
had_write_register(intelhaddata,
|
|
|
|
AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH),
|
|
|
|
buf_size);
|
|
|
|
had_write_register(intelhaddata,
|
|
|
|
AUD_BUF_A_ADDR + (buf_id * HAD_REG_WIDTH),
|
|
|
|
intelhaddata->buf_info[buf_id].buf_addr |
|
|
|
|
BIT(0) | BIT(1));
|
|
|
|
|
|
|
|
had_read_register(intelhaddata,
|
|
|
|
AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH),
|
|
|
|
&len);
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "%s:Enabled buf[%d]\n", __func__, buf_id);
|
2017-01-31 13:57:58 +01:00
|
|
|
|
|
|
|
/* In case of actual data,
|
|
|
|
* report buffer_done to above ALSA layer
|
|
|
|
*/
|
2017-02-02 13:00:12 +01:00
|
|
|
substream = had_substream_get(intelhaddata);
|
|
|
|
if (substream) {
|
|
|
|
buf_size = intelhaddata->buf_info[buf_id].buf_size;
|
2017-01-31 13:57:58 +01:00
|
|
|
intelhaddata->stream_info.buffer_rendered +=
|
|
|
|
(intr_count * buf_size);
|
2017-02-02 13:00:12 +01:00
|
|
|
snd_pcm_period_elapsed(substream);
|
|
|
|
had_substream_put(intelhaddata);
|
2017-01-31 13:57:58 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-02-01 17:18:20 +01:00
|
|
|
/* called from irq handler */
|
2017-01-31 13:57:58 +01:00
|
|
|
static int had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
|
|
|
|
{
|
|
|
|
enum intel_had_aud_buf_type buf_id;
|
|
|
|
struct pcm_stream_info *stream;
|
2017-02-02 13:00:12 +01:00
|
|
|
struct snd_pcm_substream *substream;
|
2017-02-01 17:18:20 +01:00
|
|
|
unsigned long flags;
|
2017-02-02 17:46:49 +01:00
|
|
|
int connected;
|
2017-01-31 13:57:58 +01:00
|
|
|
|
|
|
|
stream = &intelhaddata->stream_info;
|
|
|
|
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
|
2017-01-31 13:57:58 +01:00
|
|
|
buf_id = intelhaddata->curr_buf;
|
|
|
|
intelhaddata->buff_done = buf_id;
|
2017-02-02 17:46:49 +01:00
|
|
|
connected = intelhaddata->connected;
|
2017-02-02 14:57:22 +01:00
|
|
|
if (stream->running)
|
2017-01-31 13:57:58 +01:00
|
|
|
intelhaddata->curr_buf = HAD_BUF_TYPE_A;
|
|
|
|
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
|
2017-01-31 13:57:58 +01:00
|
|
|
|
2017-02-02 14:57:22 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "Enter:%s buf_id=%d, stream_running=%d\n",
|
|
|
|
__func__, buf_id, stream->running);
|
2017-01-31 13:57:58 +01:00
|
|
|
|
|
|
|
snd_intelhad_handle_underrun(intelhaddata);
|
|
|
|
|
2017-02-02 17:46:49 +01:00
|
|
|
if (!connected) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev,
|
|
|
|
"%s:Device already disconnected\n", __func__);
|
2017-01-31 13:57:58 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-02-02 14:57:22 +01:00
|
|
|
/* Report UNDERRUN error to above layers */
|
|
|
|
substream = had_substream_get(intelhaddata);
|
|
|
|
if (substream) {
|
|
|
|
snd_pcm_stop_xrun(substream);
|
|
|
|
had_substream_put(intelhaddata);
|
2017-01-31 13:57:58 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-02-01 17:24:02 +01:00
|
|
|
/* process hot plug, called from wq with mutex locked */
|
2017-02-01 17:53:19 +01:00
|
|
|
static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
|
2017-01-31 13:57:58 +01:00
|
|
|
{
|
|
|
|
enum intel_had_aud_buf_type buf_id;
|
|
|
|
struct snd_pcm_substream *substream;
|
|
|
|
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_lock_irq(&intelhaddata->had_spinlock);
|
2017-02-02 17:46:49 +01:00
|
|
|
if (intelhaddata->connected) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "Device already connected\n");
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_unlock_irq(&intelhaddata->had_spinlock);
|
2017-02-01 17:53:19 +01:00
|
|
|
return;
|
2017-01-31 13:57:58 +01:00
|
|
|
}
|
2017-02-01 17:53:19 +01:00
|
|
|
|
2017-01-31 13:57:58 +01:00
|
|
|
buf_id = intelhaddata->curr_buf;
|
|
|
|
intelhaddata->buff_done = buf_id;
|
2017-02-02 17:46:49 +01:00
|
|
|
intelhaddata->connected = true;
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev,
|
|
|
|
"%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
|
2017-01-31 13:57:58 +01:00
|
|
|
__func__, __LINE__);
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_unlock_irq(&intelhaddata->had_spinlock);
|
2017-01-31 13:57:58 +01:00
|
|
|
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "Processing HOT_PLUG, buf_id = %d\n",
|
|
|
|
buf_id);
|
2017-01-31 13:57:58 +01:00
|
|
|
|
|
|
|
/* Safety check */
|
2017-02-02 13:00:12 +01:00
|
|
|
substream = had_substream_get(intelhaddata);
|
2017-01-31 13:57:58 +01:00
|
|
|
if (substream) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev,
|
|
|
|
"Force to stop the active stream by disconnection\n");
|
2017-01-31 13:57:58 +01:00
|
|
|
/* Set runtime->state to hw_params done */
|
|
|
|
snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP);
|
2017-02-02 13:00:12 +01:00
|
|
|
had_substream_put(intelhaddata);
|
2017-01-31 13:57:58 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
had_build_channel_allocation_map(intelhaddata);
|
|
|
|
}
|
|
|
|
|
2017-02-01 17:24:02 +01:00
|
|
|
/* process hot unplug, called from wq with mutex locked */
|
2017-02-01 17:53:19 +01:00
|
|
|
static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
|
2017-01-31 13:57:58 +01:00
|
|
|
{
|
|
|
|
enum intel_had_aud_buf_type buf_id;
|
2017-02-02 13:00:12 +01:00
|
|
|
struct snd_pcm_substream *substream;
|
2017-01-31 13:57:58 +01:00
|
|
|
|
|
|
|
buf_id = intelhaddata->curr_buf;
|
|
|
|
|
2017-02-02 13:00:12 +01:00
|
|
|
substream = had_substream_get(intelhaddata);
|
|
|
|
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_lock_irq(&intelhaddata->had_spinlock);
|
2017-01-31 13:57:58 +01:00
|
|
|
|
2017-02-02 17:46:49 +01:00
|
|
|
if (!intelhaddata->connected) {
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev, "Device already disconnected\n");
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_unlock_irq(&intelhaddata->had_spinlock);
|
2017-02-02 13:00:12 +01:00
|
|
|
goto out;
|
2017-01-31 13:57:58 +01:00
|
|
|
|
|
|
|
}
|
|
|
|
|
2017-02-01 17:53:19 +01:00
|
|
|
/* Disable Audio */
|
2017-02-04 22:05:33 +01:00
|
|
|
had_enable_audio_int(intelhaddata, false);
|
|
|
|
had_enable_audio(substream, intelhaddata, false);
|
2017-02-01 17:53:19 +01:00
|
|
|
|
2017-02-02 17:46:49 +01:00
|
|
|
intelhaddata->connected = false;
|
2017-01-31 15:49:15 +01:00
|
|
|
dev_dbg(intelhaddata->dev,
|
|
|
|
"%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
|
2017-01-31 13:57:58 +01:00
|
|
|
__func__, __LINE__);
|
2017-02-02 13:00:12 +01:00
|
|
|
spin_unlock_irq(&intelhaddata->had_spinlock);
|
2017-01-31 13:57:58 +01:00
|
|
|
|
|
|
|
/* Report to above ALSA layer */
|
2017-02-02 13:00:12 +01:00
|
|
|
if (substream)
|
|
|
|
snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP);
|
2017-01-31 13:57:58 +01:00
|
|
|
|
2017-02-02 13:00:12 +01:00
|
|
|
out:
|
|
|
|
if (substream)
|
|
|
|
had_substream_put(intelhaddata);
|
2017-01-31 13:57:58 +01:00
|
|
|
kfree(intelhaddata->chmap->chmap);
|
|
|
|
intelhaddata->chmap->chmap = NULL;
|
|
|
|
}
|
|
|
|
|
2017-02-02 17:38:50 +01:00
|
|
|
/*
|
|
|
|
* ALSA iec958 and ELD controls
|
|
|
|
*/
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
static int had_iec958_info(struct snd_kcontrol *kcontrol,
|
|
|
|
struct snd_ctl_elem_info *uinfo)
|
|
|
|
{
|
|
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
|
|
|
|
uinfo->count = 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int had_iec958_get(struct snd_kcontrol *kcontrol,
|
|
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
|
|
{
|
|
|
|
struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
|
|
|
|
|
2017-02-01 17:24:02 +01:00
|
|
|
mutex_lock(&intelhaddata->mutex);
|
2017-01-24 23:57:52 +01:00
|
|
|
ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
|
|
|
|
ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
|
|
|
|
ucontrol->value.iec958.status[2] =
|
|
|
|
(intelhaddata->aes_bits >> 16) & 0xff;
|
|
|
|
ucontrol->value.iec958.status[3] =
|
|
|
|
(intelhaddata->aes_bits >> 24) & 0xff;
|
2017-02-01 17:24:02 +01:00
|
|
|
mutex_unlock(&intelhaddata->mutex);
|
2017-01-24 23:57:52 +01:00
|
|
|
return 0;
|
|
|
|
}
|
2017-01-31 13:57:58 +01:00
|
|
|
|
2017-01-24 23:57:52 +01:00
|
|
|
static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
|
|
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
|
|
{
|
|
|
|
ucontrol->value.iec958.status[0] = 0xff;
|
|
|
|
ucontrol->value.iec958.status[1] = 0xff;
|
|
|
|
ucontrol->value.iec958.status[2] = 0xff;
|
|
|
|
ucontrol->value.iec958.status[3] = 0xff;
|
|
|
|
return 0;
|
|
|
|
}
|
2017-01-31 13:57:58 +01:00
|
|
|
|
2017-01-24 23:57:52 +01:00
|
|
|
static int had_iec958_put(struct snd_kcontrol *kcontrol,
|
|
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
|
|
{
|
|
|
|
unsigned int val;
|
|
|
|
struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
|
2017-02-01 17:24:02 +01:00
|
|
|
int changed = 0;
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
val = (ucontrol->value.iec958.status[0] << 0) |
|
|
|
|
(ucontrol->value.iec958.status[1] << 8) |
|
|
|
|
(ucontrol->value.iec958.status[2] << 16) |
|
|
|
|
(ucontrol->value.iec958.status[3] << 24);
|
2017-02-01 17:24:02 +01:00
|
|
|
mutex_lock(&intelhaddata->mutex);
|
2017-01-24 23:57:52 +01:00
|
|
|
if (intelhaddata->aes_bits != val) {
|
|
|
|
intelhaddata->aes_bits = val;
|
2017-02-01 17:24:02 +01:00
|
|
|
changed = 1;
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
2017-02-01 17:24:02 +01:00
|
|
|
mutex_unlock(&intelhaddata->mutex);
|
|
|
|
return changed;
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
|
|
|
|
2017-02-02 16:38:39 +01:00
|
|
|
static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
|
|
|
|
struct snd_ctl_elem_info *uinfo)
|
|
|
|
{
|
|
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
|
|
|
|
uinfo->count = HDMI_MAX_ELD_BYTES;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
|
|
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
|
|
{
|
|
|
|
struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
|
|
|
|
|
|
|
|
mutex_lock(&intelhaddata->mutex);
|
|
|
|
memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
|
|
|
|
HDMI_MAX_ELD_BYTES);
|
|
|
|
mutex_unlock(&intelhaddata->mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-02 17:38:50 +01:00
|
|
|
static const struct snd_kcontrol_new had_controls[] = {
|
2017-02-02 16:38:39 +01:00
|
|
|
{
|
|
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ,
|
|
|
|
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
|
|
|
|
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
|
|
|
|
.info = had_iec958_info, /* shared */
|
|
|
|
.get = had_iec958_mask_get,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
|
|
|
|
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
|
|
|
|
.info = had_iec958_info,
|
|
|
|
.get = had_iec958_get,
|
|
|
|
.put = had_iec958_put,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.access = (SNDRV_CTL_ELEM_ACCESS_READ |
|
|
|
|
SNDRV_CTL_ELEM_ACCESS_VOLATILE),
|
|
|
|
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
|
|
|
|
.name = "ELD",
|
|
|
|
.info = had_ctl_eld_info,
|
|
|
|
.get = had_ctl_eld_get,
|
|
|
|
},
|
2017-01-24 23:57:52 +01:00
|
|
|
};
|
|
|
|
|
2017-02-02 17:38:50 +01:00
|
|
|
/*
|
|
|
|
* audio interrupt handler
|
|
|
|
*/
|
2017-01-31 13:52:22 +01:00
|
|
|
static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct snd_intelhad *ctx = dev_id;
|
|
|
|
u32 audio_stat, audio_reg;
|
|
|
|
|
2017-01-31 18:14:15 +01:00
|
|
|
audio_reg = AUD_HDMI_STATUS;
|
2017-02-03 08:50:06 +01:00
|
|
|
had_read_register(ctx, audio_reg, &audio_stat);
|
2017-01-31 13:52:22 +01:00
|
|
|
|
|
|
|
if (audio_stat & HDMI_AUDIO_UNDERRUN) {
|
2017-02-03 08:50:06 +01:00
|
|
|
had_write_register(ctx, audio_reg, HDMI_AUDIO_UNDERRUN);
|
2017-01-31 13:52:22 +01:00
|
|
|
had_process_buffer_underrun(ctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
|
2017-02-03 08:50:06 +01:00
|
|
|
had_write_register(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE);
|
2017-01-31 13:52:22 +01:00
|
|
|
had_process_buffer_done(ctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2017-02-02 17:38:50 +01:00
|
|
|
/*
|
|
|
|
* monitor plug/unplug notification from i915; just kick off the work
|
|
|
|
*/
|
2017-01-31 13:52:22 +01:00
|
|
|
static void notify_audio_lpe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct snd_intelhad *ctx = platform_get_drvdata(pdev);
|
|
|
|
|
2017-01-31 16:26:10 +01:00
|
|
|
schedule_work(&ctx->hdmi_audio_wq);
|
|
|
|
}
|
2017-01-31 13:52:22 +01:00
|
|
|
|
2017-02-02 17:38:50 +01:00
|
|
|
/* the work to handle monitor hot plug/unplug */
|
2017-01-31 16:26:10 +01:00
|
|
|
static void had_audio_wq(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct snd_intelhad *ctx =
|
|
|
|
container_of(work, struct snd_intelhad, hdmi_audio_wq);
|
|
|
|
struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
|
2017-01-31 13:52:22 +01:00
|
|
|
|
2017-02-02 14:43:39 +01:00
|
|
|
pm_runtime_get_sync(ctx->dev);
|
2017-02-01 17:24:02 +01:00
|
|
|
mutex_lock(&ctx->mutex);
|
2017-01-31 16:26:10 +01:00
|
|
|
if (!pdata->hdmi_connected) {
|
|
|
|
dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n",
|
|
|
|
__func__);
|
2017-02-02 16:38:39 +01:00
|
|
|
memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
|
2017-02-01 17:53:19 +01:00
|
|
|
had_process_hot_unplug(ctx);
|
2017-01-31 13:52:22 +01:00
|
|
|
} else {
|
|
|
|
struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld;
|
|
|
|
|
2017-02-01 17:53:19 +01:00
|
|
|
dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
|
|
|
|
__func__, eld->port_id, pdata->tmds_clock_speed);
|
|
|
|
|
2017-01-31 13:52:22 +01:00
|
|
|
switch (eld->pipe_id) {
|
|
|
|
case 0:
|
|
|
|
ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
ctx->had_config_offset = AUDIO_HDMI_CONFIG_B;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
ctx->had_config_offset = AUDIO_HDMI_CONFIG_C;
|
|
|
|
break;
|
|
|
|
default:
|
2017-01-31 16:26:10 +01:00
|
|
|
dev_dbg(ctx->dev, "Invalid pipe %d\n",
|
2017-01-31 13:52:22 +01:00
|
|
|
eld->pipe_id);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-02-02 15:37:11 +01:00
|
|
|
memcpy(ctx->eld, eld->eld_data, sizeof(ctx->eld));
|
2017-01-31 13:52:22 +01:00
|
|
|
|
2017-02-01 17:53:19 +01:00
|
|
|
ctx->dp_output = pdata->dp_output;
|
|
|
|
ctx->tmds_clock_speed = pdata->tmds_clock_speed;
|
|
|
|
ctx->link_rate = pdata->link_rate;
|
2017-01-31 13:52:22 +01:00
|
|
|
|
2017-02-01 17:53:19 +01:00
|
|
|
had_process_hot_plug(ctx);
|
2017-01-31 13:52:22 +01:00
|
|
|
|
2017-02-01 17:53:19 +01:00
|
|
|
/* Process mode change if stream is active */
|
2017-02-04 22:05:33 +01:00
|
|
|
had_process_mode_change(ctx);
|
2017-01-31 13:52:22 +01:00
|
|
|
}
|
2017-02-01 17:24:02 +01:00
|
|
|
mutex_unlock(&ctx->mutex);
|
2017-02-02 14:43:39 +01:00
|
|
|
pm_runtime_put(ctx->dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PM callbacks
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int hdmi_lpe_audio_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct snd_intelhad *ctx = dev_get_drvdata(dev);
|
|
|
|
struct snd_pcm_substream *substream;
|
|
|
|
|
|
|
|
substream = had_substream_get(ctx);
|
|
|
|
if (substream) {
|
|
|
|
snd_pcm_suspend(substream);
|
|
|
|
had_substream_put(ctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hdmi_lpe_audio_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct snd_intelhad *ctx = dev_get_drvdata(dev);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = hdmi_lpe_audio_runtime_suspend(dev);
|
|
|
|
if (!err)
|
|
|
|
snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D3hot);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hdmi_lpe_audio_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct snd_intelhad *ctx = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D0);
|
|
|
|
return 0;
|
2017-01-31 13:52:22 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* release resources */
|
|
|
|
static void hdmi_lpe_audio_free(struct snd_card *card)
|
|
|
|
{
|
|
|
|
struct snd_intelhad *ctx = card->private_data;
|
|
|
|
|
2017-01-31 16:26:10 +01:00
|
|
|
cancel_work_sync(&ctx->hdmi_audio_wq);
|
|
|
|
|
2017-01-31 13:52:22 +01:00
|
|
|
if (ctx->mmio_start)
|
|
|
|
iounmap(ctx->mmio_start);
|
|
|
|
if (ctx->irq >= 0)
|
|
|
|
free_irq(ctx->irq, ctx);
|
|
|
|
}
|
|
|
|
|
2017-01-30 17:23:39 +01:00
|
|
|
/*
|
2017-01-31 13:52:22 +01:00
|
|
|
* hdmi_lpe_audio_probe - start bridge with i915
|
2017-01-24 23:57:52 +01:00
|
|
|
*
|
2017-01-31 13:52:22 +01:00
|
|
|
* This function is called when the i915 driver creates the
|
2017-01-31 17:09:13 +01:00
|
|
|
* hdmi-lpe-audio platform device.
|
2017-01-24 23:57:52 +01:00
|
|
|
*/
|
2017-01-31 13:52:22 +01:00
|
|
|
static int hdmi_lpe_audio_probe(struct platform_device *pdev)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
|
|
|
struct snd_card *card;
|
2017-01-31 13:52:22 +01:00
|
|
|
struct snd_intelhad *ctx;
|
|
|
|
struct snd_pcm *pcm;
|
|
|
|
struct intel_hdmi_lpe_audio_pdata *pdata;
|
|
|
|
int irq;
|
|
|
|
struct resource *res_mmio;
|
2017-02-02 16:38:39 +01:00
|
|
|
int i, ret;
|
2017-01-31 13:52:22 +01:00
|
|
|
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
|
|
if (!pdata) {
|
|
|
|
dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-01-31 13:52:22 +01:00
|
|
|
/* get resources */
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0) {
|
|
|
|
dev_err(&pdev->dev, "Could not get irq resource\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!res_mmio) {
|
|
|
|
dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-01-31 08:14:34 +01:00
|
|
|
/* create a card instance with ALSA framework */
|
2017-01-31 13:52:22 +01:00
|
|
|
ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
|
|
|
|
THIS_MODULE, sizeof(*ctx), &card);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ctx = card->private_data;
|
|
|
|
spin_lock_init(&ctx->had_spinlock);
|
2017-02-01 17:24:02 +01:00
|
|
|
mutex_init(&ctx->mutex);
|
2017-02-02 17:46:49 +01:00
|
|
|
ctx->connected = false;
|
2017-01-31 13:52:22 +01:00
|
|
|
ctx->dev = &pdev->dev;
|
|
|
|
ctx->card = card;
|
|
|
|
ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF;
|
|
|
|
strcpy(card->driver, INTEL_HAD);
|
|
|
|
strcpy(card->shortname, INTEL_HAD);
|
|
|
|
|
|
|
|
ctx->irq = -1;
|
|
|
|
ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5;
|
2017-01-31 16:26:10 +01:00
|
|
|
INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
|
2017-01-31 13:52:22 +01:00
|
|
|
|
|
|
|
card->private_free = hdmi_lpe_audio_free;
|
|
|
|
|
|
|
|
/* assume pipe A as default */
|
|
|
|
ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, ctx);
|
|
|
|
|
|
|
|
dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
|
|
|
|
__func__, (unsigned int)res_mmio->start,
|
|
|
|
(unsigned int)res_mmio->end);
|
|
|
|
|
|
|
|
ctx->mmio_start = ioremap_nocache(res_mmio->start,
|
|
|
|
(size_t)(resource_size(res_mmio)));
|
|
|
|
if (!ctx->mmio_start) {
|
|
|
|
dev_err(&pdev->dev, "Could not get ioremap\n");
|
|
|
|
ret = -EACCES;
|
|
|
|
goto err;
|
|
|
|
}
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-01-31 13:52:22 +01:00
|
|
|
/* setup interrupt handler */
|
|
|
|
ret = request_irq(irq, display_pipe_interrupt_handler, 0,
|
|
|
|
pdev->name, ctx);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "request_irq failed\n");
|
|
|
|
goto err;
|
|
|
|
}
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-01-31 13:52:22 +01:00
|
|
|
ctx->irq = irq;
|
|
|
|
|
|
|
|
ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS,
|
|
|
|
MAX_CAP_STREAMS, &pcm);
|
|
|
|
if (ret)
|
2017-01-24 23:57:52 +01:00
|
|
|
goto err;
|
|
|
|
|
|
|
|
/* setup private data which can be retrieved when required */
|
2017-01-31 13:52:22 +01:00
|
|
|
pcm->private_data = ctx;
|
2017-01-24 23:57:52 +01:00
|
|
|
pcm->info_flags = 0;
|
|
|
|
strncpy(pcm->name, card->shortname, strlen(card->shortname));
|
2017-01-31 13:52:22 +01:00
|
|
|
/* setup the ops for playabck */
|
2017-02-04 22:05:33 +01:00
|
|
|
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
|
2017-02-02 22:03:22 +01:00
|
|
|
|
|
|
|
/* only 32bit addressable */
|
|
|
|
dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
|
|
|
|
dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
|
|
|
|
|
2017-01-24 23:57:52 +01:00
|
|
|
/* allocate dma pages for ALSA stream operations
|
|
|
|
* memory allocated is based on size, not max value
|
|
|
|
* thus using same argument for max & size
|
|
|
|
*/
|
2017-01-31 13:52:22 +01:00
|
|
|
snd_pcm_lib_preallocate_pages_for_all(pcm,
|
2017-01-24 23:57:52 +01:00
|
|
|
SNDRV_DMA_TYPE_DEV, NULL,
|
|
|
|
HAD_MAX_BUFFER, HAD_MAX_BUFFER);
|
|
|
|
|
2017-02-02 16:38:39 +01:00
|
|
|
/* create controls */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
|
|
|
|
ret = snd_ctl_add(card, snd_ctl_new1(&had_controls[i], ctx));
|
|
|
|
if (ret < 0)
|
|
|
|
goto err;
|
|
|
|
}
|
2017-01-24 23:57:52 +01:00
|
|
|
|
|
|
|
init_channel_allocations();
|
|
|
|
|
|
|
|
/* Register channel map controls */
|
2017-01-31 13:52:22 +01:00
|
|
|
ret = had_register_chmap_ctls(ctx, pcm);
|
|
|
|
if (ret < 0)
|
2017-01-24 23:57:52 +01:00
|
|
|
goto err;
|
|
|
|
|
2017-01-31 13:52:22 +01:00
|
|
|
ret = snd_card_register(card);
|
|
|
|
if (ret)
|
2017-01-31 08:47:05 +01:00
|
|
|
goto err;
|
|
|
|
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_lock_irq(&pdata->lpe_audio_slock);
|
2017-01-31 13:52:22 +01:00
|
|
|
pdata->notify_audio_lpe = notify_audio_lpe;
|
2017-01-31 16:26:10 +01:00
|
|
|
pdata->notify_pending = false;
|
2017-02-01 17:18:20 +01:00
|
|
|
spin_unlock_irq(&pdata->lpe_audio_slock);
|
2017-01-31 13:52:22 +01:00
|
|
|
|
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
2017-01-31 16:26:10 +01:00
|
|
|
dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
|
2017-01-31 13:52:22 +01:00
|
|
|
schedule_work(&ctx->hdmi_audio_wq);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-01-30 17:23:39 +01:00
|
|
|
return 0;
|
2017-01-31 08:14:34 +01:00
|
|
|
|
2017-01-24 23:57:52 +01:00
|
|
|
err:
|
|
|
|
snd_card_free(card);
|
2017-01-31 13:52:22 +01:00
|
|
|
return ret;
|
2017-01-24 23:57:52 +01:00
|
|
|
}
|
|
|
|
|
2017-01-30 17:23:39 +01:00
|
|
|
/*
|
2017-01-31 13:52:22 +01:00
|
|
|
* hdmi_lpe_audio_remove - stop bridge with i915
|
2017-01-24 23:57:52 +01:00
|
|
|
*
|
2017-01-31 17:09:13 +01:00
|
|
|
* This function is called when the platform device is destroyed.
|
2017-01-24 23:57:52 +01:00
|
|
|
*/
|
2017-01-31 13:52:22 +01:00
|
|
|
static int hdmi_lpe_audio_remove(struct platform_device *pdev)
|
2017-01-24 23:57:52 +01:00
|
|
|
{
|
2017-01-31 13:52:22 +01:00
|
|
|
struct snd_intelhad *ctx = platform_get_drvdata(pdev);
|
2017-01-24 23:57:52 +01:00
|
|
|
|
2017-02-02 17:46:49 +01:00
|
|
|
if (ctx->connected)
|
2017-02-04 22:05:33 +01:00
|
|
|
had_enable_audio_int(ctx, false);
|
2017-01-31 13:52:22 +01:00
|
|
|
snd_card_free(ctx->card);
|
2017-01-24 23:57:52 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-02-02 14:43:39 +01:00
|
|
|
static const struct dev_pm_ops hdmi_lpe_audio_pm = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
|
|
|
|
SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend, NULL, NULL)
|
|
|
|
};
|
|
|
|
|
2017-01-31 13:52:22 +01:00
|
|
|
static struct platform_driver hdmi_lpe_audio_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "hdmi-lpe-audio",
|
2017-02-02 14:43:39 +01:00
|
|
|
.pm = &hdmi_lpe_audio_pm,
|
2017-01-31 13:52:22 +01:00
|
|
|
},
|
|
|
|
.probe = hdmi_lpe_audio_probe,
|
|
|
|
.remove = hdmi_lpe_audio_remove,
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(hdmi_lpe_audio_driver);
|
|
|
|
MODULE_ALIAS("platform:hdmi_lpe_audio");
|
|
|
|
|
2017-01-24 23:57:52 +01:00
|
|
|
MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
|
|
|
|
MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
|
|
|
|
MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
|
|
|
|
MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
|
|
|
|
MODULE_DESCRIPTION("Intel HDMI Audio driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");
|